/[qemu]/qemu/cpu-i386.h
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revision 1.32 by bellard, Sat Jun 21 13:09:53 2003 UTC revision 1.33 by bellard, Tue Jun 24 13:23:43 2003 UTC
# Line 50  Line 50 
50    
51  /* segment descriptor fields */  /* segment descriptor fields */
52  #define DESC_G_MASK     (1 << 23)  #define DESC_G_MASK     (1 << 23)
53  #define DESC_B_MASK     (1 << 22)  #define DESC_B_SHIFT    22
54    #define DESC_B_MASK     (1 << DESC_B_SHIFT)
55  #define DESC_AVL_MASK   (1 << 20)  #define DESC_AVL_MASK   (1 << 20)
56  #define DESC_P_MASK     (1 << 15)  #define DESC_P_MASK     (1 << 15)
57  #define DESC_DPL_SHIFT  13  #define DESC_DPL_SHIFT  13
# Line 95  Line 96 
96  #define CR4_PVI_MASK  (1 << 1)  #define CR4_PVI_MASK  (1 << 1)
97  #define CR4_TSD_MASK  (1 << 2)  #define CR4_TSD_MASK  (1 << 2)
98  #define CR4_DE_MASK   (1 << 3)  #define CR4_DE_MASK   (1 << 3)
99    #define CR4_PSE_MASK  (1 << 4)
100    
101    #define PG_PRESENT_BIT  0
102    #define PG_RW_BIT       1
103    #define PG_USER_BIT     2
104    #define PG_PWT_BIT      3
105    #define PG_PCD_BIT      4
106    #define PG_ACCESSED_BIT 5
107    #define PG_DIRTY_BIT    6
108    #define PG_PSE_BIT      7
109    #define PG_GLOBAL_BIT   8
110    
111    #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
112    #define PG_RW_MASK       (1 << PG_RW_BIT)
113    #define PG_USER_MASK     (1 << PG_USER_BIT)
114    #define PG_PWT_MASK      (1 << PG_PWT_BIT)
115    #define PG_PCD_MASK      (1 << PG_PCD_BIT)
116    #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
117    #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
118    #define PG_PSE_MASK      (1 << PG_PSE_BIT)
119    #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
120    
121    #define PG_ERROR_W_BIT     1
122    
123    #define PG_ERROR_P_MASK    0x01
124    #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
125    #define PG_ERROR_U_MASK    0x04
126    #define PG_ERROR_RSVD_MASK 0x08
127    
128  #define EXCP00_DIVZ     0  #define EXCP00_DIVZ     0
129  #define EXCP01_SSTP     1  #define EXCP01_SSTP     1
# Line 116  Line 145 
145  #define EXCP12_MCHK     18  #define EXCP12_MCHK     18
146    
147  #define EXCP_INTERRUPT  256 /* async interruption */  #define EXCP_INTERRUPT  256 /* async interruption */
148    #define EXCP_HLT        257 /* hlt instruction reached */
149    
150  enum {  enum {
151      CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */      CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
# Line 174  typedef double CPU86_LDouble; Line 204  typedef double CPU86_LDouble;
204  typedef struct SegmentCache {  typedef struct SegmentCache {
205      uint32_t selector;      uint32_t selector;
206      uint8_t *base;      uint8_t *base;
207      unsigned long limit;      uint32_t limit;
208      uint8_t seg_32bit;      uint32_t flags;
209  } SegmentCache;  } SegmentCache;
210    
211  typedef struct CPUX86State {  typedef struct CPUX86State {
# Line 219  typedef struct CPUX86State { Line 249  typedef struct CPUX86State {
249      jmp_buf jmp_env;      jmp_buf jmp_env;
250      int exception_index;      int exception_index;
251      int error_code;      int error_code;
252        int exception_is_int;
253        int exception_next_eip;
254    
255      uint32_t cr[5]; /* NOTE: cr1 is unused */      uint32_t cr[5]; /* NOTE: cr1 is unused */
256      uint32_t dr[8]; /* debug registers */      uint32_t dr[8]; /* debug registers */
257      int interrupt_request;      int interrupt_request; /* if true, will exit from cpu_exec() ASAP */
258        /* if true, will call cpu_x86_get_pic_interrupt() ASAP to get the
259           request interrupt number */
260        int hard_interrupt_request;
261        int user_mode_only; /* user mode only simulation */
262    
263      /* user data */      /* user data */
264      void *opaque;      void *opaque;
# Line 240  CPUX86State *cpu_x86_init(void); Line 277  CPUX86State *cpu_x86_init(void);
277  int cpu_x86_exec(CPUX86State *s);  int cpu_x86_exec(CPUX86State *s);
278  void cpu_x86_interrupt(CPUX86State *s);  void cpu_x86_interrupt(CPUX86State *s);
279  void cpu_x86_close(CPUX86State *s);  void cpu_x86_close(CPUX86State *s);
280    int cpu_x86_get_pic_interrupt(CPUX86State *s);
281    
282  /* needed to load some predefinied segment registers */  /* needed to load some predefinied segment registers */
283  void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);  void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
# Line 255  struct siginfo; Line 293  struct siginfo;
293  int cpu_x86_signal_handler(int host_signum, struct siginfo *info,  int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
294                             void *puc);                             void *puc);
295    
296    /* MMU defines */
297    void cpu_x86_init_mmu(CPUX86State *env);
298    extern CPUX86State *global_env;
299    extern int phys_ram_size;
300    extern int phys_ram_fd;
301    extern uint8_t *phys_ram_base;
302    
303  /* used to debug */  /* used to debug */
304  #define X86_DUMP_FPU  0x0001 /* dump FPU state too */  #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
305  #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */  #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */

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