/[qemu]/qemu/cpu-exec.c
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revision 1.56 by bellard, Sat Jul 2 14:31:34 2005 UTC revision 1.57 by bellard, Sat Jul 2 14:56:31 2005 UTC
# Line 182  int cpu_exec(CPUState *env1) Line 182  int cpu_exec(CPUState *env1)
182      saved_regwptr = REGWPTR;      saved_regwptr = REGWPTR;
183  #endif  #endif
184  #elif defined(TARGET_PPC)  #elif defined(TARGET_PPC)
185    #elif defined(TARGET_MIPS)
186  #else  #else
187  #error unsupported target CPU  #error unsupported target CPU
188  #endif  #endif
# Line 220  int cpu_exec(CPUState *env1) Line 221  int cpu_exec(CPUState *env1)
221                                   env->exception_next_eip, 0);                                   env->exception_next_eip, 0);
222  #elif defined(TARGET_PPC)  #elif defined(TARGET_PPC)
223                      do_interrupt(env);                      do_interrupt(env);
224    #elif defined(TARGET_MIPS)
225                        do_interrupt(env);
226  #elif defined(TARGET_SPARC)  #elif defined(TARGET_SPARC)
227                      do_interrupt(env->exception_index);                      do_interrupt(env->exception_index);
228  #endif  #endif
# Line 301  int cpu_exec(CPUState *env1) Line 304  int cpu_exec(CPUState *env1)
304                              env->interrupt_request &= ~CPU_INTERRUPT_TIMER;                              env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
305                          }                          }
306                      }                      }
307    #elif defined(TARGET_MIPS)
308                        if ((interrupt_request & CPU_INTERRUPT_HARD) &&
309                            (env->CP0_Status & (1 << CP0St_IE)) &&
310                            (env->CP0_Cause & 0x0000FC00) &&
311                            !(env->hflags & MIPS_HFLAG_EXL) &&
312                            !(env->hflags & MIPS_HFLAG_ERL) &&
313                            !(env->hflags & MIPS_HFLAG_DM)) {
314                            /* Raise it */
315                            env->exception_index = EXCP_EXT_INTERRUPT;
316                            env->error_code = 0;
317                            do_interrupt(env);
318                            env->interrupt_request &= ~CPU_INTERRUPT_HARD;
319                        }
320  #elif defined(TARGET_SPARC)  #elif defined(TARGET_SPARC)
321                      if ((interrupt_request & CPU_INTERRUPT_HARD) &&                      if ((interrupt_request & CPU_INTERRUPT_HARD) &&
322                          (env->psret != 0)) {                          (env->psret != 0)) {
# Line 376  int cpu_exec(CPUState *env1) Line 392  int cpu_exec(CPUState *env1)
392                      cpu_dump_state(env, logfile, fprintf, 0);                      cpu_dump_state(env, logfile, fprintf, 0);
393  #elif defined(TARGET_PPC)  #elif defined(TARGET_PPC)
394                      cpu_dump_state(env, logfile, fprintf, 0);                      cpu_dump_state(env, logfile, fprintf, 0);
395    #elif defined(TARGET_MIPS)
396                        cpu_dump_state(env, logfile, fprintf, 0);
397  #else  #else
398  #error unsupported target CPU  #error unsupported target CPU
399  #endif  #endif
# Line 407  int cpu_exec(CPUState *env1) Line 425  int cpu_exec(CPUState *env1)
425                      (msr_se << MSR_SE) | (msr_le << MSR_LE);                      (msr_se << MSR_SE) | (msr_le << MSR_LE);
426                  cs_base = 0;                  cs_base = 0;
427                  pc = env->nip;                  pc = env->nip;
428    #elif defined(TARGET_MIPS)
429                    flags = env->hflags & MIPS_HFLAGS_TMASK;
430                    cs_base = NULL;
431                    pc = env->PC;
432  #else  #else
433  #error unsupported CPU  #error unsupported CPU
434  #endif  #endif
# Line 684  int cpu_exec(CPUState *env1) Line 706  int cpu_exec(CPUState *env1)
706      REGWPTR = saved_regwptr;      REGWPTR = saved_regwptr;
707  #endif  #endif
708  #elif defined(TARGET_PPC)  #elif defined(TARGET_PPC)
709    #elif defined(TARGET_MIPS)
710  #else  #else
711  #error unsupported target CPU  #error unsupported target CPU
712  #endif  #endif
# Line 935  static inline int handle_cpu_signal(unsi Line 958  static inline int handle_cpu_signal(unsi
958      /* never comes here */      /* never comes here */
959      return 1;      return 1;
960  }  }
961    
962    #elif defined (TARGET_MIPS)
963    static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
964                                        int is_write, sigset_t *old_set,
965                                        void *puc)
966    {
967        TranslationBlock *tb;
968        int ret;
969        
970        if (cpu_single_env)
971            env = cpu_single_env; /* XXX: find a correct solution for multithread */
972    #if defined(DEBUG_SIGNAL)
973        printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
974               pc, address, is_write, *(unsigned long *)old_set);
975    #endif
976        /* XXX: locking issue */
977        if (is_write && page_unprotect(address, pc, puc)) {
978            return 1;
979        }
980    
981        /* see if it is an MMU fault */
982        ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
983        if (ret < 0)
984            return 0; /* not an MMU fault */
985        if (ret == 0)
986            return 1; /* the MMU fault was handled without causing real CPU fault */
987    
988        /* now we have a real cpu fault */
989        tb = tb_find_pc(pc);
990        if (tb) {
991            /* the PC is inside the translated code. It means that we have
992               a virtual CPU fault */
993            cpu_restore_state(tb, env, pc, puc);
994        }
995        if (ret == 1) {
996    #if 0
997            printf("PF exception: NIP=0x%08x error=0x%x %p\n",
998                   env->nip, env->error_code, tb);
999    #endif
1000        /* we restore the process signal mask as the sigreturn should
1001           do it (XXX: use sigsetjmp) */
1002            sigprocmask(SIG_SETMASK, old_set, NULL);
1003            do_raise_exception_err(env->exception_index, env->error_code);
1004        } else {
1005            /* activate soft MMU for this block */
1006            cpu_resume_from_signal(env, puc);
1007        }
1008        /* never comes here */
1009        return 1;
1010    }
1011    
1012  #else  #else
1013  #error unsupported target CPU  #error unsupported target CPU
1014  #endif  #endif

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