71 |
#ifdef __sparc__ |
#ifdef __sparc__ |
72 |
int saved_i7, tmp_T0; |
int saved_i7, tmp_T0; |
73 |
#endif |
#endif |
74 |
int code_gen_size, ret; |
int code_gen_size, ret, interrupt_request; |
75 |
void (*gen_func)(void); |
void (*gen_func)(void); |
76 |
TranslationBlock *tb, **ptb; |
TranslationBlock *tb, **ptb; |
77 |
uint8_t *tc_ptr, *cs_base, *pc; |
uint8_t *tc_ptr, *cs_base, *pc; |
139 |
#else |
#else |
140 |
#error unsupported target CPU |
#error unsupported target CPU |
141 |
#endif |
#endif |
|
env->interrupt_request = 0; |
|
142 |
env->exception_index = -1; |
env->exception_index = -1; |
143 |
|
|
144 |
/* prepare setjmp context for exception handling */ |
/* prepare setjmp context for exception handling */ |
175 |
} |
} |
176 |
env->exception_index = -1; |
env->exception_index = -1; |
177 |
} |
} |
|
#if defined(TARGET_I386) |
|
|
/* if hardware interrupt pending, we execute it */ |
|
|
if (env->hard_interrupt_request && |
|
|
(env->eflags & IF_MASK)) { |
|
|
int intno; |
|
|
intno = cpu_x86_get_pic_interrupt(env); |
|
|
if (loglevel) { |
|
|
fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
|
|
} |
|
|
do_interrupt(intno, 0, 0, 0); |
|
|
env->hard_interrupt_request = 0; |
|
|
} |
|
|
#endif |
|
178 |
T0 = 0; /* force lookup of first TB */ |
T0 = 0; /* force lookup of first TB */ |
179 |
for(;;) { |
for(;;) { |
180 |
#ifdef __sparc__ |
#ifdef __sparc__ |
181 |
/* g1 can be modified by some libc? functions */ |
/* g1 can be modified by some libc? functions */ |
182 |
tmp_T0 = T0; |
tmp_T0 = T0; |
183 |
#endif |
#endif |
184 |
if (env->interrupt_request) { |
interrupt_request = env->interrupt_request; |
185 |
env->exception_index = EXCP_INTERRUPT; |
if (interrupt_request) { |
186 |
cpu_loop_exit(); |
#if defined(TARGET_I386) |
187 |
|
/* if hardware interrupt pending, we execute it */ |
188 |
|
if ((interrupt_request & CPU_INTERRUPT_HARD) && |
189 |
|
(env->eflags & IF_MASK)) { |
190 |
|
int intno; |
191 |
|
intno = cpu_x86_get_pic_interrupt(env); |
192 |
|
if (loglevel) { |
193 |
|
fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
194 |
|
} |
195 |
|
do_interrupt(intno, 0, 0, 0); |
196 |
|
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
197 |
|
} |
198 |
|
#endif |
199 |
|
if (interrupt_request & CPU_INTERRUPT_EXIT) { |
200 |
|
env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
201 |
|
env->exception_index = EXCP_INTERRUPT; |
202 |
|
cpu_loop_exit(); |
203 |
|
} |
204 |
} |
} |
205 |
#ifdef DEBUG_EXEC |
#ifdef DEBUG_EXEC |
206 |
if (loglevel) { |
if (loglevel) { |
215 |
env->regs[R_EBP] = EBP; |
env->regs[R_EBP] = EBP; |
216 |
env->regs[R_ESP] = ESP; |
env->regs[R_ESP] = ESP; |
217 |
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
218 |
cpu_x86_dump_state(env, logfile, 0); |
cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP); |
219 |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
220 |
#elif defined(TARGET_ARM) |
#elif defined(TARGET_ARM) |
221 |
cpu_arm_dump_state(env, logfile, 0); |
cpu_arm_dump_state(env, logfile, 0); |
457 |
{ |
{ |
458 |
TranslationBlock *tb; |
TranslationBlock *tb; |
459 |
int ret; |
int ret; |
460 |
|
|
461 |
if (cpu_single_env) |
if (cpu_single_env) |
462 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
463 |
#if defined(DEBUG_SIGNAL) |
#if defined(DEBUG_SIGNAL) |