182 |
tmp_T0 = T0; |
tmp_T0 = T0; |
183 |
#endif |
#endif |
184 |
interrupt_request = env->interrupt_request; |
interrupt_request = env->interrupt_request; |
185 |
if (interrupt_request) { |
if (__builtin_expect(interrupt_request, 0)) { |
186 |
#if defined(TARGET_I386) |
#if defined(TARGET_I386) |
187 |
/* if hardware interrupt pending, we execute it */ |
/* if hardware interrupt pending, we execute it */ |
188 |
if ((interrupt_request & CPU_INTERRUPT_HARD) && |
if ((interrupt_request & CPU_INTERRUPT_HARD) && |
238 |
always be the same before a given translated block |
always be the same before a given translated block |
239 |
is executed. */ |
is executed. */ |
240 |
#if defined(TARGET_I386) |
#if defined(TARGET_I386) |
241 |
flags = (env->segs[R_CS].flags & DESC_B_MASK) |
flags = env->hflags; |
|
>> (DESC_B_SHIFT - HF_CS32_SHIFT); |
|
|
flags |= (env->segs[R_SS].flags & DESC_B_MASK) |
|
|
>> (DESC_B_SHIFT - HF_SS32_SHIFT); |
|
|
flags |= (((unsigned long)env->segs[R_DS].base | |
|
|
(unsigned long)env->segs[R_ES].base | |
|
|
(unsigned long)env->segs[R_SS].base) != 0) << |
|
|
HF_ADDSEG_SHIFT; |
|
|
flags |= env->hflags; |
|
242 |
flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
243 |
cs_base = env->segs[R_CS].base; |
cs_base = env->segs[R_CS].base; |
244 |
pc = cs_base + env->eip; |
pc = cs_base + env->eip; |
394 |
saved_env = env; |
saved_env = env; |
395 |
env = s; |
env = s; |
396 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
|
SegmentCache *sc; |
|
397 |
selector &= 0xffff; |
selector &= 0xffff; |
398 |
sc = &env->segs[seg_reg]; |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
399 |
sc->base = (void *)(selector << 4); |
(uint8_t *)(selector << 4), 0xffff, 0); |
|
sc->limit = 0xffff; |
|
|
sc->flags = 0; |
|
|
sc->selector = selector; |
|
400 |
} else { |
} else { |
401 |
load_seg(seg_reg, selector, 0); |
load_seg(seg_reg, selector, 0); |
402 |
} |
} |