186 |
#if defined(TARGET_I386) |
#if defined(TARGET_I386) |
187 |
/* if hardware interrupt pending, we execute it */ |
/* if hardware interrupt pending, we execute it */ |
188 |
if ((interrupt_request & CPU_INTERRUPT_HARD) && |
if ((interrupt_request & CPU_INTERRUPT_HARD) && |
189 |
(env->eflags & IF_MASK)) { |
(env->eflags & IF_MASK) && |
190 |
|
!(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
191 |
int intno; |
int intno; |
192 |
intno = cpu_x86_get_pic_interrupt(env); |
intno = cpu_x86_get_pic_interrupt(env); |
193 |
if (loglevel) { |
if (loglevel) { |
234 |
#endif |
#endif |
235 |
} |
} |
236 |
#endif |
#endif |
237 |
/* we compute the CPU state. We assume it will not |
/* we record a subset of the CPU state. It will |
238 |
change during the whole generated block. */ |
always be the same before a given translated block |
239 |
|
is executed. */ |
240 |
#if defined(TARGET_I386) |
#if defined(TARGET_I386) |
241 |
flags = (env->segs[R_CS].flags & DESC_B_MASK) |
flags = (env->segs[R_CS].flags & DESC_B_MASK) |
242 |
>> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT); |
>> (DESC_B_SHIFT - HF_CS32_SHIFT); |
243 |
flags |= (env->segs[R_SS].flags & DESC_B_MASK) |
flags |= (env->segs[R_SS].flags & DESC_B_MASK) |
244 |
>> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT); |
>> (DESC_B_SHIFT - HF_SS32_SHIFT); |
245 |
flags |= (((unsigned long)env->segs[R_DS].base | |
flags |= (((unsigned long)env->segs[R_DS].base | |
246 |
(unsigned long)env->segs[R_ES].base | |
(unsigned long)env->segs[R_ES].base | |
247 |
(unsigned long)env->segs[R_SS].base) != 0) << |
(unsigned long)env->segs[R_SS].base) != 0) << |
248 |
GEN_FLAG_ADDSEG_SHIFT; |
HF_ADDSEG_SHIFT; |
249 |
flags |= env->cpl << GEN_FLAG_CPL_SHIFT; |
flags |= env->hflags; |
250 |
flags |= env->soft_mmu << GEN_FLAG_SOFT_MMU_SHIFT; |
flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
|
flags |= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT); |
|
|
flags |= (env->eflags & (IOPL_MASK | TF_MASK)); |
|
251 |
cs_base = env->segs[R_CS].base; |
cs_base = env->segs[R_CS].base; |
252 |
pc = cs_base + env->eip; |
pc = cs_base + env->eip; |
253 |
#elif defined(TARGET_ARM) |
#elif defined(TARGET_ARM) |
337 |
/* reset soft MMU for next block (it can currently |
/* reset soft MMU for next block (it can currently |
338 |
only be set by a memory fault) */ |
only be set by a memory fault) */ |
339 |
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) |
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) |
340 |
if (env->soft_mmu) { |
if (env->hflags & HF_SOFTMMU_MASK) { |
341 |
env->soft_mmu = 0; |
env->hflags &= ~HF_SOFTMMU_MASK; |
342 |
/* do not allow linking to another block */ |
/* do not allow linking to another block */ |
343 |
T0 = 0; |
T0 = 0; |
344 |
} |
} |
499 |
raise_exception_err(EXCP0E_PAGE, env->error_code); |
raise_exception_err(EXCP0E_PAGE, env->error_code); |
500 |
} else { |
} else { |
501 |
/* activate soft MMU for this block */ |
/* activate soft MMU for this block */ |
502 |
env->soft_mmu = 1; |
env->hflags |= HF_SOFTMMU_MASK; |
503 |
sigprocmask(SIG_SETMASK, old_set, NULL); |
sigprocmask(SIG_SETMASK, old_set, NULL); |
504 |
cpu_loop_exit(); |
cpu_loop_exit(); |
505 |
} |
} |