172 |
pc = cs_base + env->eip; |
pc = cs_base + env->eip; |
173 |
#elif defined(TARGET_ARM) |
#elif defined(TARGET_ARM) |
174 |
flags = env->thumb | (env->vfp.vec_len << 1) |
flags = env->thumb | (env->vfp.vec_len << 1) |
175 |
| (env->vfp.vec_stride << 4); |
| (env->vfp.vec_stride << 4); |
176 |
|
if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) |
177 |
|
flags |= (1 << 6); |
178 |
cs_base = 0; |
cs_base = 0; |
179 |
pc = env->regs[15]; |
pc = env->regs[15]; |
180 |
#elif defined(TARGET_SPARC) |
#elif defined(TARGET_SPARC) |
324 |
CC_OP = CC_OP_EFLAGS; |
CC_OP = CC_OP_EFLAGS; |
325 |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
326 |
#elif defined(TARGET_ARM) |
#elif defined(TARGET_ARM) |
|
{ |
|
|
unsigned int psr; |
|
|
psr = env->cpsr; |
|
|
env->CF = (psr >> 29) & 1; |
|
|
env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
|
|
env->VF = (psr << 3) & 0x80000000; |
|
|
env->QF = (psr >> 27) & 1; |
|
|
env->cpsr = psr & ~CACHED_CPSR_BITS; |
|
|
} |
|
327 |
#elif defined(TARGET_SPARC) |
#elif defined(TARGET_SPARC) |
328 |
#if defined(reg_REGWPTR) |
#if defined(reg_REGWPTR) |
329 |
saved_regwptr = REGWPTR; |
saved_regwptr = REGWPTR; |
372 |
do_interrupt(env); |
do_interrupt(env); |
373 |
#elif defined(TARGET_SPARC) |
#elif defined(TARGET_SPARC) |
374 |
do_interrupt(env->exception_index); |
do_interrupt(env->exception_index); |
375 |
|
#elif defined(TARGET_ARM) |
376 |
|
do_interrupt(env); |
377 |
#endif |
#endif |
378 |
} |
} |
379 |
env->exception_index = -1; |
env->exception_index = -1; |
503 |
//do_interrupt(0, 0, 0, 0, 0); |
//do_interrupt(0, 0, 0, 0, 0); |
504 |
env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
505 |
} |
} |
506 |
|
#elif defined(TARGET_ARM) |
507 |
|
if (interrupt_request & CPU_INTERRUPT_FIQ |
508 |
|
&& !(env->uncached_cpsr & CPSR_F)) { |
509 |
|
env->exception_index = EXCP_FIQ; |
510 |
|
do_interrupt(env); |
511 |
|
} |
512 |
|
if (interrupt_request & CPU_INTERRUPT_HARD |
513 |
|
&& !(env->uncached_cpsr & CPSR_I)) { |
514 |
|
env->exception_index = EXCP_IRQ; |
515 |
|
do_interrupt(env); |
516 |
|
} |
517 |
#endif |
#endif |
518 |
if (interrupt_request & CPU_INTERRUPT_EXITTB) { |
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
519 |
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
520 |
/* ensure that no TB jump will be modified as |
/* ensure that no TB jump will be modified as |
521 |
the program flow was changed */ |
the program flow was changed */ |
532 |
} |
} |
533 |
} |
} |
534 |
#ifdef DEBUG_EXEC |
#ifdef DEBUG_EXEC |
535 |
if ((loglevel & CPU_LOG_EXEC)) { |
if ((loglevel & CPU_LOG_TB_CPU)) { |
536 |
#if defined(TARGET_I386) |
#if defined(TARGET_I386) |
537 |
/* restore flags in standard format */ |
/* restore flags in standard format */ |
538 |
#ifdef reg_EAX |
#ifdef reg_EAX |
563 |
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
564 |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
565 |
#elif defined(TARGET_ARM) |
#elif defined(TARGET_ARM) |
|
env->cpsr = compute_cpsr(); |
|
566 |
cpu_dump_state(env, logfile, fprintf, 0); |
cpu_dump_state(env, logfile, fprintf, 0); |
|
env->cpsr &= ~CACHED_CPSR_BITS; |
|
567 |
#elif defined(TARGET_SPARC) |
#elif defined(TARGET_SPARC) |
568 |
REGWPTR = env->regbase + (env->cwp * 16); |
REGWPTR = env->regbase + (env->cwp * 16); |
569 |
env->regwptr = REGWPTR; |
env->regwptr = REGWPTR; |
764 |
EDI = saved_EDI; |
EDI = saved_EDI; |
765 |
#endif |
#endif |
766 |
#elif defined(TARGET_ARM) |
#elif defined(TARGET_ARM) |
|
env->cpsr = compute_cpsr(); |
|
767 |
/* XXX: Save/restore host fpu exception state?. */ |
/* XXX: Save/restore host fpu exception state?. */ |
768 |
#elif defined(TARGET_SPARC) |
#elif defined(TARGET_SPARC) |
769 |
#if defined(reg_REGWPTR) |
#if defined(reg_REGWPTR) |