/[qemu]/qemu/cpu-exec.c
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revision 1.55 by bellard, Tue Apr 26 19:33:35 2005 UTC revision 1.56 by bellard, Sat Jul 2 14:31:34 2005 UTC
# Line 47  void cpu_loop_exit(void) Line 47  void cpu_loop_exit(void)
47      longjmp(env->jmp_env, 1);      longjmp(env->jmp_env, 1);
48  }  }
49  #endif  #endif
50    #ifndef TARGET_SPARC
51    #define reg_T2
52    #endif
53    
54  /* exit the current TB from a signal handler. The host registers are  /* exit the current TB from a signal handler. The host registers are
55     restored in a state compatible with the CPU emulator     restored in a state compatible with the CPU emulator
# Line 74  void cpu_resume_from_signal(CPUState *en Line 77  void cpu_resume_from_signal(CPUState *en
77    
78  int cpu_exec(CPUState *env1)  int cpu_exec(CPUState *env1)
79  {  {
80      int saved_T0, saved_T1, saved_T2;      int saved_T0, saved_T1;
81    #if defined(reg_T2)
82        int saved_T2;
83    #endif
84      CPUState *saved_env;      CPUState *saved_env;
85    #if defined(TARGET_I386)
86  #ifdef reg_EAX  #ifdef reg_EAX
87      int saved_EAX;      int saved_EAX;
88  #endif  #endif
# Line 100  int cpu_exec(CPUState *env1) Line 107  int cpu_exec(CPUState *env1)
107  #ifdef reg_EDI  #ifdef reg_EDI
108      int saved_EDI;      int saved_EDI;
109  #endif  #endif
110    #elif defined(TARGET_SPARC)
111    #if defined(reg_REGWPTR)
112        uint32_t *saved_regwptr;
113    #endif
114    #endif
115  #ifdef __sparc__  #ifdef __sparc__
116      int saved_i7, tmp_T0;      int saved_i7, tmp_T0;
117  #endif  #endif
# Line 115  int cpu_exec(CPUState *env1) Line 127  int cpu_exec(CPUState *env1)
127      env = env1;      env = env1;
128      saved_T0 = T0;      saved_T0 = T0;
129      saved_T1 = T1;      saved_T1 = T1;
130    #if defined(reg_T2)
131      saved_T2 = T2;      saved_T2 = T2;
132    #endif
133  #ifdef __sparc__  #ifdef __sparc__
134      /* we also save i7 because longjmp may not restore it */      /* we also save i7 because longjmp may not restore it */
135      asm volatile ("mov %%i7, %0" : "=r" (saved_i7));      asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
# Line 164  int cpu_exec(CPUState *env1) Line 178  int cpu_exec(CPUState *env1)
178          env->cpsr = psr & ~CACHED_CPSR_BITS;          env->cpsr = psr & ~CACHED_CPSR_BITS;
179      }      }
180  #elif defined(TARGET_SPARC)  #elif defined(TARGET_SPARC)
181    #if defined(reg_REGWPTR)
182        saved_regwptr = REGWPTR;
183    #endif
184  #elif defined(TARGET_PPC)  #elif defined(TARGET_PPC)
185  #else  #else
186  #error unsupported target CPU  #error unsupported target CPU
# Line 354  int cpu_exec(CPUState *env1) Line 371  int cpu_exec(CPUState *env1)
371                      cpu_dump_state(env, logfile, fprintf, 0);                      cpu_dump_state(env, logfile, fprintf, 0);
372                      env->cpsr &= ~CACHED_CPSR_BITS;                      env->cpsr &= ~CACHED_CPSR_BITS;
373  #elif defined(TARGET_SPARC)  #elif defined(TARGET_SPARC)
374                      cpu_dump_state (env, logfile, fprintf, 0);                      REGWPTR = env->regbase + (env->cwp * 16);
375                        env->regwptr = REGWPTR;
376                        cpu_dump_state(env, logfile, fprintf, 0);
377  #elif defined(TARGET_PPC)  #elif defined(TARGET_PPC)
378                      cpu_dump_state(env, logfile, fprintf, 0);                      cpu_dump_state(env, logfile, fprintf, 0);
379  #else  #else
# Line 376  int cpu_exec(CPUState *env1) Line 395  int cpu_exec(CPUState *env1)
395                  cs_base = 0;                  cs_base = 0;
396                  pc = env->regs[15];                  pc = env->regs[15];
397  #elif defined(TARGET_SPARC)  #elif defined(TARGET_SPARC)
398                  flags = 0;  #ifdef TARGET_SPARC64
399                    flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
400    #else
401                    flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
402    #endif
403                  cs_base = env->npc;                  cs_base = env->npc;
404                  pc = env->pc;                  pc = env->pc;
405  #elif defined(TARGET_PPC)  #elif defined(TARGET_PPC)
# Line 657  int cpu_exec(CPUState *env1) Line 680  int cpu_exec(CPUState *env1)
680      env->cpsr = compute_cpsr();      env->cpsr = compute_cpsr();
681      /* XXX: Save/restore host fpu exception state?.  */      /* XXX: Save/restore host fpu exception state?.  */
682  #elif defined(TARGET_SPARC)  #elif defined(TARGET_SPARC)
683    #if defined(reg_REGWPTR)
684        REGWPTR = saved_regwptr;
685    #endif
686  #elif defined(TARGET_PPC)  #elif defined(TARGET_PPC)
687  #else  #else
688  #error unsupported target CPU  #error unsupported target CPU
# Line 666  int cpu_exec(CPUState *env1) Line 692  int cpu_exec(CPUState *env1)
692  #endif  #endif
693      T0 = saved_T0;      T0 = saved_T0;
694      T1 = saved_T1;      T1 = saved_T1;
695    #if defined(reg_T2)
696      T2 = saved_T2;      T2 = saved_T2;
697    #endif
698      env = saved_env;      env = saved_env;
699      return ret;      return ret;
700  }  }

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