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#define MAX_BREAKPOINTS 32 |
#define MAX_BREAKPOINTS 32 |
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#define TB_JMP_CACHE_BITS 12 |
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#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
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83 |
#define CPU_TLB_SIZE 256 |
#define CPU_TLB_SIZE 256 |
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typedef struct CPUTLBEntry { |
typedef struct CPUTLBEntry { |
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target_phys_addr_t addend; |
target_phys_addr_t addend; |
95 |
} CPUTLBEntry; |
} CPUTLBEntry; |
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#define CPU_COMMON \ |
98 |
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struct TranslationBlock *current_tb; /* currently executing TB */ \ |
99 |
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/* soft mmu support */ \ |
100 |
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/* in order to avoid passing too many arguments to the memory \ |
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write helpers, we store some rarely used information in the CPU \ |
102 |
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context) */ \ |
103 |
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unsigned long mem_write_pc; /* host pc at which the memory was \ |
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written */ \ |
105 |
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target_ulong mem_write_vaddr; /* target virtual addr at which the \ |
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memory was written */ \ |
107 |
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/* 0 = kernel, 1 = user */ \ |
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CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; \ |
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CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; \ |
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struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
111 |
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\ |
112 |
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/* from this point: preserved by CPU reset */ \ |
113 |
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/* ice debug support */ \ |
114 |
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target_ulong breakpoints[MAX_BREAKPOINTS]; \ |
115 |
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int nb_breakpoints; \ |
116 |
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int singlestep_enabled; \ |
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\ |
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/* user data */ \ |
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void *opaque; |
120 |
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121 |
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122 |
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123 |
#endif |
#endif |