#include #include #include #include #include #include #include #include #include "audioio_compat.h" #include "ac97_codec.h" #include "audio_codec.h" #include #include #define AUREAL_GET8(offs) \ ddi_get8(softstate->aureal_ac97, \ (void*) ((char*)softstate->aureal_ac97_regs + (offs))) #define AUREAL_GET16(offs) \ ddi_get16(softstate->aureal_ac97, \ (void*) ((char*)softstate->aureal_ac97_regs + (offs))) #define AUREAL_GET32(offs) \ ddi_get32(softstate->aureal_ac97, \ (void*) ((char*)softstate->aureal_ac97_regs + (offs))) #define AUREAL_PUT8(offs, val) \ ddi_put8(softstate->aureal_ac97, \ (void*) ((char*)softstate->aureal_ac97_regs + (offs)), \ (val)) #define AUREAL_PUT16(offs, val) \ ddi_put16(softstate->aureal_ac97, \ (void*) ((char*)softstate->aureal_ac97_regs + (offs)), \ (val)) #define AUREAL_PUT32(offs, val) \ ddi_put32(softstate->aureal_ac97, \ (void*) ((char*)softstate->aureal_ac97_regs + (offs)), \ (val)) #define POLL_COUNT 15 /* ADB */ #define VORTEX_ADB_CTRL 0x28400 #define VORTEX_ADB_SR 0x28400 #define VORTEX_ADB_CTRL_BASE 0x27a00 #define VORTEX_ADB_CHBASE 0x282b4 #define VORTEX_ADB_RTBASE 0x28000 #define ROUTE_MASK 0x3fff #define SOURCE_MASK 0x3f80 #define DEST_MASK 0x7f /* MIXER */ #define VORTEX_MIXER_SR 0x21f00 #define VORTEX_MIXER_CHNBASE 0x21e40 #define VORTEX_MIXER_RTBASE 0x21e00 /* MIX */ #define VORTEX_MIX_INVOL_A 0x21000 #define VORTEX_MIX_INVOL_B 0x20000 #define VORTEX_MIX_VOL_A 0x21800 #define VORTEX_MIX_VOL_B 0x8800 #define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */ #define VOL_MIX 0x80 #define VOL_MAX 0x7f /* SRC */ #define VORTEX_SRCBLOCK_SR 0x2205c #define VORTEX_SRC_SOURCE 0x29194 /* FIFO */ #define VORTEX_FIFO_ADBCTRL 0x16100 #define VORTEX_FIFO_WTCTRL 0x1600 #define FIFO_RDONLY 0x00000001 #define FIFO_CTRL 0x00000002 #define FIFO_VALID 0x00000010 #define FIFO_EMPTY 0x00000020 #define FIFO_U0 0x00001000 #define VORTEX_FIFO_ADBDATA 0x14000 #define VORTEX_FIFO_WTDATA 0x10000 /* FIFO State Constants */ #define FIFO_STOP 0 #define FIFO_START 1 #define FIFO_PAUSE 2 /* CODEC */ #define VORTEX_CODEC_CTRL 0x29184 #define VORTEX_CODEC_EN 0x29190 #define VORTEX_CODEC_CHN 0x29080 #define VORTEX_CODEC_WRITE 0x800000 #define VORTEX_CODEC_ADDSHIFT 16 #define VORTEX_CODEC_ADDMASK 0x7f0000 #define VORTEX_CODEC_DATSHIFT 0 #define VORTEX_CODEC_DATMASK 0xffff #define VORTEX_CODEC_IO 0x29188 /* DMA */ #define VORTEX_ADB_DMA_CTRL 0x27e00 /* IRQ */ #define VORTEX_IRQ_GLOB 0x2a00c #define VORTEX_IRQ_ENABLE 0x4000 #define VORTEX_IRQ_SOURCE 0x2a000 #define VORTEX_IRQ_CTRL 0x2a004 /* GAME */ #define VORTEX_CTRL 0x2880c #define CTRL_GAME_ADCMODE 0x40 #define VORTEX_GAME_LEGACY 0x28808 #define VORTEX_GAME_AXIS 0x28810 #define AXIS_SIZE 4 #define AXIS_RANGE 0x1fff #define VORTEX_FMT_STEREO 0x1 struct aureal_state { dev_info_t *dip; /* Interrupt Mutex and Cookie to Setup Interrupt Handler */ kmutex_t intr_mutex; ddi_iblock_cookie_t intr_cookie; /* Register Map that Contains Aureal Registers */ ddi_acc_handle_t aureal_ac97; struct ac97_regs *aureal_ac97_regs; /* Unused? */ ddi_acc_handle_t aureal_mixer; struct aureal_regs *aureal_mixer_regs; ddi_acc_handle_t aureal_bus; struct aureal_dma_regs *aureal_bus_regs; /* PCI Configuration Handle for PCI Register Map */ ddi_acc_handle_t pci_conf_handle; caddr_t dmadata; size_t dmalen; ddi_dma_handle_t dmahandle; ddi_acc_handle_t accdma; ddi_dma_cookie_t cookie; /* ddi_dma_addr_bind_handle */ uint_t count; /* ddi_dma_addr_bind_handle */ /* Used For Display Purposes */ uint8_t rev; /* device revision code */ char *revstr; /* pci device text string */ /* Used For Audio Support/libutil */ audiohdl_t audio_handle; audio_codec_handle_t codec_handle; int format; /* not too sure if we need this for anything */ int num_timeouts; /* these four fields used for playback */ int samples_played; int playing_stream; timeout_id_t play_timeout_id; int num_record_timeouts; int recording_stream; timeout_id_t record_timeout_id; int last_position; int dmacount; }; /* Used to describe sample byte order for the PCI card */ static struct ddi_device_acc_attr dev_sample_attr = { DDI_DEVICE_ATTR_V0, DDI_NEVERSWAP_ACC, DDI_STRICTORDER_ACC }; void vortex2_mixerinit(struct aureal_state *softstate); void vortex2_fifoinit(struct aureal_state *softstate); void vortex2_dmainit(struct aureal_state *softstate); void vortex2_srcblockinit(struct aureal_state *softstate); void vortex2_clearadbdata(struct aureal_state *softstate, int i, int x); void vortex2_addroute(struct aureal_state *softstate, unsigned char route_num, unsigned char route_location, unsigned char route_value); void vortex2_enablesamplerate(struct aureal_state *softstate, int channel, int stereo); void vortex2_setadbvalid(struct aureal_state *softstate, int value); void vortex2_enable_timer_int(struct aureal_state *softstate); void vortex2_disablefifo(struct aureal_state *softstate); void vortex2_stopfifo(struct aureal_state *softstate); void vortex2_disable_int(struct aureal_state *softstate); void vortex2_flushbuffers(struct aureal_state *softstate); int alloc_dmabuf(struct aureal_state *softstate); void dealloc_dmabuf(struct aureal_state *softstate); void vortex2_setupbuffer(struct aureal_state *softstate, unsigned long address); void vortex2_startfifo(struct aureal_state *softstate);