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<p style="text-align: center;"><font size="5" style="font-size: 20pt;">Aureal |
<h1>Aureal Vortex Sound Board Chipset Technical description.</h1> |
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Vortex Sound Board Chipset Technical description.</font></p> |
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<p><br /> |
<p class="disclaimer">This VERY preliminary. There is ABOSULUTELY NO WARRANTY about the content of this |
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document. Any corrections, addition however are gladly welcome.</p> |
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<p><font size="5" style="font-size: 20pt;"><span><font size="4" |
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style="font-size: 16pt;">This VERY preliminary.  There is ABOSULUTELY NO WARRANTY about the content of this |
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document. Any corrections, addition however are gladly welcome.</font></span></font></p> |
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<p>Author: Manuel Jander (mjander@embedded.cl)<br /> |
<p>Author: Manuel Jander (mjander@embedded.cl) |
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</p> |
</p> |
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<p><i><b><br /> |
<h3>Preamble</h3> |
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Preamble</b></i></p> |
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<p>This a mix of several separate pieces of documents, most of them part |
<p>This a mix of several separate pieces of documents, most of them part |
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of the Sourceforge and Savannah disassembling project efforts. The goal of this paper is to order and combine all |
of the Sourceforge and Savannah disassembling project efforts. The goal of this paper is to order and combine all |
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of the available information regarding this superb and historical important audio chipset. I would like to thank |
of the available information regarding this superb and historical important audio chipset. I would like to thank |
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anyone involved at the Sourceforge Aureal and the Savannah OpenVortex projects.</p> |
anyone involved at the Sourceforge Aureal and the Savannah OpenVortex projects.</p> |
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<p><br /> |
<h3>General description</h3> |
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<p><b><i>General description</i></b></p> |
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<p>The vortex architecture consists of a variety of |
<p>The vortex architecture consists of a variety of |
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modules that are connected by programmable routes. Various routes are made between the these modules to produce the |
modules that are connected by programmable routes. Various routes are made between the these modules to produce the |
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controller to a sample rate converter and then to the output codec. They can be strung together in a variety of |
controller to a sample rate converter and then to the output codec. They can be strung together in a variety of |
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ways.</p> |
ways.</p> |
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<p><img src="overview.png" |
<p><img src="overview.png" |
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align="left" /><br /> |
alt="vortex layout diagram" /> |
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Dotted lines are supposedly possible routeable audio data path. The existence and internals of the EQ and A3D |
Dotted lines are supposedly possible routeable audio data path. The existence and internals of the EQ and A3D |
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module are very uncertain, and probably we will not be able to be used, except if some former employee of Aureal |
module are very uncertain, and probably we will not be able to be used, except if some former employee of Aureal |
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Semiconductors gives us a little help.<br /> |
Semiconductors gives us a little help. |
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</p> |
</p> |
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<p>There are several i/o ports mapped to a MMIO area |
<p>There are several i/o ports mapped to a MMIO area |
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<p>There are some mayor family of ports, which will be |
<p>There are some mayor family of ports, which will be |
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described along this document in sequence</p> |
described along this document in sequence</p> |
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70 |
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71 |
<ul> |
<ul> |
72 |
<li> |
<li> |
73 |
<p>Global configuration register</p> |
Global configuration register |
74 |
</li> |
</li> |
75 |
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|
76 |
<li> |
<li> |
77 |
<p>Interrupt Control, Status and Programmable |
Interrupt Control, Status and Programmable |
78 |
Timer Interface</p> |
Timer Interface |
79 |
</li> |
</li> |
80 |
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|
81 |
<li> |
<li> |
82 |
<p>AC97 Codec I/O</p> |
AC97 Codec I/O |
83 |
</li> |
</li> |
84 |
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|
85 |
<li> |
<li> |
86 |
<p>ADB (Audio Data Bus) and WT (WaveTable)</p> |
ADB (Audio Data Bus) and WT (WaveTable) |
87 |
</li> |
</li> |
88 |
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89 |
<li> |
<li> |
90 |
<p>Routing</p> |
Routing |
91 |
</li> |
</li> |
92 |
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93 |
<li> |
<li> |
94 |
<p>Mixer</p> |
Mixer |
95 |
</li> |
</li> |
96 |
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|
97 |
<li> |
<li> |
98 |
<p>Sample Rate Converter</p> |
Sample Rate Converter |
99 |
</li> |
</li> |
100 |
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|
101 |
<li> |
<li> |
102 |
<p>DMA controller</p> |
DMA controller |
103 |
</li> |
</li> |
104 |
</ul> |
</ul> |
105 |
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106 |
<p><br /> |
<h2>Global Configuration Register</h2> |
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</p> |
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<p><br /> |
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</p> |
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<p style="page-break-before: always;"><font size="5" |
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style="font-size: 20pt;"><i><b>Global Configuration Register</b></i></font></p> |
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<p><br /> |
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</p> |
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107 |
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108 |
<p>This is a global configuration port, which contains |
<p>This is a global configuration port, which contains |
109 |
the following global configuration flags.</p> |
the following global configuration flags.</p> |
110 |
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|
111 |
<p><br /> |
<p><br /> |
112 |
</p> |
</p> |
113 |
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|
114 |
<table width="100%" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="100%" border="1" cellpadding="4" cellspacing="0"> |
115 |
<col width="52*" /> |
<col width="52*" /> |
116 |
<col width="60*" /> |
<col width="60*" /> |
117 |
<col width="68*" /> |
<col width="68*" /> |
140 |
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|
141 |
<tbody> |
<tbody> |
142 |
<tr valign="top"> |
<tr valign="top"> |
143 |
<td width="20%"> |
<td> |
144 |
<p>Enable glob. IRQ</p> |
<p>Enable glob. IRQ</p> |
145 |
</td> |
</td> |
146 |
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147 |
<td width="23%"> |
<td> |
148 |
<p align="center"><br /> |
<p align="center"><br /> |
149 |
</p> |
</p> |
150 |
</td> |
</td> |
151 |
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|
152 |
<td width="27%"> |
<td> |
153 |
<p align="center"><font face="Andale Mono">0x00004000</font></p> |
<p align="center"><font face="Andale Mono">0x00004000</font></p> |
154 |
</td> |
</td> |
155 |
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|
156 |
<td width="30%"> |
<td> |
157 |
<p align="center"><font face="Andale Mono">0x0004000</font></p> |
<p align="center"><font face="Andale Mono">0x0004000</font></p> |
158 |
</td> |
</td> |
159 |
</tr> |
</tr> |
160 |
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|
161 |
<tr valign="top"> |
<tr valign="top"> |
162 |
<td width="20%"> |
<td> |
163 |
<p>Enable MPU401</p> |
<p>Enable MPU401</p> |
164 |
</td> |
</td> |
165 |
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|
166 |
<td width="23%"> |
<td> |
167 |
<p align="center"><br /> |
<p align="center"><br /> |
168 |
</p> |
</p> |
169 |
</td> |
</td> |
170 |
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|
171 |
<td width="27%"> |
<td> |
172 |
<p align="center"><font face="Andale Mono">0x00000001</font></p> |
<p align="center"><font face="Andale Mono">0x00000001</font></p> |
173 |
</td> |
</td> |
174 |
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|
175 |
<td width="30%"> |
<td> |
176 |
<p align="center"><br /> |
<br /> |
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</p> |
|
177 |
</td> |
</td> |
178 |
</tr> |
</tr> |
179 |
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|
180 |
<tr valign="top"> |
<tr valign="top" align="center"> |
181 |
<td width="20%"> |
<td> |
182 |
<p>MIDI Legacy port<br /> |
<p>MIDI Legacy port<br /> |
183 |
    0x330 - 0x331<br /> |
    0x330 - 0x331<br /> |
184 |
    0x3xx - 0x3xx<br /> |
    0x3xx - 0x3xx<br /> |
187 |
</p> |
</p> |
188 |
</td> |
</td> |
189 |
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|
190 |
<td width="23%"> |
<td> |
191 |
<p align="center"><br /> |
<br /> |
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</p> |
|
192 |
</td> |
</td> |
193 |
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|
194 |
<td width="27%"> |
<td> |
195 |
<p align="center"><font face="Andale Mono">0x00000060<br /> |
<font face="Andale Mono">0x00000060<br /> |
196 |
</font> <font face="Andale Mono">0x00000060<br /> |
0x00000060<br /> |
197 |
</font> <font face="Andale Mono">0x00000040<br /> |
0x00000040<br /> |
198 |
</font> <font face="Andale Mono">0x00000020<br /> |
0x00000020<br /> |
199 |
</font> <font face="Andale Mono">0x00000000</font><br /> |
0x00000000</font><br /> |
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</p> |
|
200 |
</td> |
</td> |
201 |
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|
202 |
<td width="30%"> |
<td> |
203 |
<p align="center"><br /> |
<br /> |
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</p> |
|
204 |
</td> |
</td> |
205 |
</tr> |
</tr> |
206 |
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|
207 |
<tr valign="top"> |
<tr valign="top"> |
208 |
<td width="20%"> |
<td> |
209 |
<p>Enable Joystick</p> |
<p>Enable Joystick</p> |
210 |
</td> |
</td> |
211 |
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|
212 |
<td width="23%"> |
<td> |
213 |
<p align="center"><br /> |
<p align="center"><br /> |
214 |
</p> |
</p> |
215 |
</td> |
</td> |
216 |
|
|
217 |
<td width="27%"> |
<td> |
218 |
<p align="center"><font face="Andale Mono">0x00000008</font></p> |
<p align="center"><font face="Andale Mono">0x00000008</font></p> |
219 |
</td> |
</td> |
220 |
|
|
221 |
<td width="30%"> |
<td> |
222 |
<p align="center"><br /> |
<p align="center"><br /> |
223 |
</p> |
</p> |
224 |
</td> |
</td> |
225 |
</tr> |
</tr> |
226 |
|
|
227 |
<tr valign="top"> |
<tr valign="top"> |
228 |
<td width="20%"> |
<td> |
229 |
<p>Jstck. Legacy port</p> |
<p>Jstck. Legacy port</p> |
230 |
</td> |
</td> |
231 |
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|
232 |
<td width="23%"> |
<td> |
233 |
<p align="center"><br /> |
<p align="center"><br /> |
234 |
</p> |
</p> |
235 |
</td> |
</td> |
236 |
|
|
237 |
<td width="27%"> |
<td> |
238 |
<p align="center"><font face="Andale Mono">0x00000e00</font></p> |
<p align="center"><font face="Andale Mono">0x00000e00</font></p> |
239 |
</td> |
</td> |
240 |
|
|
241 |
<td width="30%"> |
<td> |
242 |
<p align="center"><br /> |
<p align="center"><br /> |
243 |
</p> |
</p> |
244 |
</td> |
</td> |
245 |
</tr> |
</tr> |
246 |
|
|
247 |
<tr valign="top"> |
<tr valign="top"> |
248 |
<td width="20%"> |
<td> |
249 |
<p>Addr (0x201, 0x207)</p> |
<p>Addr (0x201, 0x207)</p> |
250 |
</td> |
</td> |
251 |
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|
252 |
<td width="23%"> |
<td> |
253 |
<p align="center"><br /> |
<p align="center"><br /> |
254 |
</p> |
</p> |
255 |
</td> |
</td> |
256 |
|
|
257 |
<td width="27%"> |
<td> |
258 |
<p align="center"><font face="Andale Mono">(addr << 9)</font></p> |
<p align="center"><font face="Andale Mono">(addr << 9)</font></p> |
259 |
</td> |
</td> |
260 |
|
|
261 |
<td width="30%"> |
<td> |
262 |
<p align="center"><br /> |
<p align="center"><br /> |
263 |
</p> |
</p> |
264 |
</td> |
</td> |
269 |
<p><br /> |
<p><br /> |
270 |
</p> |
</p> |
271 |
<br /> |
<br /> |
272 |
<hr style="width: 100%; height: 2px;" /> |
<hr /> |
273 |
|
|
274 |
<p><font size="5" style="font-size: 20pt;"><i><b>Interrupt Control and |
<h2>Interrupt Control and |
275 |
Status Registers</b></i></font></p> |
Status Registers</h2> |
276 |
|
|
277 |
<p><br /> |
<p><br /> |
278 |
</p> |
</p> |
521 |
</tbody> |
</tbody> |
522 |
</table> |
</table> |
523 |
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<p><br /> |
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<br /> |
|
524 |
</p> |
</p> |
525 |
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|
526 |
<ul> |
<ul> |
689 |
<p><br /> |
<p><br /> |
690 |
</p> |
</p> |
691 |
|
|
692 |
<p><b><i><font size="5" style="font-size: 20pt;">AC97 |
<h2>AC97 Codec I/O</h2> |
|
Codec I/O</font></i></b></p> |
|
693 |
|
|
694 |
<p><br /> |
<p><br /> |
695 |
</p> |
</p> |
974 |
</li> |
</li> |
975 |
</ul> |
</ul> |
976 |
<br /> |
<br /> |
977 |
<hr style="width: 100%; height: 2px;" /> |
<hr /> |
978 |
|
|
979 |
<p style="page-break-before: always;"><b><i><font size="5" |
<h2>ADB and WT</h2> |
|
style="font-size: 20pt;">ADB and WT<br /> |
|
|
</font></i></b></p> |
|
980 |
|
|
981 |
<p><br /> |
<p><br /> |
982 |
There are two audio engines. The ADB engine which provides 16 channels, and the WT engine with 32 channels (48 |
There are two audio engines. The ADB engine which provides 16 channels, and the WT engine with 32 channels (48 |
998 |
<br /> |
<br /> |
999 |
<br /> |
<br /> |
1000 |
<br /> |
<br /> |
1001 |
<hr style="width: 100%; height: 2px;" /> |
<hr /> |
1002 |
<font size="5" style="font-size: 20pt;"><i><b>ADB DMA Engine</b></i></font> |
<h2>ADB DMA Engine</h2> |
|
|
|
|
<p><br /> |
|
|
</p> |
|
1003 |
|
|
1004 |
<p>This is the DMA engine that feeds the ADB engine (something). The |
<p>This is the DMA engine that feeds the ADB engine (something). The |
1005 |
ADB_CTRL and ADB_STATUS access the same internal register, but one is read only and the other is write only, |
ADB_CTRL and ADB_STATUS access the same internal register, but one is read only and the other is write only, |
1006 |
providing complete write read access with the corresponding MMIO ports.<br /> |
providing complete write read access with the corresponding MMIO ports.<br /> |
1007 |
</p> |
</p> |
1008 |
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<p><br /> |
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</p> |
|
|
|
|
1009 |
<p>Routing Addresses:<br /> |
<p>Routing Addresses:<br /> |
1010 |
<br /> |
<br /> |
1011 |
</p> |
</p> |
1340 |
|
|
1341 |
<p><br /> |
<p><br /> |
1342 |
</p> |
</p> |
1343 |
<hr style="width: 100%; height: 2px;" /> |
<hr /> |
1344 |
|
|
1345 |
<p><font size="5" style="font-size: 20pt;"><i><b>WT DMA |
<h2>WT DMA Engine</h2> |
|
Engine</b></i></font></p> |
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|
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|
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<p><br /> |
|
|
</p> |
|
1346 |
|
|
1347 |
<p>The WT DMA Engine is another audio data path presumably used for the |
<p>The WT DMA Engine is another audio data path presumably used for the |
1348 |
WaveTable engine. The WT_CTRL and WT_STATUS, same as the similar ADB registers, access the same internal register, |
WaveTable engine. The WT_CTRL and WT_STATUS, same as the similar ADB registers, access the same internal register, |
1349 |
but one is read only and the other is write only, providing complete read write access with the corresponding MMIO |
but one is read only and the other is write only, providing complete read write access with the corresponding MMIO |
1350 |
ports. In the particular case of the AU8820, these MMIO addresses are the same.</p> |
ports. In the particular case of the AU8820, these MMIO addresses are the same.</p> |
1351 |
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|
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<p align="center"><br /> |
|
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</p> |
|
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|
|
1352 |
<table width="690" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="690" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
1353 |
<col width="76" /> |
<col width="76" /> |
1354 |
<col width="98" /> |
<col width="98" /> |
1789 |
|
|
1790 |
<p style="page-break-before: always;"><br /> |
<p style="page-break-before: always;"><br /> |
1791 |
</p> |
</p> |
1792 |
<hr style="width: 100%; height: 2px;" /> |
<hr /> |
1793 |
|
|
1794 |
<p><b><i><font size="5" style="font-size: 20pt;">FIFO</font></i></b></p> |
<p><b><i><font size="5" style="font-size: 20pt;">FIFO</font></i></b></p> |
1795 |
|
|
2078 |
</p> |
</p> |
2079 |
<br /> |
<br /> |
2080 |
<br /> |
<br /> |
2081 |
<hr style="width: 100%; height: 2px;" /> |
<hr /> |
2082 |
|
|
2083 |
<p style="page-break-before: always;"><font size="5" |
<h2>Mixer</h2> |
|
style="font-size: 20pt;"><i><b>Mixer</b></i></font></p> |
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|
|
<p><br /> |
|
|
</p> |
|
2084 |
|
|
2085 |
<p>Apart of the analog mixing of the AC97 codec, several digital sound |
<p>Apart of the analog mixing of the AC97 codec, several digital sound |
2086 |
source have to be combined/mixed before sending them to the AC97 codec through the AC97 5 wire link. The same is |
source have to be combined/mixed before sending them to the AC97 codec through the AC97 5 wire link. The same is |
2302 |
|
|
2303 |
<p><br /> |
<p><br /> |
2304 |
</p> |
</p> |
2305 |
<hr style="width: 100%; height: 2px;" /> |
<hr /> |
|
|
|
|
<p><b><i><font size="5" style="font-size: 20pt;">Sample Rate |
|
|
Converter</font></i></b></p> |
|
2306 |
|
|
2307 |
<p><br /> |
<h2>Sample Rate Converter</h2> |
|
</p> |
|
2308 |
|
|
2309 |
<p>This functional block, connectible through routes, as it name states, |
<p>This functional block, connectible through routes, as it name states, |
2310 |
converts the sample rate of its incoming audio data, you guess it, to 48KHz, the sample rate of the AC97 codec.</p> |
converts the sample rate of its incoming audio data, you guess it, to 48KHz, the sample rate of the AC97 codec.</p> |
2499 |
</p> |
</p> |
2500 |
<br /> |
<br /> |
2501 |
<br /> |
<br /> |
2502 |
<hr style="width: 100%; height: 2px;" /> |
<hr /> |
2503 |
|
|
2504 |
<table width="377" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="377" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
2505 |
<col width="66" /> |
<col width="66" /> |
2598 |
|
|
2599 |
<p><br /> |
<p><br /> |
2600 |
</p> |
</p> |
2601 |
<hr style="width: 100%; height: 2px;" /> |
<hr /> |
2602 |
|
|
2603 |
<p style="page-break-before: always;"><font size="5" |
<h2>ROUTING</h2> |
|
style="font-size: 20pt;"><i><b>ROUTING</b></i></font></p> |
|
2604 |
|
|
2605 |
<p>The routes and addresses structure:<br /> |
<p>The routes and addresses structure:<br /> |
2606 |
Source addresses in the higher bits and destination address in the lower bits. The address size is different for |
Source addresses in the higher bits and destination address in the lower bits. The address size is different for |
2728 |
ROUTE_BASE[0x35]:    0x3fff<br /> |
ROUTE_BASE[0x35]:    0x3fff<br /> |
2729 |
</font></p> |
</font></p> |
2730 |
|
|
|
<p><font size="3"><br /> |
|
|
</font></p> |
|
|
|
|
2731 |
<p><font size="3">VAL_SHIFT is 8 bits for the AU8810 |
<p><font size="3">VAL_SHIFT is 8 bits for the AU8810 |
2732 |
and AU8830 and 7 bits for the AU8820 chips.</font></p> |
and AU8830 and 7 bits for the AU8820 chips.</font></p> |
2733 |
|
|