26 |
</head> |
</head> |
27 |
|
|
28 |
<body lang="es-ES"> |
<body lang="es-ES"> |
29 |
<p style="margin-bottom: 0cm; text-align: center;"><font size="5" style="font-size: 20pt;">Aureal |
<p style="text-align: center;"><font size="5" style="font-size: 20pt;">Aureal |
30 |
Vortex Sound Board Chipset Technical description.</font></p> |
Vortex Sound Board Chipset Technical description.</font></p> |
31 |
|
|
32 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
33 |
</p> |
</p> |
34 |
|
|
35 |
<p style="margin-bottom: 0cm;"><font size="5" style="font-size: 20pt;"><span><font size="4" |
<p><font size="5" style="font-size: 20pt;"><span><font size="4" |
36 |
style="font-size: 16pt;">This VERY preliminary.  There is ABOSULUTELY NO WARRANTY about the content of this |
style="font-size: 16pt;">This VERY preliminary.  There is ABOSULUTELY NO WARRANTY about the content of this |
37 |
document. Any corrections, addition however are gladly welcome.</font></span></font></p> |
document. Any corrections, addition however are gladly welcome.</font></span></font></p> |
38 |
|
|
39 |
<p style="margin-bottom: 0cm;">Author: Manuel Jander (mjander@embedded.cl)<br /> |
<p>Author: Manuel Jander (mjander@embedded.cl)<br /> |
40 |
</p> |
</p> |
41 |
|
|
42 |
<p style="margin-bottom: 0cm;"><i><b><br /> |
<p><i><b><br /> |
43 |
Preamble</b></i></p> |
Preamble</b></i></p> |
44 |
|
|
45 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
46 |
</p> |
</p> |
47 |
|
|
48 |
<p style="margin-bottom: 0cm;">This a mix of several separate pieces of documents, most of them part |
<p>This a mix of several separate pieces of documents, most of them part |
49 |
of the Sourceforge and Savannah disassembling project efforts. The goal of this paper is to order and combine all |
of the Sourceforge and Savannah disassembling project efforts. The goal of this paper is to order and combine all |
50 |
of the available information regarding this superb and historical important audio chipset. I would like to thank |
of the available information regarding this superb and historical important audio chipset. I would like to thank |
51 |
anyone involved at the Sourceforge Aureal and the Savannah OpenVortex projects.</p> |
anyone involved at the Sourceforge Aureal and the Savannah OpenVortex projects.</p> |
52 |
|
|
53 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
54 |
</p> |
</p> |
55 |
|
|
56 |
<p style="margin-bottom: 0cm;"><b><i>General description</i></b></p> |
<p><b><i>General description</i></b></p> |
57 |
|
|
58 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
59 |
</p> |
</p> |
60 |
|
|
61 |
<p style="margin-bottom: 0cm; font-style: normal;">The vortex architecture consists of a variety of |
<p>The vortex architecture consists of a variety of |
62 |
modules that are connected by programmable routes. Various routes are made between the these modules to produce the |
modules that are connected by programmable routes. Various routes are made between the these modules to produce the |
63 |
desired results. For example, a route can be made between a DMA controller and output codec, or from a DMA |
desired results. For example, a route can be made between a DMA controller and output codec, or from a DMA |
64 |
controller to a sample rate converter and then to the output codec. They can be strung together in a variety of |
controller to a sample rate converter and then to the output codec. They can be strung together in a variety of |
65 |
ways.</p> |
ways.</p> |
66 |
|
|
67 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
68 |
</p> |
</p> |
69 |
|
|
70 |
<p style="margin-bottom: 0cm; font-style: normal;"><img src="techpaper_html_740e8dd1.gif" |
<p><img src="overview.png" |
71 |
align="left" /><br /> |
align="left" /><br /> |
72 |
</p> |
</p> |
73 |
|
|
74 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
75 |
</p> |
</p> |
76 |
|
|
77 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
78 |
</p> |
</p> |
79 |
|
|
80 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
81 |
</p> |
</p> |
82 |
|
|
83 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
84 |
</p> |
</p> |
85 |
|
|
86 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
87 |
</p> |
</p> |
88 |
|
|
89 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
90 |
</p> |
</p> |
91 |
|
|
92 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
93 |
</p> |
</p> |
94 |
|
|
95 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
96 |
</p> |
</p> |
97 |
|
|
98 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
99 |
</p> |
</p> |
100 |
|
|
101 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
102 |
</p> |
</p> |
103 |
<br /> |
<br /> |
104 |
|
|
105 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
106 |
</p> |
</p> |
107 |
|
|
108 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
109 |
</p> |
</p> |
110 |
|
|
111 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
112 |
Dotted lines are supposedly possible routeable audio data path. The existence and internals of the EQ and A3D |
Dotted lines are supposedly possible routeable audio data path. The existence and internals of the EQ and A3D |
113 |
module are very uncertain, and probably we will not be able to be used, except if some former employee of Aureal |
module are very uncertain, and probably we will not be able to be used, except if some former employee of Aureal |
114 |
Semiconductors gives us a little help.<br /> |
Semiconductors gives us a little help.<br /> |
115 |
</p> |
</p> |
116 |
|
|
117 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
118 |
</p> |
</p> |
119 |
|
|
120 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
121 |
</p> |
</p> |
122 |
|
|
123 |
<p style="margin-bottom: 0cm; font-style: normal;">There are several i/o ports mapped to a MMIO area |
<p>There are several i/o ports mapped to a MMIO area |
124 |
of different size, depending on the particular model, which are used to control and monitor the behavior of the |
of different size, depending on the particular model, which are used to control and monitor the behavior of the |
125 |
chipset.</p> |
chipset.</p> |
126 |
|
|
127 |
<p style="margin-bottom: 0cm; font-style: normal;">There are some mayor family of ports, which will be |
<p>There are some mayor family of ports, which will be |
128 |
described along this document in sequence</p> |
described along this document in sequence</p> |
129 |
<br /> |
<br /> |
130 |
|
|
131 |
<ul> |
<ul> |
132 |
<li> |
<li> |
133 |
<p style="margin-bottom: 0cm; font-style: normal;">Global configuration register</p> |
<p>Global configuration register</p> |
134 |
</li> |
</li> |
135 |
|
|
136 |
<li> |
<li> |
137 |
<p style="margin-bottom: 0cm; font-style: normal;">Interrupt Control, Status and Programmable |
<p>Interrupt Control, Status and Programmable |
138 |
Timer Interface</p> |
Timer Interface</p> |
139 |
</li> |
</li> |
140 |
|
|
141 |
<li> |
<li> |
142 |
<p style="margin-bottom: 0cm; font-style: normal;">AC97 Codec I/O</p> |
<p>AC97 Codec I/O</p> |
143 |
</li> |
</li> |
144 |
|
|
145 |
<li> |
<li> |
146 |
<p style="margin-bottom: 0cm; font-style: normal;">ADB (Audio Data Bus) and WT (WaveTable)</p> |
<p>ADB (Audio Data Bus) and WT (WaveTable)</p> |
147 |
</li> |
</li> |
148 |
|
|
149 |
<li> |
<li> |
150 |
<p style="margin-bottom: 0cm; font-style: normal;">Routing</p> |
<p>Routing</p> |
151 |
</li> |
</li> |
152 |
|
|
153 |
<li> |
<li> |
154 |
<p style="margin-bottom: 0cm; font-style: normal;">Mixer</p> |
<p>Mixer</p> |
155 |
</li> |
</li> |
156 |
|
|
157 |
<li> |
<li> |
158 |
<p style="margin-bottom: 0cm; font-style: normal;">Sample Rate Converter</p> |
<p>Sample Rate Converter</p> |
159 |
</li> |
</li> |
160 |
|
|
161 |
<li> |
<li> |
162 |
<p style="margin-bottom: 0cm; font-style: normal;">DMA controller</p> |
<p>DMA controller</p> |
163 |
</li> |
</li> |
164 |
</ul> |
</ul> |
165 |
|
|
166 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
167 |
</p> |
</p> |
168 |
|
|
169 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
170 |
</p> |
</p> |
171 |
|
|
172 |
<p style="margin-bottom: 0cm; page-break-before: always;"><font size="5" |
<p style="page-break-before: always;"><font size="5" |
173 |
style="font-size: 20pt;"><i><b>Global Configuration Register</b></i></font></p> |
style="font-size: 20pt;"><i><b>Global Configuration Register</b></i></font></p> |
174 |
|
|
175 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
176 |
</p> |
</p> |
177 |
|
|
178 |
<p style="margin-bottom: 0cm; font-style: normal;">This is a global configuration port, which contains |
<p>This is a global configuration port, which contains |
179 |
the following global configuration flags.</p> |
the following global configuration flags.</p> |
180 |
|
|
181 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
182 |
</p> |
</p> |
183 |
|
|
184 |
<table width="100%" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="100%" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
190 |
<thead> |
<thead> |
191 |
<tr valign="top"> |
<tr valign="top"> |
192 |
<th width="20%"> |
<th width="20%"> |
193 |
<p style="font-style: normal;">bits<br /> |
<p>bits<br /> |
194 |
</p> |
</p> |
195 |
</th> |
</th> |
196 |
|
|
197 |
<th width="23%"> |
<th width="23%"> |
198 |
<p style="font-style: normal;">AU8810</p> |
<p>AU8810</p> |
199 |
</th> |
</th> |
200 |
|
|
201 |
<th width="27%"> |
<th width="27%"> |
202 |
<p style="font-style: normal;">AU8820 (0x1280c)</p> |
<p>AU8820 (0x1280c)</p> |
203 |
</th> |
</th> |
204 |
|
|
205 |
<th width="30%"> |
<th width="30%"> |
206 |
<p style="font-style: normal;">AU8830</p> |
<p>AU8830</p> |
207 |
</th> |
</th> |
208 |
</tr> |
</tr> |
209 |
</thead> |
</thead> |
211 |
<tbody> |
<tbody> |
212 |
<tr valign="top"> |
<tr valign="top"> |
213 |
<td width="20%"> |
<td width="20%"> |
214 |
<p style="font-style: normal;">Enable glob. IRQ</p> |
<p>Enable glob. IRQ</p> |
215 |
</td> |
</td> |
216 |
|
|
217 |
<td width="23%"> |
<td width="23%"> |
218 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
219 |
</p> |
</p> |
220 |
</td> |
</td> |
221 |
|
|
222 |
<td width="27%"> |
<td width="27%"> |
223 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00004000</font></p> |
<p align="center"><font face="Andale Mono">0x00004000</font></p> |
224 |
</td> |
</td> |
225 |
|
|
226 |
<td width="30%"> |
<td width="30%"> |
227 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x0004000</font></p> |
<p align="center"><font face="Andale Mono">0x0004000</font></p> |
228 |
</td> |
</td> |
229 |
</tr> |
</tr> |
230 |
|
|
231 |
<tr valign="top"> |
<tr valign="top"> |
232 |
<td width="20%"> |
<td width="20%"> |
233 |
<p style="font-style: normal;">Enable MPU401</p> |
<p>Enable MPU401</p> |
234 |
</td> |
</td> |
235 |
|
|
236 |
<td width="23%"> |
<td width="23%"> |
237 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
238 |
</p> |
</p> |
239 |
</td> |
</td> |
240 |
|
|
241 |
<td width="27%"> |
<td width="27%"> |
242 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000001</font></p> |
<p align="center"><font face="Andale Mono">0x00000001</font></p> |
243 |
</td> |
</td> |
244 |
|
|
245 |
<td width="30%"> |
<td width="30%"> |
246 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
247 |
</p> |
</p> |
248 |
</td> |
</td> |
249 |
</tr> |
</tr> |
264 |
</td> |
</td> |
265 |
|
|
266 |
<td width="27%"> |
<td width="27%"> |
267 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000060<br /> |
<p align="center"><font face="Andale Mono">0x00000060<br /> |
268 |
</font> <font face="Andale Mono">0x00000060<br /> |
</font> <font face="Andale Mono">0x00000060<br /> |
269 |
</font> <font face="Andale Mono">0x00000040<br /> |
</font> <font face="Andale Mono">0x00000040<br /> |
270 |
</font> <font face="Andale Mono">0x00000020<br /> |
</font> <font face="Andale Mono">0x00000020<br /> |
273 |
</td> |
</td> |
274 |
|
|
275 |
<td width="30%"> |
<td width="30%"> |
276 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
277 |
</p> |
</p> |
278 |
</td> |
</td> |
279 |
</tr> |
</tr> |
289 |
</td> |
</td> |
290 |
|
|
291 |
<td width="27%"> |
<td width="27%"> |
292 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000008</font></p> |
<p align="center"><font face="Andale Mono">0x00000008</font></p> |
293 |
</td> |
</td> |
294 |
|
|
295 |
<td width="30%"> |
<td width="30%"> |
296 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
297 |
</p> |
</p> |
298 |
</td> |
</td> |
299 |
</tr> |
</tr> |
309 |
</td> |
</td> |
310 |
|
|
311 |
<td width="27%"> |
<td width="27%"> |
312 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000e00</font></p> |
<p align="center"><font face="Andale Mono">0x00000e00</font></p> |
313 |
</td> |
</td> |
314 |
|
|
315 |
<td width="30%"> |
<td width="30%"> |
316 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
317 |
</p> |
</p> |
318 |
</td> |
</td> |
319 |
</tr> |
</tr> |
329 |
</td> |
</td> |
330 |
|
|
331 |
<td width="27%"> |
<td width="27%"> |
332 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">(addr << 9)</font></p> |
<p align="center"><font face="Andale Mono">(addr << 9)</font></p> |
333 |
</td> |
</td> |
334 |
|
|
335 |
<td width="30%"> |
<td width="30%"> |
336 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
337 |
</p> |
</p> |
338 |
</td> |
</td> |
339 |
</tr> |
</tr> |
340 |
</tbody> |
</tbody> |
341 |
</table> |
</table> |
342 |
|
|
343 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
344 |
</p> |
</p> |
345 |
<br /> |
<br /> |
346 |
<hr style="width: 100%; height: 2px;" /> |
<hr style="width: 100%; height: 2px;" /> |
347 |
|
|
348 |
<p style="margin-bottom: 0cm;"><font size="5" style="font-size: 20pt;"><i><b>Interrupt Control and |
<p><font size="5" style="font-size: 20pt;"><i><b>Interrupt Control and |
349 |
Status Registers</b></i></font></p> |
Status Registers</b></i></font></p> |
350 |
|
|
351 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
352 |
</p> |
</p> |
353 |
|
|
354 |
<ul> |
<ul> |
355 |
<li> |
<li> |
356 |
<p style="margin-bottom: 0cm; font-style: normal;">Port Numbers: Here is a table of the names |
<p>Port Numbers: Here is a table of the names |
357 |
(suggestions?) of the interrupt related registers for each of the Aureal chipset family.</p> |
(suggestions?) of the interrupt related registers for each of the Aureal chipset family.</p> |
358 |
</li> |
</li> |
359 |
</ul> |
</ul> |
360 |
|
|
361 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
362 |
</p> |
</p> |
363 |
|
|
364 |
<table width="577" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="577" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
374 |
</th> |
</th> |
375 |
|
|
376 |
<th width="129"> |
<th width="129"> |
377 |
<p style="font-style: normal;">IRQ_SOURCE</p> |
<p>IRQ_SOURCE</p> |
378 |
</th> |
</th> |
379 |
|
|
380 |
<th width="141"> |
<th width="141"> |
381 |
<p style="font-style: normal;">IRQ_CTRL</p> |
<p>IRQ_CTRL</p> |
382 |
</th> |
</th> |
383 |
|
|
384 |
<th width="141"> |
<th width="141"> |
385 |
<p style="font-style: normal;">IRQ_STAT</p> |
<p>IRQ_STAT</p> |
386 |
</th> |
</th> |
387 |
</tr> |
</tr> |
388 |
</thead> |
</thead> |
450 |
</tbody> |
</tbody> |
451 |
</table> |
</table> |
452 |
|
|
453 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
454 |
<br /> |
<br /> |
455 |
</p> |
</p> |
456 |
|
|
457 |
<ul> |
<ul> |
458 |
<li> |
<li> |
459 |
<p style="margin-bottom: 0cm; font-style: normal;">Interrupt Control</p> |
<p>Interrupt Control</p> |
460 |
</li> |
</li> |
461 |
</ul> |
</ul> |
462 |
|
|
463 |
<p style="margin-bottom: 0cm; font-style: normal;">This port allows to enable or disable individual |
<p>This port allows to enable or disable individual |
464 |
sources of interrupts, for example the MIDI port, Timer or whatever. <font color="#000000">The flags for each |
sources of interrupts, for example the MIDI port, Timer or whatever. <font color="#000000">The flags for each |
465 |
Interrupt source are the same as the IRQ_SOURCE flags.</font></p> |
Interrupt source are the same as the IRQ_SOURCE flags.</font></p> |
466 |
<br /> |
<br /> |
595 |
</tbody> |
</tbody> |
596 |
</table> |
</table> |
597 |
|
|
598 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
599 |
<br /> |
<br /> |
600 |
</p> |
</p> |
601 |
|
|
602 |
<ul> |
<ul> |
603 |
<li> |
<li> |
604 |
<p style="margin-bottom: 0cm; font-style: normal; page-break-before: always;">Interrupt |
<p style="font-style: normal; page-break-before: always;">Interrupt |
605 |
Sources</p> |
Sources</p> |
606 |
</li> |
</li> |
607 |
</ul> |
</ul> |
742 |
</tbody> |
</tbody> |
743 |
</table> |
</table> |
744 |
|
|
745 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
746 |
</p> |
</p> |
747 |
|
|
748 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
749 |
</p> |
</p> |
750 |
|
|
751 |
<ul> |
<ul> |
752 |
<li> |
<li> |
753 |
<p style="margin-bottom: 0cm;">Interrupt Acknowledge and Timer.</p> |
<p>Interrupt Acknowledge and Timer.</p> |
754 |
</li> |
</li> |
755 |
</ul> |
</ul> |
756 |
|
|
757 |
<p style="margin-bottom: 0cm;">The chipset has a programmable Timer, which can be programmed to |
<p>The chipset has a programmable Timer, which can be programmed to |
758 |
generate periodic interrupts for example to update DMA buffers. The associated port has a different function for |
generate periodic interrupts for example to update DMA buffers. The associated port has a different function for |
759 |
reading and writing. When read it acknowledges the current interrupt (?) and when written one can set the Timer |
reading and writing. When read it acknowledges the current interrupt (?) and when written one can set the Timer |
760 |
period in 1/48000 second units. A typical value is 0x60 which equals to about 500 interrupts per second.</p> |
period in 1/48000 second units. A typical value is 0x60 which equals to about 500 interrupts per second.</p> |
761 |
|
|
762 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
763 |
</p> |
</p> |
764 |
|
|
765 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
766 |
</p> |
</p> |
767 |
|
|
768 |
<p style="margin-bottom: 0cm; font-style: normal;"><b><i><font size="5" style="font-size: 20pt;">AC97 |
<p><b><i><font size="5" style="font-size: 20pt;">AC97 |
769 |
Codec I/O</font></i></b></p> |
Codec I/O</font></i></b></p> |
770 |
|
|
771 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
772 |
</p> |
</p> |
773 |
|
|
774 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
775 |
</p> |
</p> |
776 |
|
|
777 |
<table width="705" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="705" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
789 |
</th> |
</th> |
790 |
|
|
791 |
<td width="122"> |
<td width="122"> |
792 |
<p align="center" style="font-style: normal;">CODEC_CTRL</p> |
<p align="center">CODEC_CTRL</p> |
793 |
</td> |
</td> |
794 |
|
|
795 |
<td width="99"> |
<td width="99"> |
796 |
<p align="center" style="font-style: normal;">CODEC_EN</p> |
<p align="center">CODEC_EN</p> |
797 |
</td> |
</td> |
798 |
|
|
799 |
<td width="109"> |
<td width="109"> |
800 |
<p align="center" style="font-style: normal;">CODEC_CHN</p> |
<p align="center">CODEC_CHN</p> |
801 |
</td> |
</td> |
802 |
|
|
803 |
<td width="101"> |
<td width="101"> |
804 |
<p align="center" style="font-style: normal;">CODEC_IO</p> |
<p align="center">CODEC_IO</p> |
805 |
</td> |
</td> |
806 |
|
|
807 |
<th width="92"> |
<th width="92"> |
808 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
809 |
</p> |
</p> |
810 |
</th> |
</th> |
811 |
</tr> |
</tr> |
818 |
</td> |
</td> |
819 |
|
|
820 |
<td width="122"> |
<td width="122"> |
821 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
822 |
</p> |
</p> |
823 |
</td> |
</td> |
824 |
|
|
849 |
</td> |
</td> |
850 |
|
|
851 |
<td width="122"> |
<td width="122"> |
852 |
<p align="center" style="font-style: normal;">0x11984</p> |
<p align="center">0x11984</p> |
853 |
</td> |
</td> |
854 |
|
|
855 |
<td width="99"> |
<td width="99"> |
856 |
<p align="center" style="font-style: normal;">0x11990</p> |
<p align="center">0x11990</p> |
857 |
</td> |
</td> |
858 |
|
|
859 |
<td width="109"> |
<td width="109"> |
860 |
<p align="center" style="font-style: normal;">0x11880</p> |
<p align="center">0x11880</p> |
861 |
</td> |
</td> |
862 |
|
|
863 |
<td width="101"> |
<td width="101"> |
864 |
<p align="center" style="font-style: normal;">0x11988</p> |
<p align="center">0x11988</p> |
865 |
</td> |
</td> |
866 |
|
|
867 |
<td width="92"> |
<td width="92"> |
899 |
</tbody> |
</tbody> |
900 |
</table> |
</table> |
901 |
|
|
902 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
903 |
</p> |
</p> |
904 |
|
|
905 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
906 |
</p> |
</p> |
907 |
|
|
908 |
<p style="margin-bottom: 0cm; font-style: normal;">CODEC_CTRL</p> |
<p>CODEC_CTRL</p> |
909 |
|
|
910 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
911 |
</p> |
</p> |
912 |
|
|
913 |
<p style="margin-bottom: 0cm; font-style: normal;">A static write sequence to this port initializes |
<p>A static write sequence to this port initializes |
914 |
the CODEC with a 5ms delay in between. This sequence are:</p> |
the CODEC with a 5ms delay in between. This sequence are:</p> |
915 |
|
|
916 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
917 |
</p> |
</p> |
918 |
|
|
919 |
<p style="margin-bottom: 0cm; font-style: normal;">For AU8810: FIXME</p> |
<p>For AU8810: FIXME</p> |
920 |
|
|
921 |
<p style="margin-bottom: 0cm; font-style: normal;">For AU8820: 0x00a8, 0x80a8, 0x80e8, 0x80a8, 0x00a8, |
<p>For AU8820: 0x00a8, 0x80a8, 0x80e8, 0x80a8, 0x00a8, |
922 |
0x00e8</p> |
0x00e8</p> |
923 |
|
|
924 |
<p style="margin-bottom: 0cm; font-style: normal;">For AU8830: 0x8068, 0x00e8</p> |
<p>For AU8830: 0x8068, 0x00e8</p> |
925 |
|
|
926 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
927 |
</p> |
</p> |
928 |
|
|
929 |
<p style="margin-bottom: 0cm; font-style: normal;">[8] -> (read) Codec ready.</p> |
<p>[8] -> (read) Codec ready.</p> |
930 |
|
|
931 |
<p style="margin-bottom: 0cm; font-style: normal;">?[9..21] -> slot valid tag bits.<br /> |
<p>?[9..21] -> slot valid tag bits.<br /> |
932 |
</p> |
</p> |
933 |
|
|
934 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
935 |
<br /> |
<br /> |
936 |
</p> |
</p> |
937 |
|
|
938 |
<p style="margin-bottom: 0cm; font-style: normal;">CODEC_IO<br /> |
<p>CODEC_IO<br /> |
939 |
<br /> |
<br /> |
940 |
This port is used to communicate directly to the codec, using the output and input stream slot 1 and 2 of the AC97 |
This port is used to communicate directly to the codec, using the output and input stream slot 1 and 2 of the AC97 |
941 |
codec.</p> |
codec.</p> |
942 |
|
|
943 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
944 |
Write Flag: 0x800000 = 1 << (19 + 4)</p> |
Write Flag: 0x800000 = 1 << (19 + 4)</p> |
945 |
|
|
946 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
947 |
Both data and address are read and writable. After a write, the address can be read back to ensure that the data |
Both data and address are read and writable. After a write, the address can be read back to ensure that the data |
948 |
corresponds to the command issued before, since this is a synchronous interface.</p> |
corresponds to the command issued before, since this is a synchronous interface.</p> |
949 |
|
|
950 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
951 |
</p> |
</p> |
952 |
|
|
953 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;">[21..22,24..31] -> |
<p align="left">[21..22,24..31] -> |
954 |
unused/unknown.</p> |
unused/unknown.</p> |
955 |
|
|
956 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;">[23] -> write only: 0 = READ CMD, 1 |
<p align="left">[23] -> write only: 0 = READ CMD, 1 |
957 |
= WRITE CMD.</p> |
= WRITE CMD.</p> |
958 |
|
|
959 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;">[16..20] -> slot1 [12..18] addr</p> |
<p align="left">[16..20] -> slot1 [12..18] addr</p> |
960 |
|
|
961 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;">[0..15] -> slot 2 [4..19] data</p> |
<p align="left">[0..15] -> slot 2 [4..19] data</p> |
962 |
|
|
963 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p align="left"><br /> |
964 |
</p> |
</p> |
965 |
|
|
966 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p align="left"><br /> |
967 |
</p> |
</p> |
968 |
|
|
969 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;">CODEC_EN</p> |
<p align="left">CODEC_EN</p> |
970 |
|
|
971 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p align="left"><br /> |
972 |
</p> |
</p> |
973 |
|
|
974 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font size="3">This register purpose |
<p align="left"><font size="3">This register purpose |
975 |
is to enable/disable the different channels of the codec. Each channel has a flag associated to it. There are only |
is to enable/disable the different channels of the codec. Each channel has a flag associated to it. There are only |
976 |
two interesting flags, for channel 0 and 1.</font></p> |
two interesting flags, for channel 0 and 1.</font></p> |
977 |
|
|
978 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p align="left"><br /> |
979 |
</p> |
</p> |
980 |
|
|
981 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font size="3">Channel0: |
<p align="left"><font size="3">Channel0: |
982 |
0x00000100</font></p> |
0x00000100</font></p> |
983 |
|
|
984 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font size="3">Channel0: |
<p align="left"><font size="3">Channel0: |
985 |
0x00000200</font></p> |
0x00000200</font></p> |
986 |
|
|
987 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p align="left"><br /> |
988 |
</p> |
</p> |
989 |
|
|
990 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font size="3">CODEC_CHN</font></p> |
<p align="left"><font size="3">CODEC_CHN</font></p> |
991 |
|
|
992 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p align="left"><br /> |
993 |
</p> |
</p> |
994 |
|
|
995 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font size="3">The only known thing |
<p align="left"><font size="3">The only known thing |
996 |
about this register is that its the base of a series of register which are initialized once and never touched |
about this register is that its the base of a series of register which are initialized once and never touched |
997 |
again.</font></p> |
again.</font></p> |
998 |
|
|
999 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p align="left"><br /> |
1000 |
</p> |
</p> |
1001 |
|
|
1002 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font size="3">AU8810:</font></p> |
<p align="left"><font size="3">AU8810:</font></p> |
1003 |
|
|
1004 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font size="3">FIXME!</font></p> |
<p align="left"><font size="3">FIXME!</font></p> |
1005 |
|
|
1006 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p align="left"><br /> |
1007 |
</p> |
</p> |
1008 |
|
|
1009 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font size="3">AU8830 and AU8820: 32 |
<p align="left"><font size="3">AU8830 and AU8820: 32 |
1010 |
writes, following this pattern:</font></p> |
writes, following this pattern:</font></p> |
1011 |
|
|
1012 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p align="left"><br /> |
1013 |
</p> |
</p> |
1014 |
|
|
1015 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font face="Andale Mono"><font |
<p align="left"><font face="Andale Mono"><font |
1016 |
size="3">CODEC_CHN + 0x0 = 0x00000000</font></font></p> |
size="3">CODEC_CHN + 0x0 = 0x00000000</font></font></p> |
1017 |
|
|
1018 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font face="Andale Mono"><font |
<p align="left"><font face="Andale Mono"><font |
1019 |
size="3">CODEC_CHN + 0x4 = 0xffffffff</font></font></p> |
size="3">CODEC_CHN + 0x4 = 0xffffffff</font></font></p> |
1020 |
|
|
1021 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font face="Andale Mono"><font |
<p align="left"><font face="Andale Mono"><font |
1022 |
size="3">CODEC_CHN + 0x8 = 0xfffffffe</font></font></p> |
size="3">CODEC_CHN + 0x8 = 0xfffffffe</font></font></p> |
1023 |
|
|
1024 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;"><font face="Andale Mono"><font |
<p align="left"><font face="Andale Mono"><font |
1025 |
size="3">CODEC_CHN + 0xc = 0xfffffffd</font></font></p> |
size="3">CODEC_CHN + 0xc = 0xfffffffd</font></font></p> |
1026 |
|
|
1027 |
<p align="left" style="margin-bottom: 0cm;"><font face="Andale Mono"><font |
<p align="left"><font face="Andale Mono"><font |
1028 |
size="3"><i><b>...</b></i></font></font></p> |
size="3"><i><b>...</b></i></font></font></p> |
1029 |
|
|
1030 |
<p style="margin-bottom: 0cm;"><b>The complete initialization sequence is</b>:</p> |
<p><b>The complete initialization sequence is</b>:</p> |
1031 |
|
|
1032 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1033 |
</p> |
</p> |
1034 |
|
|
1035 |
<ul> |
<ul> |
1036 |
<li> |
<li> |
1037 |
<p style="margin-bottom: 0cm;">Initialize CODEC_CTRL register</p> |
<p>Initialize CODEC_CTRL register</p> |
1038 |
</li> |
</li> |
1039 |
|
|
1040 |
<li> |
<li> |
1041 |
<p style="margin-bottom: 0cm;">Initialize CODEC_CHN registers.</p> |
<p>Initialize CODEC_CHN registers.</p> |
1042 |
</li> |
</li> |
1043 |
|
|
1044 |
<li> |
<li> |
1045 |
<p style="margin-bottom: 0cm;">Initialize CODEC_EN register.</p> |
<p>Initialize CODEC_EN register.</p> |
1046 |
</li> |
</li> |
1047 |
|
|
1048 |
<li> |
<li> |
1049 |
<p style="margin-bottom: 0cm;">Write again last written value to CODEC_CTRL (0x00e8 for AU8820 and |
<p>Write again last written value to CODEC_CTRL (0x00e8 for AU8820 and |
1050 |
AU8830).</p> |
AU8830).</p> |
1051 |
</li> |
</li> |
1052 |
</ul> |
</ul> |
1053 |
<br /> |
<br /> |
1054 |
<hr style="width: 100%; height: 2px;" /> |
<hr style="width: 100%; height: 2px;" /> |
1055 |
|
|
1056 |
<p style="margin-bottom: 0cm; page-break-before: always;"><b><i><font size="5" |
<p style="page-break-before: always;"><b><i><font size="5" |
1057 |
style="font-size: 20pt;">ADB and WT<br /> |
style="font-size: 20pt;">ADB and WT<br /> |
1058 |
</font></i></b></p> |
</font></i></b></p> |
1059 |
|
|
1060 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1061 |
There are two audio engines. The ADB engine which provides 16 channels, and the WT engine with 32 channels (48 |
There are two audio engines. The ADB engine which provides 16 channels, and the WT engine with 32 channels (48 |
1062 |
total). Each engine uses one single DMA buffer through which the different channels are multiplexed (interlaced). |
total). Each engine uses one single DMA buffer through which the different channels are multiplexed (interlaced). |
1063 |
Each DMA buffer has 4 subbuffers of a size of upto 4kB, which can be chained in sequence or used |
Each DMA buffer has 4 subbuffers of a size of upto 4kB, which can be chained in sequence or used |
1070 |
special attributes, because some very specific channels are used to connect one given block with another.<br /> |
special attributes, because some very specific channels are used to connect one given block with another.<br /> |
1071 |
</p> |
</p> |
1072 |
|
|
1073 |
<p style="margin-bottom: 0cm;">The most important blocks of the engines are the DMA engine, |
<p>The most important blocks of the engines are the DMA engine, |
1074 |
SampleRateConverter, the mixer and the Codec interface. For Playback for example the DMA engine is connected to a |
SampleRateConverter, the mixer and the Codec interface. For Playback for example the DMA engine is connected to a |
1075 |
SRC, the SRC output to the mixer and the mixer output to the codec.<br /> |
SRC, the SRC output to the mixer and the mixer output to the codec.<br /> |
1076 |
</p> |
</p> |
1080 |
<hr style="width: 100%; height: 2px;" /> |
<hr style="width: 100%; height: 2px;" /> |
1081 |
<font size="5" style="font-size: 20pt;"><i><b>ADB DMA Engine</b></i></font> |
<font size="5" style="font-size: 20pt;"><i><b>ADB DMA Engine</b></i></font> |
1082 |
|
|
1083 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1084 |
</p> |
</p> |
1085 |
|
|
1086 |
<p style="margin-bottom: 0cm;">This is the DMA engine that feeds the ADB engine (something). The |
<p>This is the DMA engine that feeds the ADB engine (something). The |
1087 |
ADB_CTRL and ADB_STATUS access the same internal register, but one is read only and the other is write only, |
ADB_CTRL and ADB_STATUS access the same internal register, but one is read only and the other is write only, |
1088 |
providing complete write read access with the corresponding MMIO ports.<br /> |
providing complete write read access with the corresponding MMIO ports.<br /> |
1089 |
</p> |
</p> |
1090 |
|
|
1091 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1092 |
</p> |
</p> |
1093 |
|
|
1094 |
<p style="margin-bottom: 0cm;">Routing Addresses:<br /> |
<p>Routing Addresses:<br /> |
1095 |
<br /> |
<br /> |
1096 |
</p> |
</p> |
1097 |
|
|
1114 |
</td> |
</td> |
1115 |
|
|
1116 |
<td> |
<td> |
1117 |
<p style="font-style: normal;">0 .. ?<br /> |
<p>0 .. ?<br /> |
1118 |
</p> |
</p> |
1119 |
</td> |
</td> |
1120 |
</tr> |
</tr> |
1125 |
</td> |
</td> |
1126 |
|
|
1127 |
<td width="101"> |
<td width="101"> |
1128 |
<p style="font-style: normal;">0 .. 0x0f</p> |
<p>0 .. 0x0f</p> |
1129 |
</td> |
</td> |
1130 |
</tr> |
</tr> |
1131 |
|
|
1143 |
</tbody> |
</tbody> |
1144 |
</table> |
</table> |
1145 |
|
|
1146 |
<p align="left" style="margin-bottom: 0cm;"><br /> |
<p align="left"><br /> |
1147 |
</p> |
</p> |
1148 |
|
|
1149 |
<p align="center" style="margin-bottom: 0cm;"><br /> |
<p align="center"><br /> |
1150 |
</p> |
</p> |
1151 |
|
|
1152 |
<table width="697" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="697" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
1164 |
</th> |
</th> |
1165 |
|
|
1166 |
<td width="101"> |
<td width="101"> |
1167 |
<p align="center" style="font-style: normal;">SR_EN</p> |
<p align="center">SR_EN</p> |
1168 |
</td> |
</td> |
1169 |
|
|
1170 |
<td width="140"> |
<td width="140"> |
1171 |
<p align="center" style="font-style: normal;">DMA_CTRL</p> |
<p align="center">DMA_CTRL</p> |
1172 |
</td> |
</td> |
1173 |
|
|
1174 |
<td width="141"> |
<td width="141"> |
1175 |
<p align="center" style="font-style: normal;">DMA_STAT</p> |
<p align="center">DMA_STAT</p> |
1176 |
</td> |
</td> |
1177 |
|
|
1178 |
<td width="95"> |
<td width="95"> |
1179 |
<p align="center" style="font-style: normal;">ADB_S0</p> |
<p align="center">ADB_S0</p> |
1180 |
</td> |
</td> |
1181 |
|
|
1182 |
<td width="92"> |
<td width="92"> |
1183 |
<p align="center" style="font-style: normal;">ADB_S1</p> |
<p align="center">ADB_S1</p> |
1184 |
</td> |
</td> |
1185 |
</tr> |
</tr> |
1186 |
</thead> |
</thead> |
1192 |
</td> |
</td> |
1193 |
|
|
1194 |
<td width="101"> |
<td width="101"> |
1195 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1196 |
</p> |
</p> |
1197 |
</td> |
</td> |
1198 |
|
|
1223 |
</td> |
</td> |
1224 |
|
|
1225 |
<td width="101"> |
<td width="101"> |
1226 |
<p align="center" style="font-style: normal;">0x10a00</p> |
<p align="center">0x10a00</p> |
1227 |
</td> |
</td> |
1228 |
|
|
1229 |
<td width="140"> |
<td width="140"> |
1230 |
<p align="center" style="font-style: normal;">0x10580</p> |
<p align="center">0x10580</p> |
1231 |
</td> |
</td> |
1232 |
|
|
1233 |
<td width="141"> |
<td width="141"> |
1234 |
<p align="center" style="font-style: normal;">0x105c0</p> |
<p align="center">0x105c0</p> |
1235 |
</td> |
</td> |
1236 |
|
|
1237 |
<td width="95"> |
<td width="95"> |
1238 |
<p align="center" style="font-style: normal;">0x10608</p> |
<p align="center">0x10608</p> |
1239 |
</td> |
</td> |
1240 |
|
|
1241 |
<td width="92"> |
<td width="92"> |
1242 |
<p align="center" style="font-style: normal;">0x1060c</p> |
<p align="center">0x1060c</p> |
1243 |
</td> |
</td> |
1244 |
</tr> |
</tr> |
1245 |
|
|
1273 |
</tbody> |
</tbody> |
1274 |
</table> |
</table> |
1275 |
|
|
1276 |
<p align="left" style="margin-bottom: 0cm;"><br /> |
<p align="left"><br /> |
1277 |
</p> |
</p> |
1278 |
|
|
1279 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1280 |
</p> |
</p> |
1281 |
|
|
1282 |
<table width="666" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="666" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
1288 |
<thead> |
<thead> |
1289 |
<tr valign="top"> |
<tr valign="top"> |
1290 |
<td width="149"> |
<td width="149"> |
1291 |
<p align="center" style="font-style: normal;">DMA_CTRL</p> |
<p align="center">DMA_CTRL</p> |
1292 |
</td> |
</td> |
1293 |
|
|
1294 |
<th width="154"> |
<th width="154"> |
1295 |
<p style="font-style: normal;">AU8810</p> |
<p>AU8810</p> |
1296 |
</th> |
</th> |
1297 |
|
|
1298 |
<th width="161"> |
<th width="161"> |
1299 |
<p style="font-style: normal;">AU8820</p> |
<p>AU8820</p> |
1300 |
</th> |
</th> |
1301 |
|
|
1302 |
<th width="167"> |
<th width="167"> |
1303 |
<p style="font-style: normal;">AU8830</p> |
<p>AU8830</p> |
1304 |
</th> |
</th> |
1305 |
</tr> |
</tr> |
1306 |
</thead> |
</thead> |
1308 |
<tbody> |
<tbody> |
1309 |
<tr valign="top"> |
<tr valign="top"> |
1310 |
<td width="149"> |
<td width="149"> |
1311 |
<p style="font-style: normal;">DMA position</p> |
<p>DMA position</p> |
1312 |
</td> |
</td> |
1313 |
|
|
1314 |
<td width="154"> |
<td width="154"> |
1315 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1316 |
</p> |
</p> |
1317 |
</td> |
</td> |
1318 |
|
|
1319 |
<td width="161"> |
<td width="161"> |
1320 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000fff</font></p> |
<p align="center"><font face="Andale Mono">0x00000fff</font></p> |
1321 |
</td> |
</td> |
1322 |
|
|
1323 |
<td width="167"> |
<td width="167"> |
1324 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1325 |
</p> |
</p> |
1326 |
</td> |
</td> |
1327 |
</tr> |
</tr> |
1337 |
</td> |
</td> |
1338 |
|
|
1339 |
<td width="161"> |
<td width="161"> |
1340 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00003000</font></p> |
<p align="center"><font face="Andale Mono">0x00003000</font></p> |
1341 |
</td> |
</td> |
1342 |
|
|
1343 |
<td width="167"> |
<td width="167"> |
1344 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1345 |
</p> |
</p> |
1346 |
</td> |
</td> |
1347 |
</tr> |
</tr> |
1348 |
</tbody> |
</tbody> |
1349 |
</table> |
</table> |
1350 |
|
|
1351 |
<p style="margin-bottom: 0cm;">DMA_CTRL is write only.<br /> |
<p>DMA_CTRL is write only.<br /> |
1352 |
<br /> |
<br /> |
1353 |
</p> |
</p> |
1354 |
|
|
1361 |
<thead> |
<thead> |
1362 |
<tr valign="top"> |
<tr valign="top"> |
1363 |
<td width="149"> |
<td width="149"> |
1364 |
<p align="center" style="font-style: normal;">DMA_STAT(r)</p> |
<p align="center">DMA_STAT(r)</p> |
1365 |
</td> |
</td> |
1366 |
|
|
1367 |
<th width="155"> |
<th width="155"> |
1368 |
<p style="font-style: normal;">AU8810</p> |
<p>AU8810</p> |
1369 |
</th> |
</th> |
1370 |
|
|
1371 |
<th width="161"> |
<th width="161"> |
1372 |
<p style="font-style: normal;">AU8820</p> |
<p>AU8820</p> |
1373 |
</th> |
</th> |
1374 |
|
|
1375 |
<th width="167"> |
<th width="167"> |
1376 |
<p style="font-style: normal;">AU8830</p> |
<p>AU8830</p> |
1377 |
</th> |
</th> |
1378 |
</tr> |
</tr> |
1379 |
</thead> |
</thead> |
1381 |
<tbody> |
<tbody> |
1382 |
<tr valign="top"> |
<tr valign="top"> |
1383 |
<td width="149"> |
<td width="149"> |
1384 |
<p align="left" style="font-style: normal;">DMA position</p> |
<p align="left">DMA position</p> |
1385 |
</td> |
</td> |
1386 |
|
|
1387 |
<th width="155"> |
<th width="155"> |
1388 |
<p style="font-style: normal;"><br /> |
<p><br /> |
1389 |
</p> |
</p> |
1390 |
</th> |
</th> |
1391 |
|
|
1392 |
<th width="161"> |
<th width="161"> |
1393 |
<p style="font-style: normal;"><font face="Andale Mono">0x00000fff</font></p> |
<p><font face="Andale Mono">0x00000fff</font></p> |
1394 |
</th> |
</th> |
1395 |
|
|
1396 |
<th width="167"> |
<th width="167"> |
1397 |
<p style="font-style: normal;"><br /> |
<p><br /> |
1398 |
</p> |
</p> |
1399 |
</th> |
</th> |
1400 |
</tr> |
</tr> |
1410 |
</td> |
</td> |
1411 |
|
|
1412 |
<td width="161"> |
<td width="161"> |
1413 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00003000</font></p> |
<p align="center"><font face="Andale Mono">0x00003000</font></p> |
1414 |
</td> |
</td> |
1415 |
|
|
1416 |
<th width="167"> |
<th width="167"> |
1417 |
<p style="font-style: normal;"><br /> |
<p><br /> |
1418 |
</p> |
</p> |
1419 |
</th> |
</th> |
1420 |
</tr> |
</tr> |
1421 |
</tbody> |
</tbody> |
1422 |
</table> |
</table> |
1423 |
|
|
1424 |
<p style="margin-bottom: 0cm;">DMA_STAT is read only.</p> |
<p>DMA_STAT is read only.</p> |
1425 |
|
|
1426 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1427 |
</p> |
</p> |
1428 |
<hr style="width: 100%; height: 2px;" /> |
<hr style="width: 100%; height: 2px;" /> |
1429 |
|
|
1430 |
<p style="margin-bottom: 0cm;"><font size="5" style="font-size: 20pt;"><i><b>WT DMA |
<p><font size="5" style="font-size: 20pt;"><i><b>WT DMA |
1431 |
Engine</b></i></font></p> |
Engine</b></i></font></p> |
1432 |
|
|
1433 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1434 |
</p> |
</p> |
1435 |
|
|
1436 |
<p style="margin-bottom: 0cm;">The WT DMA Engine is another audio data path presumably used for the |
<p>The WT DMA Engine is another audio data path presumably used for the |
1437 |
WaveTable engine. The WT_CTRL and WT_STATUS, same as the similar ADB registers, access the same internal register, |
WaveTable engine. The WT_CTRL and WT_STATUS, same as the similar ADB registers, access the same internal register, |
1438 |
but one is read only and the other is write only, providing complete read write access with the corresponding MMIO |
but one is read only and the other is write only, providing complete read write access with the corresponding MMIO |
1439 |
ports. In the particular case of the AU8820, these MMIO addresses are the same.</p> |
ports. In the particular case of the AU8820, these MMIO addresses are the same.</p> |
1440 |
|
|
1441 |
<p align="center" style="margin-bottom: 0cm;"><br /> |
<p align="center"><br /> |
1442 |
</p> |
</p> |
1443 |
|
|
1444 |
<table width="690" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="690" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
1456 |
</th> |
</th> |
1457 |
|
|
1458 |
<td width="98"> |
<td width="98"> |
1459 |
<p align="center" style="font-style: normal;">SR_EN</p> |
<p align="center">SR_EN</p> |
1460 |
</td> |
</td> |
1461 |
|
|
1462 |
<td width="107"> |
<td width="107"> |
1463 |
<p align="center" style="font-style: normal;">WT_STATUS</p> |
<p align="center">WT_STATUS</p> |
1464 |
</td> |
</td> |
1465 |
|
|
1466 |
<td width="97"> |
<td width="97"> |
1467 |
<p align="center" style="font-style: normal;">WT_CTRL</p> |
<p align="center">WT_CTRL</p> |
1468 |
</td> |
</td> |
1469 |
|
|
1470 |
<td width="123"> |
<td width="123"> |
1471 |
<p align="center" style="font-style: normal;">WT_S0</p> |
<p align="center">WT_S0</p> |
1472 |
</td> |
</td> |
1473 |
|
|
1474 |
<td width="141"> |
<td width="141"> |
1475 |
<p align="center" style="font-style: normal;">WT_S1</p> |
<p align="center">WT_S1</p> |
1476 |
</td> |
</td> |
1477 |
</tr> |
</tr> |
1478 |
</thead> |
</thead> |
1484 |
</td> |
</td> |
1485 |
|
|
1486 |
<td width="98"> |
<td width="98"> |
1487 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1488 |
</p> |
</p> |
1489 |
</td> |
</td> |
1490 |
|
|
1518 |
</td> |
</td> |
1519 |
|
|
1520 |
<td width="107"> |
<td width="107"> |
1521 |
<p align="center" style="font-style: normal;">0x10500</p> |
<p align="center">0x10500</p> |
1522 |
</td> |
</td> |
1523 |
|
|
1524 |
<td width="97"> |
<td width="97"> |
1525 |
<p align="center" style="font-style: normal;">0x10500</p> |
<p align="center">0x10500</p> |
1526 |
</td> |
</td> |
1527 |
|
|
1528 |
<td width="123"> |
<td width="123"> |
1529 |
<p align="center" style="font-style: normal;">0x10600</p> |
<p align="center">0x10600</p> |
1530 |
</td> |
</td> |
1531 |
|
|
1532 |
<td width="141"> |
<td width="141"> |
1533 |
<p align="center" style="font-style: normal;">0x10604</p> |
<p align="center">0x10604</p> |
1534 |
</td> |
</td> |
1535 |
</tr> |
</tr> |
1536 |
|
|
1565 |
</tbody> |
</tbody> |
1566 |
</table> |
</table> |
1567 |
|
|
1568 |
<p align="left" style="margin-bottom: 0cm;"><br /> |
<p align="left"><br /> |
1569 |
</p> |
</p> |
1570 |
|
|
1571 |
<p align="left" style="margin-bottom: 0cm;"><br /> |
<p align="left"><br /> |
1572 |
</p> |
</p> |
1573 |
|
|
1574 |
<table width="666" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="666" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
1580 |
<thead> |
<thead> |
1581 |
<tr valign="top"> |
<tr valign="top"> |
1582 |
<td width="149"> |
<td width="149"> |
1583 |
<p align="center" style="font-style: normal;">DMA_STAT</p> |
<p align="center">DMA_STAT</p> |
1584 |
</td> |
</td> |
1585 |
|
|
1586 |
<th width="154"> |
<th width="154"> |
1587 |
<p style="font-style: normal;">AU8810</p> |
<p>AU8810</p> |
1588 |
</th> |
</th> |
1589 |
|
|
1590 |
<th width="161"> |
<th width="161"> |
1591 |
<p style="font-style: normal;">AU8820</p> |
<p>AU8820</p> |
1592 |
</th> |
</th> |
1593 |
|
|
1594 |
<th width="167"> |
<th width="167"> |
1595 |
<p style="font-style: normal;">AU8830</p> |
<p>AU8830</p> |
1596 |
</th> |
</th> |
1597 |
</tr> |
</tr> |
1598 |
</thead> |
</thead> |
1600 |
<tbody> |
<tbody> |
1601 |
<tr valign="top"> |
<tr valign="top"> |
1602 |
<td width="149"> |
<td width="149"> |
1603 |
<p style="font-style: normal;">DMA position</p> |
<p>DMA position</p> |
1604 |
</td> |
</td> |
1605 |
|
|
1606 |
<td width="154"> |
<td width="154"> |
1607 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1608 |
</p> |
</p> |
1609 |
</td> |
</td> |
1610 |
|
|
1611 |
<td width="161"> |
<td width="161"> |
1612 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000fff</font></p> |
<p align="center"><font face="Andale Mono">0x00000fff</font></p> |
1613 |
</td> |
</td> |
1614 |
|
|
1615 |
<td width="167"> |
<td width="167"> |
1616 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1617 |
</p> |
</p> |
1618 |
</td> |
</td> |
1619 |
</tr> |
</tr> |
1629 |
</td> |
</td> |
1630 |
|
|
1631 |
<td width="161"> |
<td width="161"> |
1632 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00600000</font></p> |
<p align="center"><font face="Andale Mono">0x00600000</font></p> |
1633 |
</td> |
</td> |
1634 |
|
|
1635 |
<td width="167"> |
<td width="167"> |
1636 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00003000</font></p> |
<p align="center"><font face="Andale Mono">0x00003000</font></p> |
1637 |
</td> |
</td> |
1638 |
</tr> |
</tr> |
1639 |
|
|
1648 |
</td> |
</td> |
1649 |
|
|
1650 |
<td width="161"> |
<td width="161"> |
1651 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x0003c000</font></p> |
<p align="center"><font face="Andale Mono">0x0003c000</font></p> |
1652 |
</td> |
</td> |
1653 |
|
|
1654 |
<td width="167"> |
<td width="167"> |
1655 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">-</font></p> |
<p align="center"><font face="Andale Mono">-</font></p> |
1656 |
</td> |
</td> |
1657 |
</tr> |
</tr> |
1658 |
|
|
1667 |
</td> |
</td> |
1668 |
|
|
1669 |
<td width="161"> |
<td width="161"> |
1670 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1671 |
</p> |
</p> |
1672 |
</td> |
</td> |
1673 |
|
|
1674 |
<td width="167"> |
<td width="167"> |
1675 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00200000</font></p> |
<p align="center"><font face="Andale Mono">0x00200000</font></p> |
1676 |
</td> |
</td> |
1677 |
</tr> |
</tr> |
1678 |
|
|
1688 |
</td> |
</td> |
1689 |
|
|
1690 |
<td width="161"> |
<td width="161"> |
1691 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1692 |
</p> |
</p> |
1693 |
</td> |
</td> |
1694 |
|
|
1695 |
<td width="167"> |
<td width="167"> |
1696 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1697 |
</p> |
</p> |
1698 |
</td> |
</td> |
1699 |
</tr> |
</tr> |
1700 |
</tbody> |
</tbody> |
1701 |
</table> |
</table> |
1702 |
|
|
1703 |
<p style="margin-bottom: 0cm;">DMA_STAT is read only.</p> |
<p>DMA_STAT is read only.</p> |
1704 |
|
|
1705 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1706 |
</p> |
</p> |
1707 |
|
|
1708 |
<table width="666" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="666" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
1714 |
<thead> |
<thead> |
1715 |
<tr valign="top"> |
<tr valign="top"> |
1716 |
<td width="149"> |
<td width="149"> |
1717 |
<p align="center" style="font-style: normal;">DMA_CTRL</p> |
<p align="center">DMA_CTRL</p> |
1718 |
</td> |
</td> |
1719 |
|
|
1720 |
<th width="155"> |
<th width="155"> |
1721 |
<p style="font-style: normal;">AU8810</p> |
<p>AU8810</p> |
1722 |
</th> |
</th> |
1723 |
|
|
1724 |
<th width="161"> |
<th width="161"> |
1725 |
<p style="font-style: normal;">AU8820</p> |
<p>AU8820</p> |
1726 |
</th> |
</th> |
1727 |
|
|
1728 |
<th width="167"> |
<th width="167"> |
1729 |
<p style="font-style: normal;">AU8830</p> |
<p>AU8830</p> |
1730 |
</th> |
</th> |
1731 |
</tr> |
</tr> |
1732 |
</thead> |
</thead> |
1743 |
</td> |
</td> |
1744 |
|
|
1745 |
<td width="161"> |
<td width="161"> |
1746 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x0000f000</font></p> |
<p align="center"><font face="Andale Mono">0x0000f000</font></p> |
1747 |
</td> |
</td> |
1748 |
|
|
1749 |
<td width="167"> |
<td width="167"> |
1750 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1751 |
</p> |
</p> |
1752 |
</td> |
</td> |
1753 |
</tr> |
</tr> |
1763 |
</td> |
</td> |
1764 |
|
|
1765 |
<td width="161"> |
<td width="161"> |
1766 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00001000</font></p> |
<p align="center"><font face="Andale Mono">0x00001000</font></p> |
1767 |
</td> |
</td> |
1768 |
|
|
1769 |
<td width="167"> |
<td width="167"> |
1770 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1771 |
</p> |
</p> |
1772 |
</td> |
</td> |
1773 |
</tr> |
</tr> |
1783 |
</td> |
</td> |
1784 |
|
|
1785 |
<td width="161"> |
<td width="161"> |
1786 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00002000</font></p> |
<p align="center"><font face="Andale Mono">0x00002000</font></p> |
1787 |
</td> |
</td> |
1788 |
|
|
1789 |
<td width="167"> |
<td width="167"> |
1790 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1791 |
</p> |
</p> |
1792 |
</td> |
</td> |
1793 |
</tr> |
</tr> |
1803 |
</td> |
</td> |
1804 |
|
|
1805 |
<td width="161"> |
<td width="161"> |
1806 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x0003c000</font></p> |
<p align="center"><font face="Andale Mono">0x0003c000</font></p> |
1807 |
</td> |
</td> |
1808 |
|
|
1809 |
<td width="167"> |
<td width="167"> |
1810 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1811 |
</p> |
</p> |
1812 |
</td> |
</td> |
1813 |
</tr> |
</tr> |
1823 |
</td> |
</td> |
1824 |
|
|
1825 |
<td width="161"> |
<td width="161"> |
1826 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00020000</font></p> |
<p align="center"><font face="Andale Mono">0x00020000</font></p> |
1827 |
</td> |
</td> |
1828 |
|
|
1829 |
<td width="167"> |
<td width="167"> |
1830 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00200000</font></p> |
<p align="center"><font face="Andale Mono">0x00200000</font></p> |
1831 |
</td> |
</td> |
1832 |
</tr> |
</tr> |
1833 |
|
|
1843 |
</td> |
</td> |
1844 |
|
|
1845 |
<td width="161"> |
<td width="161"> |
1846 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1847 |
</p> |
</p> |
1848 |
</td> |
</td> |
1849 |
|
|
1850 |
<td width="167"> |
<td width="167"> |
1851 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1852 |
</p> |
</p> |
1853 |
</td> |
</td> |
1854 |
</tr> |
</tr> |
1865 |
</td> |
</td> |
1866 |
|
|
1867 |
<td width="161"> |
<td width="161"> |
1868 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1869 |
</p> |
</p> |
1870 |
</td> |
</td> |
1871 |
|
|
1872 |
<td width="167"> |
<td width="167"> |
1873 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
1874 |
</p> |
</p> |
1875 |
</td> |
</td> |
1876 |
</tr> |
</tr> |
1877 |
</tbody> |
</tbody> |
1878 |
</table> |
</table> |
1879 |
|
|
1880 |
<p style="margin-bottom: 0cm;">DMA_CTRL is write only.</p> |
<p>DMA_CTRL is write only.</p> |
1881 |
|
|
1882 |
<p style="margin-bottom: 0cm; page-break-before: always;"><br /> |
<p style="page-break-before: always;"><br /> |
1883 |
</p> |
</p> |
1884 |
<hr style="width: 100%; height: 2px;" /> |
<hr style="width: 100%; height: 2px;" /> |
1885 |
|
|
1886 |
<p style="margin-bottom: 0cm;"><b><i><font size="5" style="font-size: 20pt;">FIFO</font></i></b></p> |
<p><b><i><font size="5" style="font-size: 20pt;">FIFO</font></i></b></p> |
1887 |
|
|
1888 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1889 |
</p> |
</p> |
1890 |
|
|
1891 |
<p style="margin-bottom: 0cm;">Each DMA channel has a fifo. There are CTRL/STATUS register which allow |
<p>Each DMA channel has a fifo. There are CTRL/STATUS register which allow |
1892 |
to set/get the state of each fifo data dword. The FIFO_DATA registers is the actual fifo data mapped to |
to set/get the state of each fifo data dword. The FIFO_DATA registers is the actual fifo data mapped to |
1893 |
registers.</p> |
registers.</p> |
1894 |
|
|
1895 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
1896 |
</p> |
</p> |
1897 |
|
|
1898 |
<table width="697" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="697" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
1905 |
<thead> |
<thead> |
1906 |
<tr valign="top"> |
<tr valign="top"> |
1907 |
<td width="66"> |
<td width="66"> |
1908 |
<p align="center" style="font-style: normal;">Chipset</p> |
<p align="center">Chipset</p> |
1909 |
</td> |
</td> |
1910 |
|
|
1911 |
<td width="142"> |
<td width="142"> |
1912 |
<p align="center" style="font-style: normal;">ADB_FIFO_CTRL</p> |
<p align="center">ADB_FIFO_CTRL</p> |
1913 |
</td> |
</td> |
1914 |
|
|
1915 |
<td width="148"> |
<td width="148"> |
1916 |
<p align="center" style="font-style: normal;">ADB_FIFO_DATA</p> |
<p align="center">ADB_FIFO_DATA</p> |
1917 |
</td> |
</td> |
1918 |
|
|
1919 |
<td width="140"> |
<td width="140"> |
1920 |
<p align="center" style="font-style: normal;">WT_FIFO_CTRL</p> |
<p align="center">WT_FIFO_CTRL</p> |
1921 |
</td> |
</td> |
1922 |
|
|
1923 |
<td width="160"> |
<td width="160"> |
1924 |
<p align="center" style="font-style: normal;">WT_FIFO_DATA</p> |
<p align="center">WT_FIFO_DATA</p> |
1925 |
</td> |
</td> |
1926 |
</tr> |
</tr> |
1927 |
</thead> |
</thead> |
1955 |
|
|
1956 |
<tr valign="top"> |
<tr valign="top"> |
1957 |
<td width="66"> |
<td width="66"> |
1958 |
<p align="center" style="font-style: normal;">AU8820</p> |
<p align="center">AU8820</p> |
1959 |
</td> |
</td> |
1960 |
|
|
1961 |
<td width="142"> |
<td width="142"> |
1962 |
<p align="center" style="font-style: normal;">0xf800</p> |
<p align="center">0xf800</p> |
1963 |
</td> |
</td> |
1964 |
|
|
1965 |
<td width="148"> |
<td width="148"> |
1966 |
<p align="center" style="font-style: normal;">0xe000</p> |
<p align="center">0xe000</p> |
1967 |
</td> |
</td> |
1968 |
|
|
1969 |
<td width="140"> |
<td width="140"> |
1970 |
<p align="center" style="font-style: normal;">0xf840</p> |
<p align="center">0xf840</p> |
1971 |
</td> |
</td> |
1972 |
|
|
1973 |
<td width="160"> |
<td width="160"> |
1974 |
<p align="center" style="font-style: normal;">0xe800</p> |
<p align="center">0xe800</p> |
1975 |
</td> |
</td> |
1976 |
</tr> |
</tr> |
1977 |
|
|
1999 |
</tbody> |
</tbody> |
2000 |
</table> |
</table> |
2001 |
|
|
2002 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2003 |
</p> |
</p> |
2004 |
|
|
2005 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2006 |
</p> |
</p> |
2007 |
|
|
2008 |
<p style="margin-bottom: 0cm;">The FIFO_CTRL registers are a set of FIFO control register, which |
<p>The FIFO_CTRL registers are a set of FIFO control register, which |
2009 |
control the behavior and status of the FIFO data. There is a set of those for the ADB and another for the WT |
control the behavior and status of the FIFO data. There is a set of those for the ADB and another for the WT |
2010 |
engine.</p> |
engine.</p> |
2011 |
|
|
2012 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2013 |
</p> |
</p> |
2014 |
|
|
2015 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2016 |
</p> |
</p> |
2017 |
|
|
2018 |
<table width="664" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="664" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
2024 |
<thead> |
<thead> |
2025 |
<tr valign="top"> |
<tr valign="top"> |
2026 |
<td width="149"> |
<td width="149"> |
2027 |
<p align="center" style="font-style: normal;">FIFO_CTRL</p> |
<p align="center">FIFO_CTRL</p> |
2028 |
</td> |
</td> |
2029 |
|
|
2030 |
<th width="154"> |
<th width="154"> |
2031 |
<p style="font-style: normal;">AU8810</p> |
<p>AU8810</p> |
2032 |
</th> |
</th> |
2033 |
|
|
2034 |
<th width="167"> |
<th width="167"> |
2035 |
<p style="font-style: normal;">AU8820</p> |
<p>AU8820</p> |
2036 |
</th> |
</th> |
2037 |
|
|
2038 |
<th width="159"> |
<th width="159"> |
2039 |
<p style="font-style: normal;">AU8830</p> |
<p>AU8830</p> |
2040 |
</th> |
</th> |
2041 |
</tr> |
</tr> |
2042 |
</thead> |
</thead> |
2044 |
<tbody> |
<tbody> |
2045 |
<tr valign="top"> |
<tr valign="top"> |
2046 |
<td width="149"> |
<td width="149"> |
2047 |
<p align="left" style="font-style: normal;">set this reg. readonly</p> |
<p align="left">set this reg. readonly</p> |
2048 |
</td> |
</td> |
2049 |
|
|
2050 |
<th width="154"> |
<th width="154"> |
2051 |
<p style="font-style: normal;"><br /> |
<p><br /> |
2052 |
</p> |
</p> |
2053 |
</th> |
</th> |
2054 |
|
|
2055 |
<td width="167"> |
<td width="167"> |
2056 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000001</font></p> |
<p align="center"><font face="Andale Mono">0x00000001</font></p> |
2057 |
</td> |
</td> |
2058 |
|
|
2059 |
<td width="159"> |
<td width="159"> |
2060 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000001</font></p> |
<p align="center"><font face="Andale Mono">0x00000001</font></p> |
2061 |
</td> |
</td> |
2062 |
</tr> |
</tr> |
2063 |
|
|
2064 |
<tr valign="top"> |
<tr valign="top"> |
2065 |
<td width="149"> |
<td width="149"> |
2066 |
<p align="left" style="font-style: normal;">can do CTRL</p> |
<p align="left">can do CTRL</p> |
2067 |
</td> |
</td> |
2068 |
|
|
2069 |
<th width="154"> |
<th width="154"> |
2070 |
<p style="font-style: normal;"><br /> |
<p><br /> |
2071 |
</p> |
</p> |
2072 |
</th> |
</th> |
2073 |
|
|
2074 |
<td width="167"> |
<td width="167"> |
2075 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000002</font></p> |
<p align="center"><font face="Andale Mono">0x00000002</font></p> |
2076 |
</td> |
</td> |
2077 |
|
|
2078 |
<td width="159"> |
<td width="159"> |
2079 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000002</font></p> |
<p align="center"><font face="Andale Mono">0x00000002</font></p> |
2080 |
</td> |
</td> |
2081 |
</tr> |
</tr> |
2082 |
|
|
2083 |
<tr valign="top"> |
<tr valign="top"> |
2084 |
<td width="149"> |
<td width="149"> |
2085 |
<p style="font-style: normal;">Valid</p> |
<p>Valid</p> |
2086 |
</td> |
</td> |
2087 |
|
|
2088 |
<td width="154"> |
<td width="154"> |
2089 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2090 |
</p> |
</p> |
2091 |
</td> |
</td> |
2092 |
|
|
2093 |
<td width="167"> |
<td width="167"> |
2094 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000010</font></p> |
<p align="center"><font face="Andale Mono">0x00000010</font></p> |
2095 |
</td> |
</td> |
2096 |
|
|
2097 |
<td width="159"> |
<td width="159"> |
2098 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000010</font></p> |
<p align="center"><font face="Andale Mono">0x00000010</font></p> |
2099 |
</td> |
</td> |
2100 |
</tr> |
</tr> |
2101 |
|
|
2110 |
</td> |
</td> |
2111 |
|
|
2112 |
<td width="167"> |
<td width="167"> |
2113 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000020</font></p> |
<p align="center"><font face="Andale Mono">0x00000020</font></p> |
2114 |
</td> |
</td> |
2115 |
|
|
2116 |
<td width="159"> |
<td width="159"> |
2117 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000020</font></p> |
<p align="center"><font face="Andale Mono">0x00000020</font></p> |
2118 |
</td> |
</td> |
2119 |
</tr> |
</tr> |
2120 |
|
|
2129 |
</td> |
</td> |
2130 |
|
|
2131 |
<td width="167"> |
<td width="167"> |
2132 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00000800</font></p> |
<p align="center"><font face="Andale Mono">0x00000800</font></p> |
2133 |
</td> |
</td> |
2134 |
|
|
2135 |
<td width="159"> |
<td width="159"> |
2136 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2137 |
</p> |
</p> |
2138 |
</td> |
</td> |
2139 |
</tr> |
</tr> |
2149 |
</td> |
</td> |
2150 |
|
|
2151 |
<td width="167"> |
<td width="167"> |
2152 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x00010000</font></p> |
<p align="center"><font face="Andale Mono">0x00010000</font></p> |
2153 |
</td> |
</td> |
2154 |
|
|
2155 |
<td width="159"> |
<td width="159"> |
2156 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2157 |
</p> |
</p> |
2158 |
</td> |
</td> |
2159 |
</tr> |
</tr> |
2160 |
</tbody> |
</tbody> |
2161 |
</table> |
</table> |
2162 |
|
|
2163 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2164 |
</p> |
</p> |
2165 |
|
|
2166 |
<p style="margin-bottom: 0cm;">The FIFO data registers are the actual data registers of the FIFO. |
<p>The FIFO data registers are the actual data registers of the FIFO. |
2167 |
There is one FIFO for each audio data path, the ADB FIFO and the WT FIFO.</p> |
There is one FIFO for each audio data path, the ADB FIFO and the WT FIFO.</p> |
2168 |
|
|
2169 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2170 |
</p> |
</p> |
2171 |
<br /> |
<br /> |
2172 |
<br /> |
<br /> |
2173 |
<hr style="width: 100%; height: 2px;" /> |
<hr style="width: 100%; height: 2px;" /> |
2174 |
|
|
2175 |
<p style="margin-bottom: 0cm; page-break-before: always;"><font size="5" |
<p style="page-break-before: always;"><font size="5" |
2176 |
style="font-size: 20pt;"><i><b>Mixer</b></i></font></p> |
style="font-size: 20pt;"><i><b>Mixer</b></i></font></p> |
2177 |
|
|
2178 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2179 |
</p> |
</p> |
2180 |
|
|
2181 |
<p style="margin-bottom: 0cm;">Apart of the analog mixing of the AC97 codec, several digital sound |
<p>Apart of the analog mixing of the AC97 codec, several digital sound |
2182 |
source have to be combined/mixed before sending them to the AC97 codec through the AC97 5 wire link. The same is |
source have to be combined/mixed before sending them to the AC97 codec through the AC97 5 wire link. The same is |
2183 |
true for the data coming from the AC97 codec, while recording audio data. This is done on the Aureal sound chip |
true for the data coming from the AC97 codec, while recording audio data. This is done on the Aureal sound chip |
2184 |
(supposedly) using accumulators.<br /> |
(supposedly) using accumulators.<br /> |
2185 |
</p> |
</p> |
2186 |
|
|
2187 |
<p style="margin-bottom: 0cm;">The mixer posesses 16 mix elements, which can mix together 16 (or 32 ?) |
<p>The mixer posesses 16 mix elements, which can mix together 16 (or 32 ?) |
2188 |
different inputs (the same for all mix elements). The mix inputs are routeable, so a route can deliver audio data |
different inputs (the same for all mix elements). The mix inputs are routeable, so a route can deliver audio data |
2189 |
to a mix input, and the different mix elements can select the amount of audio data (input gain) of each mix input |
to a mix input, and the different mix elements can select the amount of audio data (input gain) of each mix input |
2190 |
and send it to each mix output, with a given output gain.Then again the mix outputs can be routed elsewhere.<br /> |
and send it to each mix output, with a given output gain.Then again the mix outputs can be routed elsewhere.<br /> |
2191 |
</p> |
</p> |
2192 |
|
|
2193 |
<p style="margin-bottom: 0cm;">The registers for the mixer are:<br /> |
<p>The registers for the mixer are:<br /> |
2194 |
</p> |
</p> |
2195 |
|
|
2196 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2197 |
</p> |
</p> |
2198 |
|
|
2199 |
<table width="695" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="695" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
2209 |
<thead> |
<thead> |
2210 |
<tr valign="top"> |
<tr valign="top"> |
2211 |
<td width="61"> |
<td width="61"> |
2212 |
<p align="center" style="font-style: normal;">Chip</p> |
<p align="center">Chip</p> |
2213 |
</td> |
</td> |
2214 |
|
|
2215 |
<th width="106"> |
<th width="106"> |
2216 |
<p style="font-style: normal;">SR_EN</p> |
<p>SR_EN</p> |
2217 |
</th> |
</th> |
2218 |
|
|
2219 |
<th width="77"> |
<th width="77"> |
2220 |
<p style="font-style: normal;">RTBASE<br /> |
<p>RTBASE<br /> |
2221 |
</p> |
</p> |
2222 |
</th> |
</th> |
2223 |
|
|
2225 |
</th> |
</th> |
2226 |
|
|
2227 |
<th width="77"> |
<th width="77"> |
2228 |
<p style="font-style: normal;">IE_BASE<br /> |
<p>IE_BASE<br /> |
2229 |
</p> |
</p> |
2230 |
</th> |
</th> |
2231 |
|
|
2232 |
<th width="79"> |
<th width="79"> |
2233 |
<p style="font-style: normal;">IVOL_A<br /> |
<p>IVOL_A<br /> |
2234 |
</p> |
</p> |
2235 |
</th> |
</th> |
2236 |
|
|
2237 |
<th width="78"> |
<th width="78"> |
2238 |
<p style="font-style: normal;">IVOL_B<br /> |
<p>IVOL_B<br /> |
2239 |
</p> |
</p> |
2240 |
</th> |
</th> |
2241 |
|
|
2242 |
<th width="70"> |
<th width="70"> |
2243 |
<p style="font-style: normal;">OVOL_A</p> |
<p>OVOL_A</p> |
2244 |
</th> |
</th> |
2245 |
|
|
2246 |
<td style="vertical-align: top;"><span style="font-weight: bold;">OVOL_B</span><br /> |
<td style="vertical-align: top;"><span style="font-weight: bold;">OVOL_B</span><br /> |
2251 |
<tbody> |
<tbody> |
2252 |
<tr valign="top"> |
<tr valign="top"> |
2253 |
<td width="61"> |
<td width="61"> |
2254 |
<p align="left" style="font-style: normal;">AU8810</p> |
<p align="left">AU8810</p> |
2255 |
</td> |
</td> |
2256 |
|
|
2257 |
<th width="106"> |
<th width="106"> |
2258 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2259 |
</p> |
</p> |
2260 |
</th> |
</th> |
2261 |
|
|
2262 |
<th width="77"> |
<th width="77"> |
2263 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2264 |
</p> |
</p> |
2265 |
</th> |
</th> |
2266 |
|
|
2267 |
<th width="81"> |
<th width="81"> |
2268 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2269 |
</p> |
</p> |
2270 |
</th> |
</th> |
2271 |
|
|
2272 |
<th width="77"> |
<th width="77"> |
2273 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2274 |
</p> |
</p> |
2275 |
</th> |
</th> |
2276 |
|
|
2277 |
<th width="79"> |
<th width="79"> |
2278 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2279 |
</p> |
</p> |
2280 |
</th> |
</th> |
2281 |
|
|
2282 |
<th width="78"> |
<th width="78"> |
2283 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2284 |
</p> |
</p> |
2285 |
</th> |
</th> |
2286 |
|
|
2287 |
<th width="70"> |
<th width="70"> |
2288 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2289 |
</p> |
</p> |
2290 |
</th> |
</th> |
2291 |
|
|
2295 |
|
|
2296 |
<tr valign="top"> |
<tr valign="top"> |
2297 |
<td width="61"> |
<td width="61"> |
2298 |
<p align="left" style="font-style: normal;">AU8820</p> |
<p align="left">AU8820</p> |
2299 |
</td> |
</td> |
2300 |
|
|
2301 |
<td width="106"> |
<td width="106"> |
2332 |
|
|
2333 |
<tr valign="top"> |
<tr valign="top"> |
2334 |
<td width="61"> |
<td width="61"> |
2335 |
<p align="left" style="font-style: normal;">AU8830</p> |
<p align="left">AU8830</p> |
2336 |
</td> |
</td> |
2337 |
|
|
2338 |
<th width="106"> |
<th width="106"> |
2339 |
<p align="center" style="font-style: normal;"><font face="Andale Mono">0x21f00</font></p> |
<p align="center"><font face="Andale Mono">0x21f00</font></p> |
2340 |
</th> |
</th> |
2341 |
|
|
2342 |
<th width="77"> |
<th width="77"> |
2343 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2344 |
</p> |
</p> |
2345 |
</th> |
</th> |
2346 |
|
|
2347 |
<th width="81"> |
<th width="81"> |
2348 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2349 |
</p> |
</p> |
2350 |
</th> |
</th> |
2351 |
|
|
2352 |
<th width="77"> |
<th width="77"> |
2353 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2354 |
</p> |
</p> |
2355 |
</th> |
</th> |
2356 |
|
|
2357 |
<th width="79"> |
<th width="79"> |
2358 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2359 |
</p> |
</p> |
2360 |
</th> |
</th> |
2361 |
|
|
2362 |
<th width="78"> |
<th width="78"> |
2363 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2364 |
</p> |
</p> |
2365 |
</th> |
</th> |
2366 |
|
|
2367 |
<th width="70"> |
<th width="70"> |
2368 |
<p align="center" style="font-style: normal;"><br /> |
<p align="center"><br /> |
2369 |
</p> |
</p> |
2370 |
</th> |
</th> |
2371 |
|
|
2375 |
</tbody> |
</tbody> |
2376 |
</table> |
</table> |
2377 |
|
|
2378 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2379 |
</p> |
</p> |
2380 |
|
|
2381 |
<p style="margin-bottom: 0cm;">SR_EN: SampleRate enable register for the mixer. Setting the nth bit, |
<p>SR_EN: SampleRate enable register for the mixer. Setting the nth bit, |
2382 |
enables communication to the nth routing channel.</p> |
enables communication to the nth routing channel.</p> |
2383 |
|
|
2384 |
<p style="margin-bottom: 0cm;">RTBASE: Some kind of route base register.<br /> |
<p>RTBASE: Some kind of route base register.<br /> |
2385 |
</p> |
</p> |
2386 |
|
|
2387 |
<p style="margin-bottom: 0cm;">IE_BASE: Input Enable base register. the complete register address is |
<p>IE_BASE: Input Enable base register. the complete register address is |
2388 |
"IE_BASE  + ((input / 4) + (mix * 8)) * 4".<br /> |
"IE_BASE  + ((input / 4) + (mix * 8)) * 4".<br /> |
2389 |
</p> |
</p> |
2390 |
|
|
2391 |
<p style="margin-bottom: 0cm;">IVOL_A: Input gain base register. The address for the mix element "mix" |
<p>IVOL_A: Input gain base register. The address for the mix element "mix" |
2392 |
and input "input" is "IVOL_A + (((mix * 32) + mixin) * 4)".<br /> |
and input "input" is "IVOL_A + (((mix * 32) + mixin) * 4)".<br /> |
2393 |
</p> |
</p> |
2394 |
|
|
2395 |
<p style="margin-bottom: 0cm;">OVOL_A: Output volume base register. The address for the mix element "mix" is |
<p>OVOL_A: Output volume base register. The address for the mix element "mix" is |
2396 |
"OVOL_A + (mix * 4)".<br /> |
"OVOL_A + (mix * 4)".<br /> |
2397 |
</p> |
</p> |
2398 |
|
|
2399 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2400 |
</p> |
</p> |
2401 |
<hr style="width: 100%; height: 2px;" /> |
<hr style="width: 100%; height: 2px;" /> |
2402 |
|
|
2403 |
<p style="margin-bottom: 0cm;"><b><i><font size="5" style="font-size: 20pt;">Sample Rate |
<p><b><i><font size="5" style="font-size: 20pt;">Sample Rate |
2404 |
Converter</font></i></b></p> |
Converter</font></i></b></p> |
2405 |
|
|
2406 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2407 |
</p> |
</p> |
2408 |
|
|
2409 |
<p style="margin-bottom: 0cm;">This functional block, connectible through routes, as it name states, |
<p>This functional block, connectible through routes, as it name states, |
2410 |
converts the sample rate of its incoming audio data, you guess it, to 48KHz, the sample rate of the AC97 codec.</p> |
converts the sample rate of its incoming audio data, you guess it, to 48KHz, the sample rate of the AC97 codec.</p> |
2411 |
|
|
2412 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2413 |
</p> |
</p> |
2414 |
|
|
2415 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2416 |
</p> |
</p> |
2417 |
|
|
2418 |
<table width="732" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="732" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
2428 |
<thead> |
<thead> |
2429 |
<tr valign="top"> |
<tr valign="top"> |
2430 |
<td width="62"> |
<td width="62"> |
2431 |
<p align="center" style="font-style: normal;">Chip</p> |
<p align="center">Chip</p> |
2432 |
</td> |
</td> |
2433 |
|
|
2434 |
<th width="105"> |
<th width="105"> |
2435 |
<p style="font-style: normal;">SR_EN</p> |
<p>SR_EN</p> |
2436 |
</th> |
</th> |
2437 |
|
|
2438 |
<td style="vertical-align: top;"><span style="font-weight: bold;">RTBASE</span><br /> |
<td style="vertical-align: top;"><span style="font-weight: bold;">RTBASE</span><br /> |
2439 |
</td> |
</td> |
2440 |
|
|
2441 |
<th width="75"> |
<th width="75"> |
2442 |
<p style="font-style: normal;">SOURCE</p> |
<p>SOURCE</p> |
2443 |
</th> |
</th> |
2444 |
|
|
2445 |
<th width="75"> |
<th width="75"> |
2446 |
<p style="font-style: normal;">CNVR</p> |
<p>CNVR</p> |
2447 |
</th> |
</th> |
2448 |
|
|
2449 |
<th width="88"> |
<th width="88"> |
2450 |
<p style="font-style: normal;">DRIFT2</p> |
<p>DRIFT2</p> |
2451 |
</th> |
</th> |
2452 |
|
|
2453 |
<th width="99"> |
<th width="99"> |
2454 |
<p style="font-style: normal;">BUFFER</p> |
<p>BUFFER</p> |
2455 |
</th> |
</th> |
2456 |
|
|
2457 |
<th width="77"> |
<th width="77"> |
2458 |
<p style="font-style: normal;">?<br /> |
<p>?<br /> |
2459 |
</p> |
</p> |
2460 |
</th> |
</th> |
2461 |
|
|
2462 |
<th width="85"> |
<th width="85"> |
2463 |
<p style="font-style: normal;">DRIFT</p> |
<p>DRIFT</p> |
2464 |
</th> |
</th> |
2465 |
</tr> |
</tr> |
2466 |
</thead> |
</thead> |
2468 |
<tbody> |
<tbody> |
2469 |
<tr valign="top"> |
<tr valign="top"> |
2470 |
<td width="62"> |
<td width="62"> |
2471 |
<p align="left" style="font-style: normal;">AU8810</p> |
<p align="left">AU8810</p> |
2472 |
</td> |
</td> |
2473 |
|
|
2474 |
<th width="105" style="font-family: monospace;"> |
<th width="105" style="font-family: monospace;"> |
2475 |
|
|
2476 |
<p align="center" style="font-style: normal;"><big><br /> |
<p align="center"><big><br /> |
2477 |
</big></p> |
</big></p> |
2478 |
</th> |
</th> |
2479 |
|
|
2482 |
|
|
2483 |
<th width="75" style="font-family: monospace;"> |
<th width="75" style="font-family: monospace;"> |
2484 |
|
|
2485 |
<p align="center" style="font-style: normal;"><big><br /> |
<p align="center"><big><br /> |
2486 |
</big></p> |
</big></p> |
2487 |
</th> |
</th> |
2488 |
|
|
2489 |
<th width="75" style="font-family: monospace;"> |
<th width="75" style="font-family: monospace;"> |
2490 |
|
|
2491 |
<p align="center" style="font-style: normal;"><big><br /> |
<p align="center"><big><br /> |
2492 |
</big></p> |
</big></p> |
2493 |
</th> |
</th> |
2494 |
|
|
2495 |
<th width="88" style="font-family: monospace;"> |
<th width="88" style="font-family: monospace;"> |
2496 |
|
|
2497 |
<p align="center" style="font-style: normal;"><big><br /> |
<p align="center"><big><br /> |
2498 |
</big></p> |
</big></p> |
2499 |
</th> |
</th> |
2500 |
|
|
2501 |
<th width="99" style="font-family: monospace;"> |
<th width="99" style="font-family: monospace;"> |
2502 |
|
|
2503 |
<p align="center" style="font-style: normal;"><big><br /> |
<p align="center"><big><br /> |
2504 |
</big></p> |
</big></p> |
2505 |
</th> |
</th> |
2506 |
|
|
2507 |
<th width="77" style="font-family: monospace;"> |
<th width="77" style="font-family: monospace;"> |
2508 |
|
|
2509 |
<p align="center" style="font-style: normal;"><big><br /> |
<p align="center"><big><br /> |
2510 |
</big></p> |
</big></p> |
2511 |
</th> |
</th> |
2512 |
|
|
2516 |
|
|
2517 |
<tr valign="top"> |
<tr valign="top"> |
2518 |
<td width="62"> |
<td width="62"> |
2519 |
<p align="left" style="font-style: normal;">AU8820</p> |
<p align="left">AU8820</p> |
2520 |
</td> |
</td> |
2521 |
|
|
2522 |
<td width="105" style="font-family: monospace;"> |
<td width="105" style="font-family: monospace;"> |
2555 |
|
|
2556 |
<tr valign="top"> |
<tr valign="top"> |
2557 |
<td width="62"> |
<td width="62"> |
2558 |
<p align="left" style="font-style: normal;">AU8830</p> |
<p align="left">AU8830</p> |
2559 |
</td> |
</td> |
2560 |
|
|
2561 |
<th width="105" style="font-family: monospace;"> |
<th width="105" style="font-family: monospace;"> |
2562 |
<p align="center" style="font-style: normal;"><font size="+1"><br /> |
<p align="center"><font size="+1"><br /> |
2563 |
</font></p> |
</font></p> |
2564 |
</th> |
</th> |
2565 |
|
|
2567 |
</font></td> |
</font></td> |
2568 |
|
|
2569 |
<th width="75" style="font-family: monospace;"> |
<th width="75" style="font-family: monospace;"> |
2570 |
<p align="center" style="font-style: normal;"><font size="+1"><br /> |
<p align="center"><font size="+1"><br /> |
2571 |
</font></p> |
</font></p> |
2572 |
</th> |
</th> |
2573 |
|
|
2574 |
<th width="75" style="font-family: monospace;"> |
<th width="75" style="font-family: monospace;"> |
2575 |
<p align="center" style="font-style: normal;"><font size="+1"><br /> |
<p align="center"><font size="+1"><br /> |
2576 |
</font></p> |
</font></p> |
2577 |
</th> |
</th> |
2578 |
|
|
2579 |
<th width="88" style="font-family: monospace;"> |
<th width="88" style="font-family: monospace;"> |
2580 |
<p align="center" style="font-style: normal;"><font size="+1"><br /> |
<p align="center"><font size="+1"><br /> |
2581 |
</font></p> |
</font></p> |
2582 |
</th> |
</th> |
2583 |
|
|
2584 |
<th width="99" style="font-family: monospace;"> |
<th width="99" style="font-family: monospace;"> |
2585 |
<p align="center" style="font-style: normal;"><font size="+1"><br /> |
<p align="center"><font size="+1"><br /> |
2586 |
</font></p> |
</font></p> |
2587 |
</th> |
</th> |
2588 |
|
|
2595 |
</tbody> |
</tbody> |
2596 |
</table> |
</table> |
2597 |
|
|
2598 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2599 |
</p> |
</p> |
2600 |
<br /> |
<br /> |
2601 |
<br /> |
<br /> |
2678 |
</table> |
</table> |
2679 |
<br /> |
<br /> |
2680 |
|
|
2681 |
<p style="margin-bottom: 0cm;">SAMPLE_TIMER</p> |
<p>SAMPLE_TIMER</p> |
2682 |
|
|
2683 |
<p style="margin-bottom: 0cm;">This register holds the sample time. This register is read only.</p> |
<p>This register holds the sample time. This register is read only.</p> |
2684 |
<br /> |
<br /> |
2685 |
<br /> |
<br /> |
2686 |
|
|
2687 |
<p align="left" style="margin-bottom: 0cm; font-style: normal;">TIMER_UNK1</p> |
<p align="left">TIMER_UNK1</p> |
2688 |
|
|
2689 |
<p style="margin-bottom: 0cm;">This register when read clears the Timer interrupt. When written to |
<p>This register when read clears the Timer interrupt. When written to |
2690 |
allows to set the timer timeout value (period). It looks like there are some flags mapped to this register, but |
allows to set the timer timeout value (period). It looks like there are some flags mapped to this register, but |
2691 |
their use is unknown.</p> |
their use is unknown.</p> |
2692 |
|
|
2693 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2694 |
</p> |
</p> |
2695 |
|
|
2696 |
<p style="margin-bottom: 0cm;">AU8820: upper limit appears to be 0x3ffff<br /> |
<p>AU8820: upper limit appears to be 0x3ffff<br /> |
2697 |
masks: 0x800000, 0xffffff, 0xff000000</p> |
masks: 0x800000, 0xffffff, 0xff000000</p> |
2698 |
|
|
2699 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2700 |
</p> |
</p> |
2701 |
<hr style="width: 100%; height: 2px;" /> |
<hr style="width: 100%; height: 2px;" /> |
2702 |
|
|
2703 |
<p style="margin-bottom: 0cm; page-break-before: always;"><font size="5" |
<p style="page-break-before: always;"><font size="5" |
2704 |
style="font-size: 20pt;"><i><b>ROUTING</b></i></font></p> |
style="font-size: 20pt;"><i><b>ROUTING</b></i></font></p> |
2705 |
|
|
2706 |
<p style="margin-bottom: 0cm; font-style: normal;">The routes and addresses structure:<br /> |
<p>The routes and addresses structure:<br /> |
2707 |
Source addresses in the higher bits and destination address in the lower bits. The address size is different for |
Source addresses in the higher bits and destination address in the lower bits. The address size is different for |
2708 |
the different Aureal chips. the AU8810 and AU8830 use 8 bit addresses while the AU8820 uses 7 bit addresses.<br /> |
the different Aureal chips. the AU8810 and AU8830 use 8 bit addresses while the AU8820 uses 7 bit addresses.<br /> |
2709 |
</p> |
</p> |
2710 |
|
|
2711 |
<p style="margin-bottom: 0cm; font-style: normal;">There are MMIO registers for the routing |
<p>There are MMIO registers for the routing |
2712 |
information. The routing information for a given channel is structured in a daisy chain fashion. There is a entry |
information. The routing information for a given channel is structured in a daisy chain fashion. There is a entry |
2713 |
point register for each channel. The value of that register contains the first route. There is another set of |
point register for each channel. The value of that register contains the first route. There is another set of |
2714 |
registers, one asociated to each routeable functional block, which contain the next route for the channel.<br /> |
registers, one asociated to each routeable functional block, which contain the next route for the channel.<br /> |
2729 |
</li> |
</li> |
2730 |
</ol> |
</ol> |
2731 |
|
|
2732 |
<p style="margin-bottom: 0cm; font-style: normal;">If there are no more routes on a channel, the route |
<p>If there are no more routes on a channel, the route |
2733 |
register of the last target contains all route bits set.<br /> |
register of the last target contains all route bits set.<br /> |
2734 |
</p> |
</p> |
2735 |
|
|
2736 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
2737 |
The route registers are as follows:<br /> |
The route registers are as follows:<br /> |
2738 |
</p> |
</p> |
2739 |
|
|
2740 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
2741 |
</p> |
</p> |
2742 |
|
|
2743 |
<table width="372" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
<table width="372" border="1" bordercolor="#000000" cellpadding="4" cellspacing="0"> |
2748 |
<thead> |
<thead> |
2749 |
<tr valign="top"> |
<tr valign="top"> |
2750 |
<td width="66"> |
<td width="66"> |
2751 |
<p align="center" style="font-style: normal;">Chipset</p> |
<p align="center">Chipset</p> |
2752 |
</td> |
</td> |
2753 |
|
|
2754 |
<td width="142"> |
<td width="142"> |
2755 |
<p align="center" style="font-style: normal;">CHN_BASE</p> |
<p align="center">CHN_BASE</p> |
2756 |
</td> |
</td> |
2757 |
|
|
2758 |
<td width="137"> |
<td width="137"> |
2759 |
<p align="center" style="font-style: normal;">RT_BASE</p> |
<p align="center">RT_BASE</p> |
2760 |
</td> |
</td> |
2761 |
</tr> |
</tr> |
2762 |
</thead> |
</thead> |
2778 |
|
|
2779 |
<tr valign="top"> |
<tr valign="top"> |
2780 |
<td width="66"> |
<td width="66"> |
2781 |
<p align="center" style="font-style: normal;">AU8820</p> |
<p align="center">AU8820</p> |
2782 |
</td> |
</td> |
2783 |
|
|
2784 |
<td width="142"> |
<td width="142"> |
2785 |
<p align="center" style="font-style: normal;">0x1099c</p> |
<p align="center">0x1099c</p> |
2786 |
</td> |
</td> |
2787 |
|
|
2788 |
<td width="137"> |
<td width="137"> |
2789 |
<p align="center" style="font-style: normal;">0x10800</p> |
<p align="center">0x10800</p> |
2790 |
</td> |
</td> |
2791 |
</tr> |
</tr> |
2792 |
|
|
2806 |
</tbody> |
</tbody> |
2807 |
</table> |
</table> |
2808 |
|
|
2809 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
2810 |
CHN_BASE: Entry point register for each channel base register. They are at dword offsets, so the entry point |
CHN_BASE: Entry point register for each channel base register. They are at dword offsets, so the entry point |
2811 |
register for channel X is equal to (CHN_BASE + (X*4)).<br /> |
register for channel X is equal to (CHN_BASE + (X*4)).<br /> |
2812 |
</p> |
</p> |
2813 |
|
|
2814 |
<p style="margin-bottom: 0cm; font-style: normal;">RT_BASE: Base register of the other routes of a |
<p>RT_BASE: Base register of the other routes of a |
2815 |
channel. There is one asociated for each routeable functional block. For example the next route after a route that |
channel. There is one asociated for each routeable functional block. For example the next route after a route that |
2816 |
had as target the address Y would be (RT_BASE + (Y*4)).</p> |
had as target the address Y would be (RT_BASE + (Y*4)).</p> |
2817 |
|
|
2818 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
2819 |
<font size="3">Example:</font></p> |
<font size="3">Example:</font></p> |
2820 |
|
|
2821 |
<p style="margin-bottom: 0cm; font-style: normal;"><font size="3">CHN_BASE[0x11]:    |
<p><font size="3">CHN_BASE[0x11]:    |
2822 |
    (0x20 << VAL_SHIFT) | 0x31<br /> |
    (0x20 << VAL_SHIFT) | 0x31<br /> |
2823 |
ROUTE_BASE[0x31]:    (0x21 << VAL_SHIFT) | 0x32<br /> |
ROUTE_BASE[0x31]:    (0x21 << VAL_SHIFT) | 0x32<br /> |
2824 |
ROUTE_BASE[0x32]:    (0x22 << VAL_SHIFT) | 0x58<br /> |
ROUTE_BASE[0x32]:    (0x22 << VAL_SHIFT) | 0x58<br /> |
2829 |
ROUTE_BASE[0x35]:    0x3fff<br /> |
ROUTE_BASE[0x35]:    0x3fff<br /> |
2830 |
</font></p> |
</font></p> |
2831 |
|
|
2832 |
<p style="margin-bottom: 0cm; font-style: normal;"><font size="3"><br /> |
<p><font size="3"><br /> |
2833 |
</font></p> |
</font></p> |
2834 |
|
|
2835 |
<p style="margin-bottom: 0cm; font-style: normal;"><font size="3">VAL_SHIFT is 8 bits for the AU8810 |
<p><font size="3">VAL_SHIFT is 8 bits for the AU8810 |
2836 |
and AU8830 and 7 bits for the AU8820 chips.</font></p> |
and AU8830 and 7 bits for the AU8820 chips.</font></p> |
2837 |
|
|
2838 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
2839 |
</p> |
</p> |
2840 |
|
|
2841 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
2842 |
<font size="3">The different target route objects that can be fed with a given channel data are explained |
<font size="3">The different target route objects that can be fed with a given channel data are explained |
2843 |
below.</font></p> |
below.</font></p> |
2844 |
|
|
2845 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
2846 |
</p> |
</p> |
2847 |
Codasdda |
Codasdda |
2848 |
|
|
3018 |
</tbody> |
</tbody> |
3019 |
</table> |
</table> |
3020 |
|
|
3021 |
<p style="margin-bottom: 0cm; font-style: normal;"><br /> |
<p><br /> |
3022 |
</p> |
</p> |
3023 |
|
|
3024 |
<p style="margin-bottom: 0cm;"><br /> |
<p><br /> |
3025 |
</p> |
</p> |
3026 |
</body> |
</body> |
3027 |
</html> |
</html> |