3 |
* for a Wavetable synthesizer. |
* for a Wavetable synthesizer. |
4 |
*/ |
*/ |
5 |
#include "au88x0.h" |
#include "au88x0.h" |
6 |
|
#include "au88x0_wt.h" |
7 |
|
|
8 |
void vortex_fifo_setwtvalid(vortex_t *vortex, int fifo, int en); |
void vortex_fifo_setwtvalid(vortex_t *vortex, int fifo, int en); |
9 |
void vortex_connection_adb_mixin(vortex_t *vortex, int en, unsigned char channel, |
void vortex_connection_adb_mixin(vortex_t *vortex, int en, unsigned char channel, |
10 |
unsigned char source, unsigned char mixin); |
unsigned char source, unsigned char mixin); |
11 |
void vortex_connection_mixin_mix(vortex_t *vortex, int en, unsigned char mixin, unsigned char mix, int a); |
void vortex_connection_mixin_mix(vortex_t *vortex, int en, unsigned char mixin, unsigned char mix, int a); |
12 |
void vortex_fifo_wtinitialize(vortex_t *vortex, int fifo, int j); |
void vortex_fifo_wtinitialize(vortex_t *vortex, int fifo, int j); |
13 |
|
int vortex_wt_SetReg(vortex_t *vortex, unsigned char reg, int wt, unsigned long val); |
14 |
/* WT */ |
/* WT */ |
15 |
|
|
16 |
void vortex_wt_setstereo(vortex_t *vortex, u32 wt, u32 stereo) { |
void vortex_wt_setstereo(vortex_t *vortex, u32 wt, u32 stereo) { |
17 |
int temp; |
int temp; |
18 |
|
|
19 |
temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2)); |
//temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2)); |
20 |
|
temp = hwread(vortex->mmio, WT_STEREO(wt)); |
21 |
temp = (temp & 0xfe) | (stereo & 1); |
temp = (temp & 0xfe) | (stereo & 1); |
22 |
hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp); |
//hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp); |
23 |
|
hwwrite(vortex->mmio, WT_STEREO(wt), temp); |
24 |
} |
} |
25 |
|
|
26 |
void vortex_wt_setdsout(vortex_t *vortex, u32 wt, int en) { |
void vortex_wt_setdsout(vortex_t *vortex, u32 wt, int en) { |
|
#ifndef CHIP_AU8820 |
|
27 |
int temp; |
int temp; |
28 |
|
|
29 |
temp = hwread(vortex->mmio, ((wt >> 0x5)<< 0xf) + 0x8); |
/* There is one DSREG register for each bank (32 voices each). */ |
30 |
|
temp = hwread(vortex->mmio, WT_DSREG((wt>=0x20)?1:0)); |
31 |
if (en) |
if (en) |
32 |
temp |= (1 << (wt & 0x1f)); |
temp |= (1 << (wt & 0x1f)); |
33 |
else |
else |
34 |
temp &= (1 << ~(wt & 0x1f)); |
temp &= (1 << ~(wt & 0x1f)); |
35 |
hwwrite(vortex->mmio, ((wt >> 0x5)<< 0xf) + 0x8, temp); |
hwwrite(vortex->mmio, WT_DSREG((wt>=0x20)?1:0), temp); |
|
#endif |
|
36 |
} |
} |
37 |
|
|
38 |
// WT routing is still a mistery. |
// WT routing is still a mistery. |
39 |
int vortex_wt_allocroute(vortex_t *vortex, int dma, int nr_ch) { |
int vortex_wt_allocroute(vortex_t *vortex, int wt, int nr_ch) { |
40 |
|
int temp; |
41 |
|
|
42 |
//FIXME: WT audio routing. |
//FIXME: WT audio routing. |
43 |
if (nr_ch) { |
if (nr_ch) { |
44 |
vortex_fifo_wtinitialize(vortex, dma, 1); |
vortex_fifo_wtinitialize(vortex, wt, 2); |
45 |
vortex_wt_setstereo(vortex, dma, nr_ch-1); |
vortex_fifo_setwtvalid(vortex, wt, 1); |
46 |
} else |
vortex_wt_setstereo(vortex, wt, nr_ch-1); |
47 |
vortex_fifo_setwtvalid(vortex, dma, 0); |
} else |
48 |
vortex_wt_setdsout(vortex, dma, 1); |
vortex_fifo_setwtvalid(vortex, wt, 0); |
49 |
return 0; |
|
50 |
} |
vortex_wt_setdsout(vortex, wt, 1); |
51 |
void vortex_wt_connect(vortex_t *vortex, int en, unsigned char mixers[]) { |
hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000); |
52 |
|
//hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff); |
53 |
vortex->mixwt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXIN); |
#ifdef CHIP_AU8830 |
54 |
vortex->mixwt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXIN); |
hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000); |
55 |
|
//hwwrite(vortex->mmio, WT_GMODE(1), 0xffffffff); |
56 |
vortex_connection_adb_mixin(vortex, en, 0x11, ADB_WTOUT(0), vortex->mixwt[0]); |
#endif |
57 |
vortex_connection_adb_mixin(vortex, en, 0x11, ADB_WTOUT(1), vortex->mixwt[1]); |
hwwrite(vortex->mmio, WT_PARM(wt,0), 0); |
58 |
vortex_connection_mixin_mix(vortex, en, vortex->mixwt[0], mixers[0], 0); |
hwwrite(vortex->mmio, WT_PARM(wt,1), 0); |
59 |
vortex_connection_mixin_mix(vortex, en, vortex->mixwt[1], mixers[1], 0); |
hwwrite(vortex->mmio, WT_PARM(wt,2), 0); |
60 |
if (VORTEX_IS_QUAD(vortex)) { |
|
61 |
vortex_connection_mixin_mix(vortex, en, vortex->mixwt[0], mixers[2], 0); |
temp = hwread(vortex->mmio, WT_PARM(wt,3)); |
62 |
vortex_connection_mixin_mix(vortex, en, vortex->mixwt[1], mixers[3], 0); |
printk("vortex: WT PARM3: %x\n", temp); |
63 |
|
hwwrite(vortex->mmio, WT_PARM(wt,3), temp); |
64 |
|
|
65 |
|
hwwrite(vortex->mmio, WT_DELAY(wt,0), 0); |
66 |
|
hwwrite(vortex->mmio, WT_DELAY(wt,1), 0); |
67 |
|
hwwrite(vortex->mmio, WT_DELAY(wt,2), 0); |
68 |
|
hwwrite(vortex->mmio, WT_DELAY(wt,3), 0); |
69 |
|
|
70 |
|
printk("vortex: WT GMODE: %x\n", hwread(vortex->mmio, WT_GMODE(wt))); |
71 |
|
|
72 |
|
hwwrite(vortex->mmio, WT_PARM(wt,0), 0xcf003d43); |
73 |
|
hwwrite(vortex->mmio, WT_PARM(wt,1), 0xcf003d43); |
74 |
|
hwwrite(vortex->mmio, WT_PARM(wt,2), 0); |
75 |
|
hwwrite(vortex->mmio, WT_PARM(wt,3), 0xcff1c810); |
76 |
|
hwwrite(vortex->mmio, WT_PARM(wt,0), 0xcfb23e2f); |
77 |
|
hwwrite(vortex->mmio, WT_PARM(wt,1), 0xcfb23e2f); |
78 |
|
|
79 |
|
return 0; |
80 |
|
} |
81 |
|
|
82 |
|
void vortex_wt_connect(vortex_t *vortex, int en) { |
83 |
|
int i,ii; |
84 |
|
|
85 |
|
#define NR_WTROUTES 6 |
86 |
|
#ifdef CHIP_AU8830 |
87 |
|
#define NR_WTBLOCKS 2 |
88 |
|
#else |
89 |
|
#define NR_WTBLOCKS 1 |
90 |
|
#endif |
91 |
|
printk("vortex: WT connected\n"); |
92 |
|
for (i=0; i<NR_WTBLOCKS; i++) { |
93 |
|
for (ii=0; ii<NR_WTROUTES; ii++) { |
94 |
|
vortex->mixwt[(i*NR_WTROUTES)+ii] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXIN); |
95 |
|
|
96 |
|
vortex_connection_adb_mixin(vortex, en, 0x11, ADB_WTOUT(i,ii+0x20), vortex->mixwt[(i*NR_WTROUTES)+ii]); |
97 |
|
vortex_connection_mixin_mix(vortex, en, vortex->mixwt[(i*NR_WTROUTES)+ii], vortex->mixplayb[ii % 2], 0); |
98 |
|
vortex_mix_setinputvolumebyte(vortex, vortex->mixplayb[ii % 2], vortex->mixwt[(i*NR_WTROUTES)+ii], MIX_DEFIGAIN); |
99 |
|
if (VORTEX_IS_QUAD(vortex)) { |
100 |
|
vortex_connection_mixin_mix(vortex, en, vortex->mixwt[(i*NR_WTROUTES)+ii], vortex->mixplayb[2+(ii%2)], 0); |
101 |
|
vortex_mix_setinputvolumebyte(vortex, vortex->mixplayb[2+(ii%2)], vortex->mixwt[(i*NR_WTROUTES)+ii], MIX_DEFIGAIN); |
102 |
|
} |
103 |
|
} |
104 |
|
} |
105 |
|
for (i=0; i<NR_WT; i++) { |
106 |
|
hwwrite(vortex->mmio, WT_RUN(i), 1); |
107 |
} |
} |
108 |
} |
} |
109 |
|
|
110 |
/* Read WT Register */ |
/* Read WT Register */ |
111 |
int vortex_wt_GetReg(vortex_t *vortex, char a, int *b) { |
int vortex_wt_GetReg(vortex_t *vortex, char reg, int wt) { |
112 |
int eax, esi; |
//int eax, esi; |
113 |
|
|
114 |
if (a != 4) { |
if (reg == 4) { |
115 |
if (a == 7) |
return hwread(vortex->mmio, WT_PARM(wt,3)); |
|
return 0; |
|
|
return hwread(vortex->mmio, (*b << 0xf) + 0x10); |
|
116 |
} |
} |
117 |
esi = b[1]; |
if (reg == 7) { |
118 |
eax = ((((a & 0x1f) + b[1]) / 32) & 0xff) << 0xb; |
return hwread(vortex->mmio, WT_GMODE(wt));; |
119 |
if (esi < 0) |
} |
120 |
esi = ((esi-1)|0x0FFFFFFE0)+1; |
|
121 |
esi &= 0xff; |
return 0; |
|
hwread(vortex->mmio, ((eax + esi) << 4) + 0x20c); |
|
|
|
|
|
return 8; |
|
122 |
} |
} |
123 |
|
|
124 |
/* |
/* WT hardware abstraction layer generic register interface. */ |
125 |
WT hardware abstraction layer generic register interface. |
int vortex_wt_SetReg2(vortex_t *vortex, unsigned char reg, int wt, unsigned short val) { |
126 |
a: type of register or register set to be accessed. |
/* |
|
b: Register offset |
|
|
c: Register value (or values) to be written. |
|
|
*/ |
|
|
int vortex_wt_SetReg2(vortex_t *vortex, unsigned char a, int b, unsigned short c) { |
|
127 |
int eax, edx; |
int eax, edx; |
128 |
|
|
129 |
if (b >= NR_WT) // 0x40 -> NR_WT |
if (wt >= NR_WT) // 0x40 -> NR_WT |
|
return 0; |
|
|
|
|
|
/* cdq: 64 bit sign extender */ |
|
|
eax = b; |
|
|
if (eax<0) |
|
|
edx = 0xffffffff & 0x1f; |
|
|
else |
|
|
edx = 0; |
|
|
eax += edx; |
|
|
edx = b & 0x8000001f; |
|
|
eax = (eax / 32) | ((char)b); |
|
|
if (eax < 0) |
|
|
edx = ((edx-1)|0x0FFFFFFE0)+1; |
|
|
|
|
|
// esp+4 = edx & 0xff |
|
|
|
|
|
if ((eax & 0xff) >= 2) |
|
130 |
return 0; |
return 0; |
131 |
|
|
132 |
if ((a & 0xff) - 0x20) { |
if ((reg - 0x20) > 0) { |
133 |
if ((a & 0xff) - 0x21) |
if ((reg - 0x21) != 0) |
134 |
return 0; |
return 0; |
135 |
eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x208; |
eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x208; // param 2 |
136 |
} else { |
} else { |
137 |
eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x20a; |
eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x20a; // param 3 |
138 |
} |
} |
139 |
hwwrite(vortex->mmio, eax, c); |
hwwrite(vortex->mmio, eax, c); |
140 |
|
*/ |
141 |
return 1; |
return 1; |
142 |
} |
} |
143 |
|
|
144 |
|
|
145 |
/*public: void __thiscall CWTHal::SetReg(unsigned char,int,unsigned long) */ |
/*public: void __thiscall CWTHal::SetReg(unsigned char,int,unsigned long) */ |
146 |
int vortex_wt_SetReg(vortex_t *vortex, unsigned char a, int b, unsigned long c) { |
int vortex_wt_SetReg(vortex_t *vortex, unsigned char reg, int wt, unsigned long val) { |
147 |
// a : type |
int ecx; |
|
// b : voice |
|
|
// c : data |
|
|
|
|
|
int ecx, edx, esp4, eax; |
|
|
|
|
|
if (b >= NR_WT) // 0x40 -> NR_WT |
|
|
return 0; |
|
|
|
|
|
#if 0 //original_code |
|
|
eax = ecx = b; |
|
|
/* cdq: 64 bit sign extender */ |
|
|
if (eax<0) |
|
|
edx = 0xffffffff; |
|
|
else |
|
|
edx = 0; |
|
|
eax += edx & 0x1f; |
|
|
edx = ecx & 0x8000001f; |
|
|
eax = (eax / 32) | ((char)b); |
|
|
// This "if" semes to be useless ... |
|
|
if (eax < 0) |
|
|
edx = ((edx-1)|0x0FFFFFFE0)+1; |
|
148 |
|
|
149 |
esp4 = (char)edx; |
if ((reg==5)||((reg>=7)&&(reg<=10))||(reg==0xc)) { |
150 |
|
if (wt >= (NR_WT/NR_WT_PB)) { |
151 |
// eax is the WT bank. AU8830 has 2 banks: 0 and 1. |
printk("vortex: WT SetReg: bank out of range. reg=0x%x, wt=%d\n", reg, wt); |
152 |
if ((char)eax >= 2) |
return 0; |
153 |
return 0; |
} |
154 |
|
} else { |
155 |
#else //rewritting_code |
if (wt >= NR_WT) { |
156 |
esp4 = b & 0x1f; |
printk("vortex: WT SetReg: voice out of range\n"); |
157 |
b = b >> 5; |
return 0; |
158 |
|
} |
159 |
#endif |
} |
160 |
|
if (reg > 0xc) |
|
if (a > 0xc) |
|
161 |
return 0; |
return 0; |
162 |
|
|
163 |
switch (a) { |
switch (reg) { |
164 |
case 0 : |
/* Voice specific parameters */ |
165 |
eax = ((b << 0xd) + esp4) << 2; |
case 0 : /* running */ |
166 |
hwwrite(vortex->mmio, 0x180 + eax, c); |
//printk("vortex: WT SetReg(0x%x) = 0x%08x\n", WT_RUN(wt), (int)val); |
167 |
|
hwwrite(vortex->mmio, WT_RUN(wt), val); |
168 |
return 0xc; |
return 0xc; |
169 |
break; |
break; |
170 |
case 1 : |
case 1 : /* param 0 */ |
171 |
edx = ((b & 0xff) << 0xb) + (esp4 & 0xff); |
//printk("vortex: WT SetReg(0x%x) = 0x%08x\n", WT_PARM(wt,0), (int)val); |
172 |
hwwrite(vortex->mmio, 0x20 + (edx << 4), c); |
hwwrite(vortex->mmio, WT_PARM(wt,0), val); |
173 |
return 0xc; |
return 0xc; |
174 |
break; |
break; |
175 |
case 2 : |
case 2 : /* param 1 */ |
176 |
eax = ((b & 0xff) << 0xb) + (esp4 & 0xff); |
//printk("vortex: WT SetReg(0x%x) = 0x%08x\n", WT_PARM(wt,1), (int)val); |
177 |
hwwrite(vortex->mmio, 0x204 + (eax << 4), c); |
hwwrite(vortex->mmio, WT_PARM(wt,1), val); |
178 |
return 0xc; |
return 0xc; |
179 |
break; |
break; |
180 |
case 3 : |
case 3 : /* param 2 */ |
181 |
eax = ((b & 0xff) << 0xb) + (esp4 & 0xff); |
//printk("vortex: WT SetReg(0x%x) = 0x%08x\n", WT_PARM(wt,2), (int)val); |
182 |
hwwrite(vortex->mmio, 0x208 + (eax << 4), c); |
hwwrite(vortex->mmio, WT_PARM(wt,2), val); |
183 |
return 0xc; |
return 0xc; |
184 |
break; |
break; |
185 |
case 4 : |
case 4 : /* param 3 */ |
186 |
eax = ((b & 0xff) << 0xb) + (esp4 & 0xff); |
//printk("vortex: WT SetReg(0x%x) = 0x%08x\n", WT_PARM(wt,3), (int)val); |
187 |
hwwrite(vortex->mmio, 0x20c + (eax << 4), c); |
hwwrite(vortex->mmio, WT_PARM(wt,3), val); |
188 |
return 0xc; |
return 0xc; |
189 |
break; |
break; |
190 |
case 6 : |
case 6 : /* mute */ |
191 |
edx = ((b & 0xff) << 0xd) + (esp4 & 0xff); |
//printk("vortex: WT SetReg(0x%x) = 0x%08x\n", WT_MUTE(wt), (int)val); |
192 |
hwwrite(vortex->mmio, 0x100 + (edx << 2), c); |
hwwrite(vortex->mmio, WT_MUTE(wt), val); |
193 |
return 0xc; |
return 0xc; |
194 |
break; |
break; |
195 |
case 0xb : |
case 0xb : { /* delay */ |
196 |
{ |
//printk("vortex: WT SetReg(0x%x) = 0x%08x\n", WT_DELAY(wt,0), (int)val); |
197 |
int ebx, esi; |
hwwrite(vortex->mmio, WT_DELAY(wt,3), val); |
198 |
// FIXME: Here is something wrong ... (check admaud30.asm) |
hwwrite(vortex->mmio, WT_DELAY(wt,2), val); |
199 |
edx = ((b & 0xff) << 0xb) + (esp4 & 0xff); |
hwwrite(vortex->mmio, WT_DELAY(wt,1), val); |
200 |
ebx = b + esp4; |
hwwrite(vortex->mmio, WT_DELAY(wt,0), val); |
201 |
esi = ebx << 4; |
return 0xc; |
|
|
|
|
hwwrite(vortex->mmio, 0x40c + esi, c); |
|
|
hwwrite(vortex->mmio, 0x408 + esi, c); |
|
|
hwwrite(vortex->mmio, 0x404 + esi, c); |
|
|
hwwrite(vortex->mmio, 0x400 + esi, c); |
|
|
return 0xc; |
|
202 |
} |
} |
203 |
break; |
break; |
204 |
case 5 : |
/* Global WT block parameters */ |
205 |
ecx = (b << 0xf) + 0x4; |
case 5 : /* sramp */ |
206 |
|
ecx = WT_SRAMP(wt); |
207 |
break; |
break; |
208 |
case 8 : |
case 8 : /* aramp */ |
209 |
ecx = (b << 0xf) + 0x14; |
ecx = WT_ARAMP(wt); |
210 |
break; |
break; |
211 |
case 9 : |
case 9 : /* mramp */ |
212 |
ecx = (b << 0xf) + 0xc; |
ecx = WT_MRAMP(wt); |
213 |
break; |
break; |
214 |
case 0xa : |
case 0xa : /* ctrl */ |
215 |
ecx = (b << 0xf) + 0x0; |
ecx = WT_CTRL(wt); |
216 |
break; |
break; |
217 |
case 0xc : |
case 0xc : /* ds_reg */ |
218 |
ecx = (b << 0xf) + 0x8; |
ecx = WT_DSREG(wt); |
219 |
break; |
break; |
220 |
default: |
default: |
221 |
return 0; |
return 0; |
222 |
break; |
break; |
223 |
} |
} |
224 |
eax = ecx; |
//printk("vortex: WT SetReg(0x%x) = 0x%08x\n", ecx, (int)val); |
225 |
hwwrite(vortex->mmio, eax, c); |
hwwrite(vortex->mmio, ecx, val); |
226 |
return 1; |
return 1; |
227 |
} |
} |
228 |
|
|
|
void vortex_wt_WriteReg(vortex_t *vortex, int wt, char addr, int data) { |
|
|
hwwrite(vortex->mmio, ((wt << 0xf) + wt) + addr, data); |
|
|
} |
|
|
void vortex_wt_ReadReg(vortex_t *vortex, int wt, char addr, int *data) { |
|
|
*data = hwread(vortex->mmio, ((wt << 0xf) + wt) + addr); |
|
|
} |
|
|
|
|
229 |
void vortex_wt_InitializeWTRegs(vortex_t * vortex) { |
void vortex_wt_InitializeWTRegs(vortex_t * vortex) { |
230 |
int ebx=0, var4, var8, varc, var10=0, edi; |
int ebx=0, var4, var8, varc, var10=0, edi; |
231 |
|
|
232 |
var10 &= 0xe3; |
var10 &= 0xFFFFFFE3; |
233 |
var10 |= 0x22; |
var10 |= 0x22; |
234 |
var10 &= 0xFFFFFEBF; |
var10 &= 0xFFFFFEBF; |
235 |
var10 |= 0x80; |
var10 |= 0x80; |
236 |
var10 |= 0x2; |
var10 |= 0x200; |
237 |
var10 &= 0xfffffffe; |
var10 &= 0xfffffffe; |
238 |
var10 &= 0xfffffffb; |
var10 &= 0xfffffbff; |
239 |
var10 |= 0x18; |
var10 |= 0x1800; |
240 |
|
// var10 = 0x1AA2 |
241 |
var4 = 0x10000000; |
var4 = 0x10000000; |
242 |
varc = 0x00830000; |
varc = 0x00830000; |
243 |
var8 = 0x00830000; |
var8 = 0x00830000; |
244 |
|
|
245 |
for (edi=0; edi<2; edi++) { |
/* Init Bank registers. */ |
246 |
vortex_wt_SetReg(vortex, 0xc, edi, ebx); |
for (edi=0; edi<(NR_WT/NR_WT_PB); edi++) { |
247 |
vortex_wt_SetReg(vortex, 0xa, edi, var10); |
vortex_wt_SetReg(vortex, 0xc, edi, ebx); /* ds_reg */ |
248 |
vortex_wt_SetReg(vortex, 0x9, edi, var4); |
vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */ |
249 |
vortex_wt_SetReg(vortex, 0x8, edi, varc); |
vortex_wt_SetReg(vortex, 0x9, edi, var4); /* mramp */ |
250 |
vortex_wt_SetReg(vortex, 0x5, edi, var8); |
vortex_wt_SetReg(vortex, 0x8, edi, varc); /* aramp */ |
251 |
|
vortex_wt_SetReg(vortex, 0x5, edi, var8); /* sramp */ |
252 |
} |
} |
253 |
|
/* Init Voice registers. */ |
254 |
for (edi=0; edi<NR_WT; edi++) { |
for (edi=0; edi<NR_WT; edi++) { |
255 |
vortex_wt_SetReg(vortex, 0x4, edi, ebx); |
vortex_wt_SetReg(vortex, 0x4, edi, ebx); /* param 3 0x20c */ |
256 |
vortex_wt_SetReg(vortex, 0x3, edi, ebx); |
vortex_wt_SetReg(vortex, 0x3, edi, ebx); /* param 2 0x208 */ |
257 |
vortex_wt_SetReg(vortex, 0x2, edi, ebx); |
vortex_wt_SetReg(vortex, 0x2, edi, ebx); /* param 1 0x204 */ |
258 |
vortex_wt_SetReg(vortex, 0x1, edi, ebx); |
vortex_wt_SetReg(vortex, 0x1, edi, ebx); /* param 0 0x200 */ |
259 |
vortex_wt_SetReg(vortex, 0xb, edi, ebx); |
vortex_wt_SetReg(vortex, 0xb, edi, ebx); /* delay 0x400 - 0x40c */ |
260 |
} |
} |
261 |
var10 |= 1; |
var10 |= 1; |
262 |
for (edi=0; edi<2; edi++) |
for (edi=0; edi<(NR_WT/NR_WT_PB); edi++) |
263 |
vortex_wt_SetReg(vortex, 0xa, edi, var10); |
vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */ |
264 |
} |
} |
265 |
/* Extract of CAdbTopology::SetVolume(struct _ASPVOLUME *) */ |
/* Extract of CAdbTopology::SetVolume(struct _ASPVOLUME *) */ |
266 |
void vortex_wt_SetVolume(vortex_t *vortex, int wt, int a, int vol[]) { |
|
267 |
int x=0, y=0; |
void vortex_wt_SetVolume(vortex_t *vortex, int wt, int vol[]) { |
268 |
// CAdbTopology->this_1E4, CAdbTopology->this_1E8 |
wt_voice_t *voice = &(vortex->wt_voice[wt]); |
269 |
vortex_wt_WriteReg(vortex, wt, 0x200 + (a<<4), (x & 0xff) << 0x10); |
int ecx, eax; |
270 |
vortex_wt_WriteReg(vortex, wt, 0x204 + (a<<4), ((x & 0xff) << 0x10) | 1); |
|
271 |
// In this case x semes to a set of 7 bit values. |
/* This is pure guess */ |
272 |
// y = CAdbTopology->this_1F0 |
voice->parm0 &= 0xff00ffff; |
273 |
vortex_wt_WriteReg(vortex, wt, 0x20c + (a<<4), y); |
voice->parm0 |= (vol[0] & 0xff) << 0x10; |
274 |
|
voice->parm1 &= 0xff00ffff; |
275 |
|
voice->parm1 |= (vol[1] & 0xff) << 0x10; |
276 |
|
|
277 |
|
/* This is real */ |
278 |
|
hwwrite(vortex, WT_PARM(wt,0), voice->parm0); |
279 |
|
hwwrite(vortex, WT_PARM(wt,1), voice->parm0); |
280 |
|
|
281 |
|
if (this_1D0 & 4) { |
282 |
|
ecx = eax >>= 8; |
283 |
|
if (ecx < 0x80) |
284 |
|
ecx = 0x7f; |
285 |
|
voice->parm3 &= 0xFFFFC07F; |
286 |
|
voice->parm3 |= (ecx & 0x7f) << 7; |
287 |
|
voice->parm3 &= 0xFFFFFF80; |
288 |
|
voice->parm3 |= (eax & 0x7f); |
289 |
|
} else { |
290 |
|
voice->parm3 &= 0xFFE03FFF; |
291 |
|
voice->parm3 |= (eax & 0FE00) << 5; |
292 |
|
} |
293 |
|
|
294 |
|
hwwrite(vortex, WT_PARM(wt,3), voice->parm3); |
295 |
|
} |
296 |
|
|
297 |
|
/* Extract of CAdbTopology::SetFrequency(unsigned long arg_0) */ |
298 |
|
void vortex_wt_SetFrequency(vortex_t *vortex, int wt, unsigned int sr) { |
299 |
|
wt_voice_t *voice = &(vortex->wt_voice[wt]); |
300 |
|
int eax, edx; |
301 |
|
|
302 |
|
eax = ((sr << 0xf)*0x57619F1) & 0xffffffff; |
303 |
|
edx = ((sr << 0xf)*0x57619F1)>>0x20; |
304 |
|
edx >>= 0xa; |
305 |
|
edx <<= 1; |
306 |
|
if (edx) { |
307 |
|
if (edx & 0x0FFF80000) |
308 |
|
eax = 0x7fff; |
309 |
|
else { |
310 |
|
edx <<= 0xd; |
311 |
|
eax = 7; |
312 |
|
while ((edx & 0x80000000) == 0) { |
313 |
|
edx <<= 1; |
314 |
|
eax--; |
315 |
|
if (eax == 0; |
316 |
|
break; |
317 |
|
} |
318 |
|
if (eax) |
319 |
|
edx <<= 1; |
320 |
|
eax <<= 0xc; |
321 |
|
edx >> 0x14; |
322 |
|
eax |= edx; |
323 |
|
} |
324 |
|
} else |
325 |
|
eax = 0; |
326 |
|
voice->parm0 &= 0xffff0001; |
327 |
|
voice->parm0 |= (eax & 0x7fff)<<1; |
328 |
|
voice->parm1 = voice->parm0 | 1; |
329 |
|
// Wt: this_1D4 |
330 |
|
//AuWt::WriteReg((ulong)(this_1DC<<4)+0x200, (ulong)this_1E4); |
331 |
|
//AuWt::WriteReg((ulong)(this_1DC<<4)+0x204, (ulong)this_1E8); |
332 |
|
hwwrite(vortex->mmio, WT_PARM(wt,0), voice->parm0); |
333 |
|
hwwrite(vortex->mmio, WT_PARM(wt,1), voice->parm1); |
334 |
} |
} |
335 |
|
|
336 |
/* The rest of this file is only for information purpose. */ |
/* The rest of this file is only for information purpose. */ |
337 |
|
|
338 |
#if 0 |
#if 0 |
339 |
void Asp4SynthTopology::Asp4SynthTopology(class CResource * res, class Asp4Topology * asp) { |
void Asp4SynthTopology::Asp4SynthTopology(class CResource * res, class Asp4Topology * asp) { |
340 |
this00 = res; |
this00 = res; |
427 |
#ifdef CHIP_AU8830 |
#ifdef CHIP_AU8830 |
428 |
Route(0, 0x11, 0x62, this08 + 0x50); |
Route(0, 0x11, 0x62, this08 + 0x50); |
429 |
#elifdef CHIP_AU8820 |
#elifdef CHIP_AU8820 |
430 |
Route(0, 0x11, 0x00, this08); |
Route(0, 0x11, 0x58, this08); |
431 |
#endif |
#endif |
432 |
if (this38) |
if (this38) |
433 |
DisableInput(this38, this08, 0); |
DisableInput(this38, this08, 0); |
642 |
|
|
643 |
|
|
644 |
// Voice related stuff. |
// Voice related stuff. |
645 |
void vortex_AspSynth_VoiceInit(void) { |
void vortex_Asp4Synth_VoiceInit(void) { |
646 |
int i; |
int i; |
647 |
struct voice_t *voice; |
struct voice_t *voice; |
648 |
//Asp4Synth::ResetPerformanceStats(void); |
//Asp4Synth::ResetPerformanceStats(void); |
663 |
voice->this_4c = 0; |
voice->this_4c = 0; |
664 |
voice->this_50 = 0; |
voice->this_50 = 0; |
665 |
|
|
666 |
if (voice->this_180) { |
if (voice->this_180 != 0) { |
667 |
vortex_SetReg(vortex, 1, i, 0); |
vortex_SetReg(vortex, 1, i, 0); |
668 |
vortex_SetReg(vortex, 2, i, 0); |
vortex_SetReg(vortex, 2, i, 0); |
669 |
//CSynth::Stop(void); |
//CSynth::Stop(void); |
670 |
//CSynth::Release(void); |
//CSynth::Release(void); |
671 |
voice->this_180 = 0; |
voice->this_180 = 0; |
|
vortex_SetReg(vortex, 0, i, 1); |
|
672 |
} |
} |
673 |
|
vortex_SetReg(vortex, 0, i, 1); /* running */ |
674 |
} |
} |
675 |
// Software voices ... |
// Software voices ... |
676 |
|
|
680 |
void Asp4Synth::MuteVoices(uchar a,ulong b) { |
void Asp4Synth::MuteVoices(uchar a,ulong b) { |
681 |
int ebx=0; |
int ebx=0; |
682 |
if (ebx != this_180) { |
if (ebx != this_180) { |
683 |
vortex_SetReg(vortex, 6, i, 1); |
vortex_SetReg(vortex, 6, i, 1); /* mute */ |
684 |
vortex_SetReg(vortex, 1, i, ebx); |
vortex_SetReg(vortex, 1, i, ebx); /* param 0 */ |
685 |
vortex_SetReg(vortex, 2, i, ebx); |
vortex_SetReg(vortex, 2, i, ebx); /* param 1 */ |
686 |
CSynth::Stop(void); |
CSynth::Stop(void); |
687 |
CSynth::Release(void); |
CSynth::Release(void); |
688 |
this_180 = ebx; |
this_180 = ebx; |
689 |
} |
} |
|
|
|
690 |
} |
} |
691 |
|
|
692 |
void Asp4Synth::ResetControllers(unsigned char) { |
void Asp4Synth::ResetControllers(unsigned char) { |
693 |
|
|
694 |
} |
} |
711 |
return 0C0000001; |
return 0C0000001; |
712 |
this_2c->this_53888 = 1; |
this_2c->this_53888 = 1; |
713 |
} |
} |
714 |
// Some "repe" things i dont understand. Basically semes to be initializers. |
// Some "repe" things i dont understand. Basically seems to be initializers. |
715 |
|
|
716 |
} |
} |
717 |
void Asp4MidiEvent::handler(void *) { |
void Asp4MidiEvent::handler(void *) { |
719 |
|
|
720 |
case x: |
case x: |
721 |
if (this_60) |
if (this_60) |
722 |
CWTHal::SetReg((uchar) 6, (int) this_58, (ulong) 1); |
CWTHal::SetReg((uchar) 6, (int) this_58, (ulong) 1); /* mute */ |
723 |
break; |
break; |
724 |
|
|
725 |
} |
} |
743 |
vortex_SetReg(vortex, 5, 1, 0x8800); |
vortex_SetReg(vortex, 5, 1, 0x8800); |
744 |
|
|
745 |
} |
} |
746 |
|
|
747 |
|
long CAdbTopology::SetFrequency(unsigned long arg_0) { |
748 |
|
int edx, eax; |
749 |
|
|
750 |
|
if (arg_0 > 96000) |
751 |
|
arg_0 = 96000; |
752 |
|
|
753 |
|
CDmaCore::SetSampleRate(arg_0); |
754 |
|
if (this_1E0) { |
755 |
|
eax = ((arg_0 << 0xf)*0x57619F1) & 0xffffffff; |
756 |
|
edx = ((arg_0 << 0xf)*0x57619F1)>>0x20; |
757 |
|
edx >>= 0xa; |
758 |
|
edx <<= 1; |
759 |
|
if (edx) { |
760 |
|
if (edx & 0x0FFF80000) |
761 |
|
eax = 0x7fff; |
762 |
|
else { |
763 |
|
edx <<= 0xd; |
764 |
|
eax = 7; |
765 |
|
while ((edx & 0x80000000) == 0) { |
766 |
|
edx <<= 1; |
767 |
|
eax--; |
768 |
|
if (eax == 0; |
769 |
|
break; |
770 |
|
} |
771 |
|
if (eax) |
772 |
|
edx <<= 1; |
773 |
|
eax <<= 0xc; |
774 |
|
edx >> 0x14; |
775 |
|
eax |= edx; |
776 |
|
} |
777 |
|
} else |
778 |
|
eax = 0; |
779 |
|
this_1E4 &= 0xffff0001; |
780 |
|
this_1E4 |= (eax & 0x7fff)<<1; |
781 |
|
this_1E8 = this_1E4 | 1; |
782 |
|
// Wt: this_1D4 |
783 |
|
AuWt::WriteReg((ulong)(this_1DC<<4)+0x200, (ulong)this_1E4); |
784 |
|
AuWt::WriteReg((ulong)(this_1DC<<4)+0x204, (ulong)this_1E8); |
785 |
|
return 1; |
786 |
|
} |
787 |
|
if (arg_0 > 96050) |
788 |
|
arg_0 = 96050; |
789 |
|
|
790 |
|
... |
791 |
|
|
792 |
|
CAsp4Src::ChangeRatio(ulong); |
793 |
|
CAsp4Src::ChangeRatio(ulong); |
794 |
|
|
795 |
|
... |
796 |
|
|
797 |
|
} |
798 |
#endif |
#endif |
799 |
|
|
800 |
/* |
/* |