907 |
hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2)); |
hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2)); |
908 |
} |
} |
909 |
|
|
910 |
void vortex_adbdma_bufshift(vortex_t *vortex, int adbdma) { |
int vortex_adbdma_bufshift(vortex_t *vortex, int adbdma) { |
911 |
stream_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
912 |
int page, p, pp, delta, i; |
int page, p, pp, delta, i; |
913 |
|
|
920 |
delta += dma->nr_periods; |
delta += dma->nr_periods; |
921 |
} |
} |
922 |
if (delta == 0) |
if (delta == 0) |
923 |
return; |
return 0; |
924 |
|
|
925 |
/* refresh hw page table */ |
/* refresh hw page table */ |
926 |
if (dma->nr_periods > 4) { |
if (dma->nr_periods > 4) { |
944 |
dma->period_virt -= dma->nr_periods; |
dma->period_virt -= dma->nr_periods; |
945 |
if ((delta != 1) || (delta < 0)) |
if ((delta != 1) || (delta < 0)) |
946 |
printk(KERN_INFO "vortex: % d virt=0x%d, real=0x%x, delta = %d\n", adbdma, dma->period_virt, dma->period_real, delta); |
printk(KERN_INFO "vortex: % d virt=0x%d, real=0x%x, delta = %d\n", adbdma, dma->period_virt, dma->period_real, delta); |
947 |
|
|
948 |
|
return delta; |
949 |
} |
} |
950 |
|
|
951 |
void vortex_adbdma_setctrl(vortex_t *vortex, int a, int b, int c, int d, int e, int f) { |
void vortex_adbdma_setctrl(vortex_t *vortex, int a, int b, int c, int d, int e, int f) { |
1245 |
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
1246 |
} |
} |
1247 |
|
|
1248 |
void vortex_wtdma_bufshift(vortex_t *vortex, int wtdma) { |
int vortex_wtdma_bufshift(vortex_t *vortex, int wtdma) { |
1249 |
stream_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1250 |
int page, p, delta, i; |
int page, p, pp, delta, i; |
1251 |
|
|
1252 |
page = (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >> 0xc) & 0x3; |
page = (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) & WT_SUBBUF_MASK) >> WT_SUBBUF_SHIFT; |
1253 |
delta = (page - dma->period_real) & 3; |
if (dma->nr_periods >= 4) |
1254 |
|
delta = (page - dma->period_real) & 3; |
1255 |
|
else { |
1256 |
|
delta = (page - dma->period_real); |
1257 |
|
if (delta < 0) |
1258 |
|
delta += dma->nr_periods; |
1259 |
|
} |
1260 |
|
if (delta == 0) |
1261 |
|
return 0; |
1262 |
|
|
1263 |
/* refresh hw page table */ |
/* refresh hw page table */ |
1264 |
if (dma->nr_periods > 4) { |
if (dma->nr_periods > 4) { |
1265 |
for (i=0 ; i < delta; i++) { |
for (i=0 ; i < delta; i++) { |
1266 |
p = dma->period_virt + i; |
/* p: audio buffer page index */ |
1267 |
|
p = dma->period_virt + i + 4; |
1268 |
if (p >= dma->nr_periods) |
if (p >= dma->nr_periods) |
1269 |
p -= dma->nr_periods; |
p -= dma->nr_periods; |
1270 |
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE+(((wtdma << 2)+(p & 3)) << 2), dma->buf_addr + ((dma->period_bytes)*p)); |
/* pp: hardware DMA page index. */ |
1271 |
|
pp = dma->period_real + i; |
1272 |
|
if (pp >= 4) |
1273 |
|
pp -= 4; |
1274 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE+(((wtdma << 2)+pp) << 2), dma->buf_addr+((dma->period_bytes)*p)); |
1275 |
|
/* Force write thru cache. */ |
1276 |
|
hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE + (((wtdma << 2)+pp) << 2)); |
1277 |
} |
} |
1278 |
} |
} |
1279 |
|
|
1280 |
dma->period_virt += delta; |
dma->period_virt += delta; |
1281 |
if (dma->period_virt >= dma->nr_periods) |
if (dma->period_virt >= dma->nr_periods) |
1282 |
dma->period_virt -= dma->nr_periods; |
dma->period_virt -= dma->nr_periods; |
1284 |
|
|
1285 |
if (delta != 1) |
if (delta != 1) |
1286 |
printk(KERN_WARNING "vortex: wt page = %d, delta = %d\n", dma->period_virt, delta); |
printk(KERN_WARNING "vortex: wt page = %d, delta = %d\n", dma->period_virt, delta); |
1287 |
|
|
1288 |
|
return delta; |
1289 |
} |
} |
1290 |
|
|
1291 |
void vortex_wtdma_getposition(vortex_t *vortex, int wtdma, int *subbuf, int *pos) { |
void vortex_wtdma_getposition(vortex_t *vortex, int wtdma, int *subbuf, int *pos) { |
1974 |
return IRQ_NONE; |
return IRQ_NONE; |
1975 |
|
|
1976 |
// This is the Interrrupt Enable flag we set before (consistency check). |
// This is the Interrrupt Enable flag we set before (consistency check). |
1977 |
if ((hwread(vortex->mmio, VORTEX_CTRL) & 0x0000ff00) == CTRL_IRQ_ENABLE) |
if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE)) |
1978 |
return IRQ_HANDLED; |
return IRQ_NONE; |
1979 |
|
|
1980 |
source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE); |
source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE); |
1981 |
// Reset IRQ flags. |
// Reset IRQ flags. |
2003 |
/* ALSA period acknowledge. */ |
/* ALSA period acknowledge. */ |
2004 |
for (i=0; i<NR_ADB; i++) { |
for (i=0; i<NR_ADB; i++) { |
2005 |
if (vortex->dma_adb[i].fifo_status == FIFO_START) { |
if (vortex->dma_adb[i].fifo_status == FIFO_START) { |
2006 |
vortex_adbdma_bufshift(vortex, i); |
if (vortex_adbdma_bufshift(vortex, i)); |
2007 |
snd_pcm_period_elapsed(vortex->dma_adb[i].substream); |
snd_pcm_period_elapsed(vortex->dma_adb[i].substream); |
2008 |
} |
} |
2009 |
} |
} |
2010 |
#ifndef CHIP_AU8810 |
#ifndef CHIP_AU8810 |
2011 |
for (i=0; i<NR_WT; i++) { |
for (i=0; i<NR_WT; i++) { |
2012 |
if (vortex->dma_wt[i].fifo_status == FIFO_START) { |
if (vortex->dma_wt[i].fifo_status == FIFO_START) { |
2013 |
vortex_wtdma_bufshift(vortex, i); |
if (vortex_wtdma_bufshift(vortex, i)); |
2014 |
snd_pcm_period_elapsed(vortex->dma_wt[i].substream); |
snd_pcm_period_elapsed(vortex->dma_wt[i].substream); |
2015 |
} |
} |
2016 |
} |
} |
2017 |
#endif |
#endif |