687 |
|
|
688 |
void vortex_fifo_adbinitialize(vortex_t *vortex, int fifo, int j) { |
void vortex_fifo_adbinitialize(vortex_t *vortex, int fifo, int j) { |
689 |
vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); |
vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); |
690 |
|
#ifdef CHIP_AU8820 |
691 |
hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); |
hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); |
692 |
|
#else |
693 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xc))); |
694 |
|
#endif |
695 |
} |
} |
696 |
|
|
697 |
void vortex_fifo_wtinitialize(vortex_t *vortex, int fifo, int j) { |
void vortex_fifo_wtinitialize(vortex_t *vortex, int fifo, int j) { |
698 |
vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); |
vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); |
699 |
|
#ifdef CHIP_AU8820 |
700 |
hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); |
hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); |
701 |
|
#else |
702 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xc))); |
703 |
|
#endif |
704 |
} |
} |
705 |
|
|
706 |
void vortex_fifo_setadbvalid(vortex_t *vortex, int fifo, int en) { |
void vortex_fifo_setadbvalid(vortex_t *vortex, int fifo, int en) { |
716 |
void vortex_fifo_setadbctrl(vortex_t *vortex, int fifo, int b, int priority, int empty, int valid, int f) { |
void vortex_fifo_setadbctrl(vortex_t *vortex, int fifo, int b, int priority, int empty, int valid, int f) { |
717 |
int temp, lifeboat=0; |
int temp, lifeboat=0; |
718 |
//int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */ |
//int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */ |
719 |
int this_4=0x0; |
int this_4=0x2; |
720 |
/* f seems priority related. |
/* f seems priority related. |
721 |
* CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1 |
* CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1 |
722 |
* every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority |
* every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority |
724 |
*/ |
*/ |
725 |
do { |
do { |
726 |
temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)); |
temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)); |
727 |
if (lifeboat++ > 0xff) { |
if (lifeboat++ > 0xbb8) { |
728 |
printk(KERN_ERR "Vortex: vortex_fifo_setadbctrl fail\n"); |
printk(KERN_ERR "Vortex: vortex_fifo_setadbctrl fail\n"); |
729 |
break; |
break; |
730 |
} |
} |
733 |
// AU8830 semes to take some special care about fifo content (data). |
// AU8830 semes to take some special care about fifo content (data). |
734 |
// But i'm just to lazy to translate that :) |
// But i'm just to lazy to translate that :) |
735 |
if (valid) { |
if (valid) { |
736 |
if (!(temp & FIFO_VALID)) { |
if ((temp & FIFO_VALID) == 0) { |
737 |
//this_8[fifo] = 0; |
//this_8[fifo] = 0; |
738 |
vortex_fifo_clearadbdata(vortex, fifo, this_4); |
vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); // this_4 |
739 |
#ifdef CHIP_AU8820 |
#ifdef CHIP_AU8820 |
740 |
temp = (this_4 & 0x1f) << 0xb; |
temp = (this_4 & 0x1f) << 0xb; |
741 |
#else |
#else |
773 |
/*if (this_8[fifo])*/ vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); |
/*if (this_8[fifo])*/ vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); |
774 |
} |
} |
775 |
hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp); |
hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp); |
776 |
|
hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)); |
777 |
} |
} |
778 |
|
|
779 |
void vortex_fifo_setwtctrl(vortex_t *vortex, int fifo, int b, int priority, int empty, int valid, int f) { |
void vortex_fifo_setwtctrl(vortex_t *vortex, int fifo, int b, int priority, int empty, int valid, int f) { |
804 |
// if "c" is 0, then DMA stops when reaching that buffer. |
// if "c" is 0, then DMA stops when reaching that buffer. |
805 |
|
|
806 |
int offset, shift, mask; |
int offset, shift, mask; |
807 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
808 |
int *cfg; |
int *cfg; |
809 |
|
|
810 |
if (sb_next == -1) { |
if (sb_next == -1) { |
841 |
} |
} |
842 |
|
|
843 |
void vortex_adbdma_setfirstbuffer(vortex_t *vortex, int adbdma) { |
void vortex_adbdma_setfirstbuffer(vortex_t *vortex, int adbdma) { |
844 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
845 |
|
|
846 |
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
847 |
} |
} |
848 |
|
|
849 |
void vortex_adbdma_setstartbuffer(vortex_t *vortex, int adbdma, int sb) { |
void vortex_adbdma_setstartbuffer(vortex_t *vortex, int adbdma, int sb) { |
850 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
851 |
hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), (sb << ((NR_ADB-adbdma)*2))); |
hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), (sb << ((NR_ADB-adbdma)*2))); |
852 |
dma->period_real = dma->period_virt = sb; |
dma->period_real = dma->period_virt = sb; |
853 |
} |
} |
854 |
|
|
855 |
void vortex_adbdma_setbuffers(vortex_t *vortex, int adbdma, unsigned int addr, int size, int count) { |
void vortex_adbdma_setbuffers(vortex_t *vortex, int adbdma, unsigned int addr, int size, int count) { |
856 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
857 |
|
|
858 |
dma->period_bytes = size; |
dma->period_bytes = size; |
859 |
dma->nr_periods = count; |
dma->nr_periods = count; |
893 |
} |
} |
894 |
|
|
895 |
void vortex_adbdma_setmode(vortex_t *vortex, int adbdma, int ie, int dir, int fmt, int d, unsigned long offset) { |
void vortex_adbdma_setmode(vortex_t *vortex, int adbdma, int ie, int dir, int fmt, int d, unsigned long offset) { |
896 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
897 |
|
|
898 |
dma->dma_unknown = d; |
dma->dma_unknown = d; |
899 |
dma->dma_ctrl = ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); |
dma->dma_ctrl = ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); |
900 |
/* Enable PCMOUT interrupts. */ |
/* Enable PCMOUT interrupts. */ |
904 |
dma->dma_ctrl = (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK); |
dma->dma_ctrl = (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK); |
905 |
|
|
906 |
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
907 |
|
hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2)); |
908 |
} |
} |
909 |
|
|
910 |
void vortex_adbdma_bufshift(vortex_t *vortex, int adbdma) { |
void vortex_adbdma_bufshift(vortex_t *vortex, int adbdma) { |
911 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
912 |
int page, p, pp, delta, i; |
int page, p, pp, delta, i; |
913 |
|
|
914 |
page = (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT; |
page = (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT; |
943 |
if (dma->period_virt >= dma->nr_periods) |
if (dma->period_virt >= dma->nr_periods) |
944 |
dma->period_virt -= dma->nr_periods; |
dma->period_virt -= dma->nr_periods; |
945 |
if ((delta != 1) || (delta < 0)) |
if ((delta != 1) || (delta < 0)) |
946 |
printk(KERN_INFO "vortex: % d virt=0x%d, real=0x%x, delta = %d\n", dma->dma, dma->period_virt, dma->period_real, delta); |
printk(KERN_INFO "vortex: % d virt=0x%d, real=0x%x, delta = %d\n", adbdma, dma->period_virt, dma->period_real, delta); |
947 |
} |
} |
948 |
|
|
949 |
void vortex_adbdma_setctrl(vortex_t *vortex, int a, int b, int c, int d, int e, int f) { |
void vortex_adbdma_setctrl(vortex_t *vortex, int a, int b, int c, int d, int e, int f) { |
952 |
|
|
953 |
void vortex_adbdma_getposition(vortex_t *vortex, int adbdma, int *subbuf, int *pos) { |
void vortex_adbdma_getposition(vortex_t *vortex, int adbdma, int *subbuf, int *pos) { |
954 |
int temp, edi, eax, ecx, esp10, edx; |
int temp, edi, eax, ecx, esp10, edx; |
955 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
956 |
|
|
957 |
// dma->cfg0: this_7c, dma->cfg1: this_80. |
// dma->cfg0: this_7c, dma->cfg1: this_80. |
958 |
|
|
1058 |
} |
} |
1059 |
|
|
1060 |
int inline vortex_adbdma_getlinearpos(vortex_t *vortex, int adbdma) { |
int inline vortex_adbdma_getlinearpos(vortex_t *vortex, int adbdma) { |
1061 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
1062 |
int temp; |
int temp; |
1063 |
|
|
1064 |
temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)); |
temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)); |
1065 |
//temp = (temp & POS_MASK) + (((temp & ADB_SUBBUF_MASK)>>ADB_SUBBUF_SHIFT)*(dma->cfg0&POS_MASK)); |
temp = (dma->period_virt * dma->period_bytes) + (temp & POS_MASK); |
|
//temp = (dma->period_virt + (((((temp & ADB_SUBBUF_MASK)>>ADB_SUBBUF_SHIFT) - dma->period_real) & 3)*dma->period_bytes)) + (temp & POS_MASK); |
|
|
//temp = ((dma->period_virt+(((temp & ADB_SUBBUF_MASK)>>ADB_SUBBUF_SHIFT) - dma->period_real)) * dma->period_bytes) + (temp & POS_MASK); |
|
|
temp = (dma->period_virt * dma->period_bytes) + (temp & POS_MASK); |
|
1066 |
return (temp); |
return (temp); |
1067 |
} |
} |
1068 |
|
|
1069 |
void vortex_adbdma_startfifo(vortex_t *vortex, int adbdma) { |
void vortex_adbdma_startfifo(vortex_t *vortex, int adbdma) { |
1070 |
int this_8=0/*empty*/, this_4=0/*priority*/; |
int this_8=0/*empty*/, this_4=0/*priority*/; |
1071 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
1072 |
|
|
1073 |
switch (dma->fifo_status) { |
switch (dma->fifo_status) { |
1074 |
case FIFO_START: |
case FIFO_START: |
1075 |
vortex_fifo_setadbvalid(vortex, adbdma, dma->fifo_enabled ? 0xff:0); |
vortex_fifo_setadbvalid(vortex, adbdma, dma->fifo_enabled ? 0xff:0); |
1076 |
break; |
break; |
1077 |
case FIFO_STOP: |
case FIFO_STOP: |
1078 |
|
this_8 = 1; |
1079 |
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
1080 |
vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, |
vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, |
1081 |
this_8, dma->fifo_enabled ? 0xff:0, 0); |
this_8, dma->fifo_enabled ? 0xff:0, 0); |
1089 |
} |
} |
1090 |
|
|
1091 |
void vortex_adbdma_resumefifo(vortex_t *vortex, int adbdma) { |
void vortex_adbdma_resumefifo(vortex_t *vortex, int adbdma) { |
1092 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
1093 |
|
|
1094 |
int this_8=1, this_4=0; |
int this_8=1, this_4=0; |
1095 |
switch (dma->fifo_status) { |
switch (dma->fifo_status) { |
1107 |
} |
} |
1108 |
|
|
1109 |
void vortex_adbdma_pausefifo(vortex_t *vortex, int adbdma) { |
void vortex_adbdma_pausefifo(vortex_t *vortex, int adbdma) { |
1110 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
1111 |
|
|
1112 |
int this_8=0, this_4=0; |
int this_8=0, this_4=0; |
1113 |
switch (dma->fifo_status) { |
switch (dma->fifo_status) { |
1123 |
} |
} |
1124 |
|
|
1125 |
void vortex_adbdma_stopfifo(vortex_t *vortex, int adbdma) { |
void vortex_adbdma_stopfifo(vortex_t *vortex, int adbdma) { |
1126 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *dma = &vortex->dma_adb[adbdma]; |
1127 |
|
|
1128 |
int this_4=0, this_8=0; |
int this_4=0, this_8=0; |
1129 |
if (dma->fifo_status == FIFO_START) |
if (dma->fifo_status == FIFO_START) |
1135 |
} |
} |
1136 |
|
|
1137 |
/* WTDMA */ |
/* WTDMA */ |
1138 |
|
#ifndef CHIP_AU8810 |
1139 |
void vortex_wtdma_init(vortex_t *vortex) { |
void vortex_wtdma_init(vortex_t *vortex) { |
1140 |
} |
} |
1141 |
|
|
1142 |
void vortex_wtdma_setupbuffer(vortex_t *vortex, int wtdma, int sb, u32 addr, u32 size, int sb_next, int c) { |
void vortex_wtdma_setupbuffer(vortex_t *vortex, int wtdma, int sb, u32 addr, u32 size, int sb_next, int c) { |
1143 |
int offset, shift, mask; |
int offset, shift, mask; |
1144 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1145 |
int *cfg; |
int *cfg; |
1146 |
|
|
1147 |
if (sb_next == -1) { |
if (sb_next == -1) { |
1179 |
|
|
1180 |
void vortex_wtdma_setfirstbuffer(vortex_t *vortex, int wtdma) { |
void vortex_wtdma_setfirstbuffer(vortex_t *vortex, int wtdma) { |
1181 |
//int this_7c=dma_ctrl; |
//int this_7c=dma_ctrl; |
1182 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1183 |
|
|
1184 |
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
1185 |
} |
} |
1186 |
|
|
1187 |
void vortex_wtdma_setstartbuffer(vortex_t *vortex, int wtdma, int sb) { |
void vortex_wtdma_setstartbuffer(vortex_t *vortex, int wtdma, int sb) { |
1188 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1189 |
hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), (sb << ((~wtdma)&0xf)*2)); |
hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), (sb << ((~wtdma)&0xf)*2)); |
1190 |
dma->period_real = dma->period_virt = sb; |
dma->period_real = dma->period_virt = sb; |
1191 |
} |
} |
1192 |
|
|
1193 |
void vortex_wtdma_setbuffers(vortex_t *vortex, int wtdma, unsigned int addr, int size, int count) { |
void vortex_wtdma_setbuffers(vortex_t *vortex, int wtdma, unsigned int addr, int size, int count) { |
1194 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1195 |
|
|
1196 |
/* Wt buffer. */ |
/* Wt buffer. */ |
1197 |
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4), addr); |
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4), addr); |
1230 |
} |
} |
1231 |
|
|
1232 |
void vortex_wtdma_setmode(vortex_t *vortex, int wtdma, int ie, int dir, int fmt, int d, unsigned long offset) { |
void vortex_wtdma_setmode(vortex_t *vortex, int wtdma, int ie, int dir, int fmt, int d, unsigned long offset) { |
1233 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1234 |
|
|
1235 |
dma->dma_unknown = d; |
dma->dma_unknown = d; |
1236 |
dma->dma_ctrl = ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); |
dma->dma_ctrl = ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); |
1244 |
} |
} |
1245 |
|
|
1246 |
void vortex_wtdma_bufshift(vortex_t *vortex, int wtdma) { |
void vortex_wtdma_bufshift(vortex_t *vortex, int wtdma) { |
1247 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1248 |
int page, p, delta, i; |
int page, p, delta, i; |
1249 |
|
|
1250 |
page = (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >> 0xc) & 0x3; |
page = (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >> 0xc) & 0x3; |
1280 |
} |
} |
1281 |
|
|
1282 |
int inline vortex_wtdma_getlinearpos(vortex_t *vortex, int wtdma) { |
int inline vortex_wtdma_getlinearpos(vortex_t *vortex, int wtdma) { |
1283 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1284 |
int temp; |
int temp; |
1285 |
|
|
1286 |
temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)); |
temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)); |
1290 |
} |
} |
1291 |
|
|
1292 |
void vortex_wtdma_startfifo(vortex_t *vortex, int wtdma) { |
void vortex_wtdma_startfifo(vortex_t *vortex, int wtdma) { |
1293 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1294 |
int this_8=0, this_4=0; |
int this_8=0, this_4=0; |
1295 |
|
|
1296 |
switch (dma->fifo_status) { |
switch (dma->fifo_status) { |
1298 |
vortex_fifo_setwtvalid(vortex, wtdma, dma->fifo_enabled ? 0xff:0); |
vortex_fifo_setwtvalid(vortex, wtdma, dma->fifo_enabled ? 0xff:0); |
1299 |
break; |
break; |
1300 |
case FIFO_STOP: |
case FIFO_STOP: |
1301 |
|
this_8 = 1; |
1302 |
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
1303 |
vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, |
vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, |
1304 |
this_8, dma->fifo_enabled ? 0xff:0, 0); |
this_8, dma->fifo_enabled ? 0xff:0, 0); |
1312 |
} |
} |
1313 |
|
|
1314 |
void vortex_wtdma_resumefifo(vortex_t *vortex, int wtdma) { |
void vortex_wtdma_resumefifo(vortex_t *vortex, int wtdma) { |
1315 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1316 |
|
|
1317 |
int this_8=0, this_4=0; |
int this_8=0, this_4=0; |
1318 |
switch (dma->fifo_status) { |
switch (dma->fifo_status) { |
1330 |
} |
} |
1331 |
|
|
1332 |
void vortex_wtdma_pausefifo(vortex_t *vortex, int wtdma) { |
void vortex_wtdma_pausefifo(vortex_t *vortex, int wtdma) { |
1333 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1334 |
|
|
1335 |
int this_8=0, this_4=0; |
int this_8=0, this_4=0; |
1336 |
switch (dma->fifo_status) { |
switch (dma->fifo_status) { |
1346 |
} |
} |
1347 |
|
|
1348 |
void vortex_wtdma_stopfifo(vortex_t *vortex, int wtdma) { |
void vortex_wtdma_stopfifo(vortex_t *vortex, int wtdma) { |
1349 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1350 |
|
|
1351 |
int this_4=0, this_8=0; |
int this_4=0, this_8=0; |
1352 |
if (dma->fifo_status == FIFO_START) |
if (dma->fifo_status == FIFO_START) |
1358 |
} |
} |
1359 |
|
|
1360 |
void vortex_wtdma_chain(vortex_t *vortex, int wtdma, char sb1, char sb0) { |
void vortex_wtdma_chain(vortex_t *vortex, int wtdma, char sb1, char sb0) { |
1361 |
dma_t *dma = &vortex->dma_wt[wtdma]; |
stream_t *dma = &vortex->dma_wt[wtdma]; |
1362 |
int *cfg; |
int *cfg; |
1363 |
int offset; |
int offset; |
1364 |
|
|
1393 |
hwwrite(vortex->mmio, offset + (wtdma << 3), *cfg); |
hwwrite(vortex->mmio, offset + (wtdma << 3), *cfg); |
1394 |
} |
} |
1395 |
|
|
|
/* WT */ |
|
|
|
|
|
void vortex_wt_setstereo(vortex_t *vortex, u32 wt, u32 stereo) { |
|
|
int temp; |
|
|
|
|
|
temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2)); |
|
|
temp = (temp & 0xfe) | (stereo & 1); |
|
|
hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp); |
|
|
} |
|
|
|
|
|
void vortex_wt_setdsout(vortex_t *vortex, u32 wt, int en) { |
|
|
#ifndef CHIP_AU8820 |
|
|
int temp; |
|
|
|
|
|
temp = hwread(vortex->mmio, ((wt >> 0x5)<< 0xf) + 0x8); |
|
|
if (en) |
|
|
temp |= (1 << (wt & 0x1f)); |
|
|
else |
|
|
temp &= (1 << ~(wt & 0x1f)); |
|
|
hwwrite(vortex->mmio, ((wt >> 0x5)<< 0xf) + 0x8, temp); |
|
1396 |
#endif |
#endif |
|
} |
|
|
|
|
|
void vortex_wt_writereg(vortex_t *vortex, u32 wt, u32 reg, u32 data) { |
|
|
hwwrite(vortex->mmio, (((wt >> 0x5)<< 0xf) + reg) , data); |
|
|
} |
|
|
|
|
|
u32 vortex_wt_readreg(vortex_t *vortex, u32 wt, u32 reg) { |
|
|
return hwread(vortex->mmio, (((wt >> 0x5)<< 0xf) + reg)); |
|
|
} |
|
|
|
|
1397 |
/* ADB */ |
/* ADB */ |
1398 |
|
|
1399 |
typedef int ADBRamLink; |
typedef int ADBRamLink; |
1634 |
} |
} |
1635 |
|
|
1636 |
/* CODEC connect. */ |
/* CODEC connect. */ |
1637 |
void vortex_connect_codecplay(vortex_t *vortex, int en, unsigned char mix0, unsigned char mix1) { |
void vortex_connect_codecplay(vortex_t *vortex, int en, unsigned char mixers[]) { |
1638 |
#ifdef CHIP_AU8820 |
#ifdef CHIP_AU8820 |
1639 |
vortex_connection_mix_adb(vortex, en, 0x11, mix0, ADB_CODECOUT(0)); |
vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0)); |
1640 |
vortex_connection_mix_adb(vortex, en, 0x11, mix1, ADB_CODECOUT(1)); |
vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1)); |
1641 |
#else |
#else |
1642 |
#if 1 |
#if 1 |
1643 |
//Connect EQ. |
// Connect front channels through EQ. |
1644 |
vortex_connection_mix_adb(vortex, en, 0x11, mix0, ADB_EQIN(0)); |
vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0)); |
1645 |
vortex_connection_mix_adb(vortex, en, 0x11, mix1, ADB_EQIN(1)); |
vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1)); |
1646 |
vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0)); |
vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0)); |
1647 |
vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1)); |
vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1)); |
1648 |
|
/* Check if reg 0x28 has SDAC bit set. */ |
1649 |
|
if (VORTEX_IS_QUAD(vortex)) { |
1650 |
|
/* Rear channel. Note: ADB_CODECOUT(0+2) and (1+2) is for AC97 modem */ |
1651 |
|
vortex_connection_mix_adb(vortex, en, 0x11, mixers[2], ADB_CODECOUT(0+4)); |
1652 |
|
vortex_connection_mix_adb(vortex, en, 0x11, mixers[3], ADB_CODECOUT(1+4)); |
1653 |
|
printk("SDAC detected "); |
1654 |
|
} |
1655 |
#else |
#else |
1656 |
// Use plain direct output to codec, since EQ still doesnt work. |
// Use plain direct output to codec. |
1657 |
vortex_connection_mix_adb(vortex, en, 0x11, mix0, ADB_CODECOUT(0)); |
vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0)); |
1658 |
vortex_connection_mix_adb(vortex, en, 0x11, mix1, ADB_CODECOUT(1)); |
vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1)); |
|
#endif |
|
1659 |
#endif |
#endif |
1660 |
|
#endif |
1661 |
} |
} |
1662 |
|
|
1663 |
void vortex_connect_codecrec(vortex_t *vortex, int en, unsigned char mixin0, unsigned char mixin1) { |
void vortex_connect_codecrec(vortex_t *vortex, int en, unsigned char mixin0, unsigned char mixin1) { |
1673 |
|
|
1674 |
// Higher level audio path (de)allocator. |
// Higher level audio path (de)allocator. |
1675 |
|
|
1676 |
void vortex_connect_default(vortex_t *vortex, int en) { |
/* Resource manager */ |
1677 |
// Connect codec. |
static int resnum[VORTEX_RESOURCE_LAST] = {NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D}; |
|
vortex_connect_codecplay(vortex, en, MIX_OUTL, MIX_OUTR); |
|
|
vortex_connect_codecrec(vortex, en, MIX_INL, MIX_INR); |
|
|
} |
|
1678 |
|
|
1679 |
int vortex_getadb(vortex_t *vortex) { |
/* |
1680 |
int adb = 1; /* FIXME why do we get chip'n dale bug if setting this to 0???*/ |
Checkout/Checkin resource of given type. |
1681 |
while (vortex->dma_adb[adb].nr_ch) { |
stream: resource map to be used. If NULL means that we want to allocate |
1682 |
adb++; |
the DMA resource (root of all other resources). |
1683 |
if (adb >= NR_ADB) |
out: Mean checkout if != 0. Else mean Checkin resource. |
1684 |
return -EBUSY; |
restype: Indicates type of resource to be checked in or out. |
1685 |
|
*/ |
1686 |
|
int vortex_adb_checkinout(vortex_t *vortex, int resmap[], int out, int restype) { |
1687 |
|
int i, qty = resnum[restype], resinuse=0; |
1688 |
|
|
1689 |
|
if (out) { |
1690 |
|
/* Gather used resources by all streams. */ |
1691 |
|
for (i=0; i<NR_ADB; i++) { |
1692 |
|
resinuse |= vortex->dma_adb[i].resources[restype]; |
1693 |
|
} |
1694 |
|
resinuse |= vortex->fixed_res[restype]; |
1695 |
|
/* Find and take free resource. */ |
1696 |
|
for (i=0; i<qty; i++) { |
1697 |
|
if ((resinuse & (1 << i)) == 0) { |
1698 |
|
if (resmap != NULL) |
1699 |
|
resmap[restype] |= (1 << i); |
1700 |
|
else |
1701 |
|
vortex->dma_adb[i].resources[restype] |= (1 << i); |
1702 |
|
//printk("vortex: ResManager: type %d out %d\n", restype, i); |
1703 |
|
return i; |
1704 |
|
} |
1705 |
|
} |
1706 |
|
} else { |
1707 |
|
if (resmap == NULL) |
1708 |
|
return -EINVAL; |
1709 |
|
/* Checkin first resource of type restype. */ |
1710 |
|
for (i=0; i<qty; i++) { |
1711 |
|
if (resmap[restype] & (1 << i)) { |
1712 |
|
resmap[restype] &= ~(1 << i); |
1713 |
|
//printk("vortex: ResManager: type %d in %d\n",restype, i); |
1714 |
|
return i; |
1715 |
|
} |
1716 |
|
} |
1717 |
|
if (vortex->fixed_res[restype] & (1 << i)) { |
1718 |
|
vortex->fixed_res[restype] &= ~(1 << i); |
1719 |
|
//printk("vortex: ResManager (fixed rsc): type %d in %d\n",restype, i); |
1720 |
|
return i; |
1721 |
|
} |
1722 |
} |
} |
1723 |
vortex->dma_adb[adb].nr_ch = -1; |
printk("vortex: ResManager: type %d FATAL\n", restype); |
1724 |
vortex->dma_adb[adb].dma = adb; |
return -ENOMEM; |
|
return adb; |
|
1725 |
} |
} |
1726 |
|
|
1727 |
int vortex_getwt(vortex_t *vortex) { |
/* Default Connections */ |
1728 |
int wt = 0; |
void vortex_connect_default(vortex_t *vortex, int en) { |
1729 |
while (vortex->dma_wt[wt].nr_ch) { |
// Connect codec. |
1730 |
wt++; |
// FIXME: check if checkout was succesful. |
1731 |
if (wt >= NR_WT) |
vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); |
1732 |
return -EBUSY; |
vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); |
1733 |
|
if (VORTEX_IS_QUAD(vortex)) { |
1734 |
|
vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); |
1735 |
|
vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXOUT); |
1736 |
} |
} |
1737 |
vortex->dma_wt[wt].nr_ch = -1; |
vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXIN); |
1738 |
vortex->dma_adb[wt].dma = wt; |
vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, VORTEX_RESOURCE_MIXIN); |
1739 |
return wt; |
|
1740 |
|
vortex_connect_codecplay(vortex, en, vortex->mixplayb); |
1741 |
|
vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1)); |
1742 |
|
#ifndef CHIP_AU8810 |
1743 |
|
//vortex_connect_wt(vortex, en, vortex->mixplayb); |
1744 |
|
#endif |
1745 |
|
/* Fast Play Workaround */ |
1746 |
|
#ifndef CHIP_AU8820 |
1747 |
|
vortex->fixed_res[VORTEX_RESOURCE_DMA] = 0x00000001; |
1748 |
|
#endif |
1749 |
} |
} |
1750 |
|
|
1751 |
/* |
/* |
1752 |
Allocate nr_ch pcm audio routes. If nr_ch is 0, existing routes |
Allocate nr_ch pcm audio routesif dma < 0. If dma >= 0, existing routes |
1753 |
are deallocated. |
are deallocated. |
1754 |
|
dma: DMA engine routes to be deallocated when dma >= 0. |
1755 |
|
nr_ch: Number of channels to be de/allocated. |
1756 |
|
dir: direction of stream. Uses same values as substream->stream. |
1757 |
|
Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0. |
1758 |
*/ |
*/ |
1759 |
int vortex_adb_waveroute(vortex_t *vortex, int adbdma, int nr_ch) { |
int vortex_adb_allocroute(vortex_t *vortex, int dma, int nr_ch, int dir) { |
1760 |
dma_t *dma = &vortex->dma_adb[adbdma]; |
stream_t *stream; |
1761 |
int n, en; |
int i, en; |
1762 |
|
|
1763 |
n = adbdma*2; |
if ((nr_ch == 3) || ((dir == SNDRV_PCM_STREAM_CAPTURE)&&(nr_ch > 2))) |
1764 |
if (nr_ch == 0) { |
return -EBUSY; |
1765 |
if (dma->nr_ch <= 0) |
|
1766 |
return -EBUSY; |
spin_lock(vortex->lock); |
1767 |
printk(KERN_INFO "vortex: de alloc %d\n", adbdma); |
if (dma >= 0) { |
1768 |
en = 0; |
en = 0; |
1769 |
nr_ch = dma->nr_ch; |
vortex_adb_checkinout(vortex, vortex->dma_adb[dma].resources, en, VORTEX_RESOURCE_DMA); |
|
dma->nr_ch = -1; |
|
|
vortex_fifo_setadbvalid(vortex, adbdma, 0); |
|
1770 |
} else { |
} else { |
|
if (dma->nr_ch > 0) |
|
|
return -EBUSY; |
|
|
printk(KERN_INFO "vortex: alloc %d\n", adbdma); |
|
1771 |
en = 1; |
en = 1; |
1772 |
dma->nr_ch = nr_ch; |
if ((dma = vortex_adb_checkinout(vortex, NULL, en, VORTEX_RESOURCE_DMA)) < 0) |
1773 |
vortex_fifo_adbinitialize(vortex, adbdma, FIFO_SIZE-1); |
return -EBUSY; |
1774 |
} |
} |
1775 |
if (dma->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
|
1776 |
vortex_connection_src_mixin(vortex, en, 0x11, n, n); |
stream = &vortex->dma_adb[dma]; |
1777 |
vortex_connection_mixin_mix(vortex, en, n, MIX_OUTL, 0); |
stream->dma = dma; |
1778 |
|
stream->dir = dir; |
1779 |
|
|
1780 |
|
// FIXME: check for success of checkout or checkin. |
1781 |
|
if (dir == SNDRV_PCM_STREAM_PLAYBACK) { |
1782 |
|
int src[4], mix[4], ch_top; |
1783 |
|
|
1784 |
|
for (i=0; i<nr_ch; i++) { |
1785 |
|
if ((src[i] = vortex_adb_checkinout(vortex, stream->resources, en, VORTEX_RESOURCE_SRC))<0) { |
1786 |
|
memset(stream->resources, 0, sizeof(unsigned char)*VORTEX_RESOURCE_LAST); |
1787 |
|
return -EBUSY; |
1788 |
|
} |
1789 |
|
if ((mix[i] = vortex_adb_checkinout(vortex, stream->resources, en, VORTEX_RESOURCE_MIXIN))<0) { |
1790 |
|
memset(stream->resources, 0, sizeof(unsigned char)*VORTEX_RESOURCE_LAST); |
1791 |
|
return -EBUSY; |
1792 |
|
} |
1793 |
|
} |
1794 |
|
for (i=0; i<nr_ch; i++) { |
1795 |
|
vortex_connection_adbdma_src(vortex, en, src[nr_ch-1], dma, src[i]); |
1796 |
|
vortex_connection_src_mixin(vortex, en, 0x11, src[i], mix[i]); |
1797 |
|
vortex_connection_mixin_mix(vortex, en, mix[i], MIX_PLAYB(i), 0); |
1798 |
|
} |
1799 |
|
ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2); |
1800 |
|
for (i=nr_ch; i<ch_top; i++) { |
1801 |
|
vortex_connection_mixin_mix(vortex, en, mix[i % nr_ch], MIX_PLAYB(i), 0); |
1802 |
|
} |
1803 |
} else { |
} else { |
1804 |
vortex_connection_mixin_mix(vortex, en, MIX_INL, n, 0); |
int src[2], mix[2]; |
1805 |
vortex_mix_setvolumebyte(vortex, n, MIX_DEFOGAIN); |
|
1806 |
vortex_mix_setinputvolumebyte(vortex, n, MIX_INL, MIX_DEFIGAIN); |
for (i=0; i<nr_ch; i++) { |
1807 |
vortex_connection_mix_src(vortex, en, 0x11, n, n); |
if ((mix[i] = vortex_adb_checkinout(vortex, stream->resources, en, VORTEX_RESOURCE_MIXOUT))<0) { |
1808 |
} |
memset(stream->resources, 0, sizeof(unsigned char)*VORTEX_RESOURCE_LAST); |
1809 |
if (nr_ch == 1) { |
return -EBUSY; |
1810 |
if (dma->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
} |
1811 |
vortex_connection_adbdma_src(vortex, en, n, adbdma, n); |
if ((src[i] = vortex_adb_checkinout(vortex, stream->resources, en, VORTEX_RESOURCE_SRC))<0) { |
1812 |
vortex_connection_mixin_mix(vortex, en, n, MIX_OUTR, 0); |
memset(stream->resources, 0, sizeof(unsigned char)*VORTEX_RESOURCE_LAST); |
1813 |
} else { |
return -EBUSY; |
1814 |
vortex_connection_src_adbdma(vortex, en, n, n, adbdma); |
} |
|
vortex_connection_mixin_mix(vortex, en, MIX_INR, n, 0); |
|
1815 |
} |
} |
1816 |
} |
vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0); |
1817 |
if (nr_ch == 2) { |
vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]); |
1818 |
if (dma->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
if (nr_ch == 1) { |
1819 |
vortex_connection_src_mixin(vortex, en, 0x11, n+1, n+1); |
vortex_connection_mixin_mix(vortex, en, MIX_CAPT(1), mix[0], 0); |
1820 |
vortex_connection_mixin_mix(vortex, en, n+1, MIX_OUTR, 0); |
vortex_connection_src_adbdma(vortex, en, src[nr_ch-1], src[0], dma); |
|
vortex_connection_adbdma_src_src(vortex, en, n, adbdma, n, n+1); |
|
1821 |
} else { |
} else { |
1822 |
vortex_connection_mixin_mix(vortex, en, MIX_INR, n+1, 0); |
vortex_connection_mixin_mix(vortex, en, MIX_CAPT(1), mix[1], 0); |
1823 |
vortex_mix_setvolumebyte(vortex, n+1, MIX_DEFOGAIN); |
vortex_connection_mix_src(vortex, en, 0x11, mix[1], src[1]); |
1824 |
vortex_mix_setinputvolumebyte(vortex, n+1, MIX_INR, MIX_DEFIGAIN); |
vortex_connection_src_src_adbdma(vortex, en, src[0], src[0], src[1], dma); |
|
vortex_connection_mix_src(vortex, en, 0x11, n+1, n+1); |
|
|
vortex_connection_src_src_adbdma(vortex, en, n, n, n+1, adbdma); |
|
1825 |
} |
} |
1826 |
} |
} |
1827 |
return 0; |
vortex->dma_adb[dma].nr_ch = nr_ch; |
1828 |
|
spin_unlock(vortex->lock); |
1829 |
|
|
1830 |
|
if (en) { |
1831 |
|
printk(KERN_INFO "vortex: alloc %d\n", dma); |
1832 |
|
//vortex_fifo_adbinitialize(vortex, dma, 0xff); |
1833 |
|
//udelay(2000); |
1834 |
|
} else { |
1835 |
|
printk(KERN_INFO "vortex: de alloc %d\n", dma); |
1836 |
|
//vortex_fifo_setadbvalid(vortex, dma, 0); |
1837 |
|
} |
1838 |
|
/* AC97 Codec channel setup. FIXME: this has no effect !! */ |
1839 |
|
if (nr_ch < 4) { |
1840 |
|
/* Copy stereo to rear channel (surround) */ |
1841 |
|
snd_ac97_write_cache(vortex->codec, AC97_SIGMATEL_DAC2INVERT, snd_ac97_read(vortex->codec, AC97_SIGMATEL_DAC2INVERT) | 4); |
1842 |
|
} else { |
1843 |
|
/* Allow separate front a rear channels. */ |
1844 |
|
snd_ac97_write_cache(vortex->codec, AC97_SIGMATEL_DAC2INVERT, snd_ac97_read(vortex->codec, AC97_SIGMATEL_DAC2INVERT) & ~((u32)4)); |
1845 |
|
} |
1846 |
|
|
1847 |
|
return dma; |
1848 |
} |
} |
1849 |
|
/* |
1850 |
|
Set the SampleRate of the SRC's attached to the given DMA engine. |
1851 |
|
*/ |
1852 |
void vortex_adb_setsrc(vortex_t *vortex, int adbdma, unsigned int rate, int dir) { |
void vortex_adb_setsrc(vortex_t *vortex, int adbdma, unsigned int rate, int dir) { |
1853 |
dma_t *dma = &(vortex->dma_adb[adbdma]); |
stream_t *stream = &(vortex->dma_adb[adbdma]); |
1854 |
int i, cvrt; |
int i, cvrt; |
1855 |
|
|
1856 |
/* dir=1:play ; dir=0:rec*/ |
/* dir=1:play ; dir=0:rec*/ |
1857 |
if (dir) |
if (dir) |
1858 |
cvrt = SRC_RATIO(rate); |
cvrt = SRC_RATIO(rate); |
1859 |
else |
else |
1860 |
cvrt = SRC_RATIO2(rate); |
cvrt = SRC_RATIO2(rate); |
1861 |
for (i=0; i<(dma->nr_ch); i++) { |
for (i=0; i<NR_SRC; i++) { |
1862 |
vortex_src_setupchannel(vortex, i+((dma->dma)*2),cvrt,0,0,((dma->dma)*2)+(dma->nr_ch)-1, |
if (stream->resources[VORTEX_RESOURCE_SRC] & (1<<i)) |
1863 |
|
vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 0, cvrt, dir); |
1864 |
|
} |
1865 |
|
/* |
1866 |
|
for (i=0; i<(stream->nr_ch); i++) { |
1867 |
|
vortex_src_setupchannel(vortex, i+((adbdma)*2),cvrt,0,0,((adbdma)*2)+(dma->nr_ch)-1, |
1868 |
dir, 0, cvrt, dir); |
dir, 0, cvrt, dir); |
1869 |
} |
} |
1870 |
} |
*/ |
|
// WT routing is still a mistery. |
|
|
int vortex_wt_waveroute(vortex_t *vortex, int wtdma, int nr_ch) { |
|
|
//FIXME: WT audio routing. |
|
|
if (nr_ch) { |
|
|
vortex_fifo_wtinitialize(vortex, wtdma, 1); |
|
|
vortex_wt_setstereo(vortex, wtdma, nr_ch-1); |
|
|
} else |
|
|
vortex_fifo_setwtvalid(vortex, wtdma, 0); |
|
|
return 0; |
|
1871 |
} |
} |
1872 |
|
|
1873 |
// Timer and ISR functions. |
// Timer and ISR functions. |
1937 |
snd_pcm_period_elapsed(vortex->dma_adb[i].substream); |
snd_pcm_period_elapsed(vortex->dma_adb[i].substream); |
1938 |
} |
} |
1939 |
} |
} |
1940 |
|
#ifndef CHIP_AU8810 |
1941 |
for (i=0; i<NR_WT; i++) { |
for (i=0; i<NR_WT; i++) { |
1942 |
if (vortex->dma_wt[i].fifo_status == FIFO_START) { |
if (vortex->dma_wt[i].fifo_status == FIFO_START) { |
1943 |
vortex_wtdma_bufshift(vortex, i); |
vortex_wtdma_bufshift(vortex, i); |
1944 |
snd_pcm_period_elapsed(vortex->dma_wt[i].substream); |
snd_pcm_period_elapsed(vortex->dma_wt[i].substream); |
1945 |
} |
} |
1946 |
} |
} |
1947 |
|
#endif |
1948 |
handled = 1; |
handled = 1; |
1949 |
} |
} |
1950 |
//Acknowledge the Timer interrupt |
//Acknowledge the Timer interrupt |
1971 |
|
|
1972 |
for(i =0; i<32; i++){ |
for(i =0; i<32; i++){ |
1973 |
hwwrite(vortex->mmio,(VORTEX_CODEC_CHN+(i<<2)),0); |
hwwrite(vortex->mmio,(VORTEX_CODEC_CHN+(i<<2)),0); |
1974 |
udelay(5000); |
udelay(2000); |
1975 |
} |
} |
1976 |
if (0) { |
if (0) { |
1977 |
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x8068); |
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x8068); |
1998 |
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0xe8); |
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0xe8); |
1999 |
udelay(1000); |
udelay(1000); |
2000 |
/* Enable codec channels 0 and 1. */ |
/* Enable codec channels 0 and 1. */ |
2001 |
hwwrite(vortex->mmio,VORTEX_CODEC_EN, hwread(vortex->mmio,VORTEX_CODEC_EN) | 0x300); |
hwwrite(vortex->mmio,VORTEX_CODEC_EN, hwread(vortex->mmio,VORTEX_CODEC_EN) | EN_CODEC); |
2002 |
} |
} |
2003 |
|
|
2004 |
void vortex_codec_write(ac97_t *codec, unsigned short addr, unsigned short data){ |
void vortex_codec_write(ac97_t *codec, unsigned short addr, unsigned short data){ |
2018 |
return; |
return; |
2019 |
} |
} |
2020 |
} |
} |
|
|
|
2021 |
/* write register */ |
/* write register */ |
2022 |
hwwrite(card->mmio, VORTEX_CODEC_IO, ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) | |
hwwrite(card->mmio, VORTEX_CODEC_IO, ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) | |
2023 |
((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) | VORTEX_CODEC_WRITE); |
((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) | VORTEX_CODEC_WRITE); |
2024 |
|
|
2025 |
/* this is necessary to flush the write */ |
/* this is necessary to flush the write */ |
2026 |
lifeboat = 0; |
lifeboat = 0; |
2027 |
while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) { |
while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) { |
2032 |
return; |
return; |
2033 |
} |
} |
2034 |
} |
} |
|
|
|
2035 |
read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK); |
read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK); |
2036 |
hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr); |
hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr); |
2037 |
spin_unlock_irqrestore(&card->lock, flags); |
spin_unlock_irqrestore(&card->lock, flags); |
2055 |
spin_unlock_irqrestore(&card->lock, flags); |
spin_unlock_irqrestore(&card->lock, flags); |
2056 |
return 0xffff; |
return 0xffff; |
2057 |
} |
} |
2058 |
} |
} |
|
|
|
2059 |
/* set up read address */ |
/* set up read address */ |
2060 |
read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK); |
read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK); |
2061 |
hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr); |
hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr); |
2070 |
return 0xffff; |
return 0xffff; |
2071 |
} |
} |
2072 |
} |
} |
|
|
|
2073 |
/* read codec */ |
/* read codec */ |
2074 |
x = hwread(card->mmio, VORTEX_CODEC_IO) & VORTEX_CODEC_DATMASK; |
x = hwread(card->mmio, VORTEX_CODEC_IO) & VORTEX_CODEC_DATMASK; |
2075 |
spin_unlock_irqrestore(&card->lock, flags); |
spin_unlock_irqrestore(&card->lock, flags); |
2092 |
hwread(vortex->mmio, VORTEX_IRQ_STAT); |
hwread(vortex->mmio, VORTEX_IRQ_STAT); |
2093 |
|
|
2094 |
vortex_codec_init(vortex); |
vortex_codec_init(vortex); |
2095 |
|
|
2096 |
|
#ifdef CHIP_AU8830 |
2097 |
|
hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000); |
2098 |
|
#endif |
2099 |
|
|
2100 |
/* Audio engine init. */ |
/* Audio engine init. */ |
2101 |
vortex_fifo_init(vortex); |
vortex_fifo_init(vortex); |
2102 |
hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58 |
hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58 |
2108 |
#ifndef CHIP_AU8820 |
#ifndef CHIP_AU8820 |
2109 |
vortex_eq_init(vortex); |
vortex_eq_init(vortex); |
2110 |
#endif |
#endif |
2111 |
vortex_connect_default(vortex, 1); |
#ifndef CHIP_AU8810 |
2112 |
|
vortex_InitializeWTRegs(vortex); |
2113 |
|
#endif |
2114 |
|
// Moved to au88x0.c |
2115 |
|
//vortex_connect_default(vortex, 1); |
2116 |
|
|
2117 |
vortex_settimer(vortex, 0x90); |
vortex_settimer(vortex, 0x90); |
2118 |
// Enable Interrupts. |
// Enable Interrupts. |
2149 |
hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0); |
hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0); |
2150 |
hwwrite(vortex->mmio, VORTEX_CTRL, 0); |
hwwrite(vortex->mmio, VORTEX_CTRL, 0); |
2151 |
udelay(5000); |
udelay(5000); |
2152 |
hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0); |
hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff); |
2153 |
|
|
2154 |
printk(KERN_INFO "done.\n"); |
printk(KERN_INFO "done.\n"); |
2155 |
return 0; |
return 0; |