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#define __NO_VERSION__ |
/* |
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#include "../../alsa-kernel/pci/au88x0/au88x0_core.c" |
Vortex core low level functions. |
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|
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Author: Manuel Jander (mjander@users.sourceforge.cl) |
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These functions are mainly the result of translations made |
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from the original disassembly of the au88x0 binary drivers, |
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written by Aureal before they went down. |
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Many thanks to the Jeff Muizelar, Kester Maddock, and whoever |
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contributed to the OpenVortex project. |
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The author of this file, put the few available pieces together |
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and translated the rest of the riddle (Mix, Src and connection stuff). |
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Some things are still to be discovered, and their meanings are unclear. |
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|
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Some of these functions aren't intended to be really used, rather |
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to help to understand how does the AU88X0 chips work. Keep them in, because |
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they could be used somewhere in the future. |
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|
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This code hasn't been tested or proof read thoroughly. If you wanna help, |
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take a look at the AU88X0 assembly and check if this matches. |
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Functions tested ok so far are (they show the desired effect |
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at least): |
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vortex_routes(); (1 bug fixed). |
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vortex_adb_addroute(); |
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vortex_adb_addroutes(); |
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vortex_connect_codecplay(); |
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vortex_src_flushbuffers(); |
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vortex_adbdma_setmode(); note: still some unknown arguments! |
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vortex_adbdma_startfifo(); |
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vortex_adbdma_stopfifo(); |
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vortex_fifo_setadbctrl(); note: still some unknown arguments! |
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vortex_mix_setinputvolumebyte(); |
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vortex_mix_enableinput(); |
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vortex_mixer_addWTD(); (fixed) |
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vortex_connection_adbdma_src_src(); |
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vortex_connection_adbdma_src(); |
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vortex_src_change_convratio(); |
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vortex_src_addWTD(); (fixed) |
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History: |
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|
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01-03-2003 First revision. |
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01-21-2003 Some bug fixes. |
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17-02-2003 many bugfixes after a big versioning mess. |
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18-02-2003 JAAAAAHHHUUUUUU!!!! The mixer works !! I'm just so happy ! |
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(2 hours later...) I cant believe it! Im really lucky today. |
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Now the SRC is working too! Yeah! XMMS works ! |
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20-02-2003 First steps into the ALSA world. |
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28-02-2003 As my birthday present, i discovered how the DMA buffer pages really |
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work :-). It was all wrong. |
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12-03-2003 ALSA driver starts working (2 channels). |
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16-03-2003 More srcblock_setupchannel discoveries. |
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12-04-2003 AU8830 playback support. Recording in the works. |
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17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording |
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works now, but chipn' dale effect is still there. |
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16-05-2003 SrcSetupChannel cleanup. Moved the Src setup stuff entirely |
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into au88x0_pcm.c . |
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06-06-2003 Buffer shifter bugfix. Mixer volume fix. |
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*/ |
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#include "au88x0.h" |
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#include <linux/delay.h> |
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/* MIXER (CAsp4Mix.s and CAsp4Mixer.s) */ |
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// FIXME: get rid of this. |
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int mchannels[NR_MIXIN]; |
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int rampchs[NR_MIXIN]; |
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|
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void vortex_mixer_en_sr(vortex_t *vortex, int channel) { |
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hwwrite(vortex->mmio, VORTEX_MIXER_SR, hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); |
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} |
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void vortex_mixer_dis_sr(vortex_t *vortex, int channel) { |
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hwwrite(vortex->mmio, VORTEX_MIXER_SR, |
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hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel)); |
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} |
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void vortex_mix_muteinputgain(vortex_t *vortex, unsigned char mix, unsigned char channel) { |
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hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel), 0x80); |
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hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel), 0x80); |
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} |
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int vortex_mix_getvolume(vortex_t *vortex, unsigned char mix) { |
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int a; |
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a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff; |
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//FP2LinearFrac(a); |
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return (a); |
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} |
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void vortex_mix_setvolumebyte(vortex_t *vortex, unsigned char mix, unsigned char vol) { |
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int temp; |
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hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol); |
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if (1) { /*if (this_10) */ |
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temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2)); |
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if ((temp != 0x80) || (vol == 0x80)) |
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return; |
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} |
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hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol); |
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} |
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int vortex_mix_getinputvolume(vortex_t *vortex, unsigned char mix, int channel, int *vol) { |
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int a; |
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if (!(mchannels[mix] & (1 << channel))) |
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return 0; |
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a = hwread(vortex->mmio, |
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VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2)); |
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/* |
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if (rampchs[mix] == 0) |
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a = FP2LinearFrac(a); |
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else |
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a = FP2LinearFracWT(a); |
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*/ |
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*vol = a; |
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return (0); |
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} |
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void vortex_mix_setinputvolumebyte(vortex_t *vortex, unsigned char mix, int mixin, unsigned char vol) { |
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int temp; |
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hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol); |
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if (1) { /* this_10, initialized to 1. */ |
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temp = hwread(vortex->mmio, VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2)); |
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if ((temp != 0x80) || (vol == 0x80)) |
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return; |
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} |
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hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol); |
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} |
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int vortex_mix_getenablebit(vortex_t *vortex, unsigned char mix, int mixin) { |
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int addr, temp; |
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if (mixin >= 0) |
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addr = mixin; |
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else |
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addr = mixin + 3; |
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addr = ((mix << 3) + (addr >> 2)) << 2; |
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temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr); |
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return ((temp >> (mixin & 3)) & 1); |
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} |
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void vortex_mix_setenablebit(vortex_t *vortex, unsigned char mix, int mixin, int en) { |
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int temp, addr; |
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|
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if (mixin < 0) |
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addr = (mixin + 3); |
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else |
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addr = mixin; |
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addr = ((mix << 3) + (addr >> 2)) << 2; |
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temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr); |
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if (en) |
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temp |= (1 << (mixin & 3)); |
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else |
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temp &= ~(1 << (mixin & 3)); |
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/* Mute input. Avoid crackling? */ |
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hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80); |
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/* No idea what this does. */ |
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hwwrite(vortex->mmio, VORTEX_MIX_U0 + (mixin << 2), 0x0); |
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hwwrite(vortex->mmio, VORTEX_MIX_U0 + 4 + (mixin << 2), 0x0); |
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/* Write enable bit. */ |
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hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp); |
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} |
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void vortex_mix_killinput(vortex_t *vortex, unsigned char mix, int mixin) { |
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rampchs[mix] &= ~(1 << mixin); |
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vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); |
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mchannels[mix] &= ~(1 << mixin); |
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vortex_mix_setenablebit(vortex, mix, mixin, 0); |
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} |
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void vortex_mix_enableinput(vortex_t *vortex, unsigned char mix, int mixin) { |
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vortex_mix_killinput(vortex, mix, mixin); |
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if ((mchannels[mix] & (1 << mixin)) == 0) { |
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vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); /*0x80 : mute */ |
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mchannels[mix] |= (1 << mixin); |
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} |
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vortex_mix_setenablebit(vortex, mix, mixin, 1); |
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} |
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void vortex_mix_disableinput(vortex_t *vortex, unsigned char mix, int channel, int ramp) { |
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if (ramp) { |
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rampchs[mix] |= (1 << channel); |
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// Register callback. |
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//vortex_mix_startrampvolume(vortex); |
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vortex_mix_killinput(vortex, mix, channel); |
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} else |
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vortex_mix_killinput(vortex, mix, channel); |
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} |
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int vortex_mixer_addWTD(vortex_t *vortex, unsigned char mix, unsigned char ch) { |
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int temp, lifeboat = 0, prev; |
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|
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temp = hwread(vortex->mmio, VORTEX_MIXER_SR); |
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if ((temp & (1 << ch)) == 0) { |
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hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix); |
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vortex_mixer_en_sr(vortex, ch); |
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return 1; |
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} |
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prev = VORTEX_MIXER_CHNBASE + (ch << 2); |
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temp = hwread(vortex->mmio, prev); |
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while (temp & 0x10) { |
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prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2); |
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temp = hwread(vortex->mmio, prev); |
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//printk(KERN_INFO "vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp); |
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if ((++lifeboat) > 0xf) { |
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printk(KERN_ERR "vortex_mixer_addWTD: lifeboat overflow\n"); |
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return 0; |
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} |
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} |
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hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix); |
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hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10); |
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return 1; |
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} |
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int vortex_mixer_delWTD(vortex_t *vortex, unsigned char mix, unsigned char ch) { |
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int esp14=-1, esp18, eax, ebx, edx, ebp, esi=0; |
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//int esp1f=edi(while)=src, esp10=ch; |
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eax = hwread(vortex->mmio, VORTEX_MIXER_SR); |
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if (((1 << ch) & eax) == 0) { |
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printk(KERN_ERR "mix ALARM %x\n", eax); |
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return 0; |
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} |
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ebp = VORTEX_MIXER_CHNBASE + (ch << 2); |
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esp18 = hwread(vortex->mmio, ebp); |
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if (esp18 & 0x10) { |
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ebx = (esp18 & 0xf); |
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if (mix == ebx) { |
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ebx = VORTEX_MIXER_RTBASE + (mix << 2); |
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edx = hwread(vortex->mmio, ebx); |
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//7b60 |
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hwwrite(vortex->mmio, ebp, edx); |
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hwwrite(vortex->mmio, ebx, 0); |
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} else { |
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//7ad3 |
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edx = hwread(vortex->mmio, VORTEX_MIXER_RTBASE + (ebx << 2)); |
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//printk(KERN_INFO "vortex: mixdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src); |
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while ((edx & 0xf) != mix) { |
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if ((esi) > 0xf) { |
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printk(KERN_ERR "vortex: mixdelWTD: error lifeboat overflow\n"); |
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return 0; |
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} |
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esp14 = ebx; |
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ebx = edx & 0xf; |
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ebp = ebx << 2; |
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edx = hwread(vortex->mmio, VORTEX_MIXER_RTBASE + ebp); |
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//printk(KERN_INFO "vortex: mixdelWTD: while addr=%x, val=%x\n", ebp, edx); |
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esi++; |
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} |
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//7b30 |
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ebp = ebx << 2; |
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if (edx & 0x10) { /* Delete entry in between others */ |
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ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2); |
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edx = hwread(vortex->mmio, ebx); |
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//7b60 |
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hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ebp, edx); |
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hwwrite(vortex->mmio, ebx, 0); |
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//printk(KERN_INFO "vortex mixdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx); |
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} else { /* Delete last entry */ |
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//7b83 |
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if (esp14 == -1) |
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hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), esp18 & 0xef); |
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else { |
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ebx = (0xffffffe0 & edx) | (0xf & ebx); |
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hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + (esp14 << 2), ebx); |
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//printk(KERN_INFO "vortex mixdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx); |
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} |
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hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ebp, 0); |
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return 1; |
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} |
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} |
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} else { |
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//printk(KERN_INFO "removed last mix\n"); |
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//7be0 |
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vortex_mixer_dis_sr(vortex, ch); |
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hwwrite(vortex->mmio, ebp, 0); |
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} |
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return 1; |
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} |
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|
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unsigned int vortex_mix_boost6db(unsigned char vol) { |
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return (vol + 8); /* WOW! what a complex function! */ |
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} |
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|
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void vortex_mix_rampvolume(vortex_t *vortex, int mix) { |
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int ch; |
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char a; |
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// This function is intended for ramping down only (see vortex_disableinput()). |
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for (ch = 0; ch < 0x20; ch++) { |
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if (((1 << ch) & rampchs[mix]) == 0) |
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continue; |
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a = hwread(vortex->mmio, |
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VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2)); |
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if (a > -126) { |
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a -= 2; |
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hwwrite(vortex->mmio, |
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VORTEX_MIX_INVOL_A + (((mix << 5) + ch) << 2), a); |
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hwwrite(vortex->mmio, |
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VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2), a); |
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} else |
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vortex_mix_killinput(vortex, mix, ch); |
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} |
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} |
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|
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void vortex_mixer_init(vortex_t *vortex) { |
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unsigned long addr; |
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int x; |
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|
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// FIXME: get rid of this crap. |
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memset(mchannels, 0, NR_MIXOUT*sizeof(int)); |
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memset(rampchs, 0, NR_MIXOUT*sizeof(int)); |
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|
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addr = VORTEX_MIX_U0 + 0x17c; |
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for (x = 0x5f; x >= 0; x--) { |
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hwwrite(vortex->mmio, addr, 0); |
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addr -= 4; |
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} |
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addr = VORTEX_MIX_ENIN + 0x1fc; |
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for (x = 0x7f; x >= 0; x--) { |
320 |
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hwwrite(vortex->mmio, addr, 0); |
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addr -= 4; |
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} |
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addr = VORTEX_MIX_U0 + 0x17c; |
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for (x = 0x5f; x >= 0; x--) { |
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hwwrite(vortex->mmio, addr, 0); |
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addr -= 4; |
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} |
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addr = VORTEX_MIX_INVOL_A + 0x7fc; |
329 |
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for (x = 0x1ff; x >= 0; x--) { |
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hwwrite(vortex->mmio, addr, 0x80); |
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addr -= 4; |
332 |
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} |
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addr = VORTEX_MIX_VOL_A + 0x3c; |
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for (x = 0xf; x >= 0; x--) { |
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hwwrite(vortex->mmio, addr, 0x80); |
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addr -= 4; |
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} |
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addr = VORTEX_MIX_INVOL_B + 0x7fc; |
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for (x = 0x1ff; x >= 0; x--) { |
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hwwrite(vortex->mmio, addr, 0x80); |
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addr -= 4; |
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} |
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addr = VORTEX_MIX_VOL_B + 0x3c; |
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for (x = 0xf; x >= 0; x--) { |
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hwwrite(vortex->mmio, addr, 0x80); |
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addr -= 4; |
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} |
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addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE-1)*4; |
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for (x = (MIXER_RTBASE_SIZE-1); x >= 0; x--) { |
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hwwrite(vortex->mmio, addr, 0x0); |
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addr -= 4; |
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} |
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hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0); |
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/* |
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call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____ |
356 |
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Register ISR callback for volume smooth fade out. |
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Maybe this avoids clicks when press "stop" ? |
358 |
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*/ |
359 |
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} |
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|
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/* SRC (CAsp4Src.s and CAsp4SrcBlock) */ |
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|
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void vortex_src_en_sr(vortex_t *vortex, int channel) { |
364 |
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hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel)); |
365 |
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} |
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|
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void vortex_src_dis_sr(vortex_t *vortex, int channel) { |
368 |
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hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel)); |
369 |
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} |
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|
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void vortex_src_flushbuffers(vortex_t *vortex, unsigned char src) { |
372 |
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int i; |
373 |
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|
374 |
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for (i = 0x1f; i >= 0; i--) |
375 |
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hwwrite(vortex->mmio, VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0); |
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hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0); |
377 |
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hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0); |
378 |
|
} |
379 |
|
|
380 |
|
void vortex_src_cleardrift(vortex_t *vortex, unsigned char src) { |
381 |
|
hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0); |
382 |
|
hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0); |
383 |
|
hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1); |
384 |
|
} |
385 |
|
|
386 |
|
void vortex_src_slowlock(vortex_t *vortex, unsigned char src) { |
387 |
|
int temp; |
388 |
|
|
389 |
|
hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1); |
390 |
|
hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0); |
391 |
|
temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2)); |
392 |
|
if (temp & 0x200) |
393 |
|
hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2), temp & ~0x200L); |
394 |
|
} |
395 |
|
|
396 |
|
void vortex_src_set_throttlesource(vortex_t *vortex, unsigned char src, int en) { |
397 |
|
int temp; |
398 |
|
|
399 |
|
temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE); |
400 |
|
if (en) |
401 |
|
temp |= 1 << src; |
402 |
|
else |
403 |
|
temp &= ~(1 << src); |
404 |
|
hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp); |
405 |
|
} |
406 |
|
|
407 |
|
int vortex_src_persist_convratio(vortex_t *vortex, unsigned char src, int ratio) { |
408 |
|
int temp, lifeboat = 0; |
409 |
|
|
410 |
|
do { |
411 |
|
hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio); |
412 |
|
temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2)); |
413 |
|
if ((++lifeboat) > 0x9) { |
414 |
|
printk(KERN_ERR "Vortex: Src cvr fail\n"); |
415 |
|
break; |
416 |
|
} |
417 |
|
} while (temp != ratio); |
418 |
|
return temp; |
419 |
|
} |
420 |
|
|
421 |
|
void vortex_src_change_convratio(vortex_t *vortex, unsigned char src, int ratio) { |
422 |
|
int temp, a; |
423 |
|
|
424 |
|
if ((ratio & 0x10000) && (ratio != 0x10000)) { |
425 |
|
if (ratio & 0x3fff) |
426 |
|
a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1; |
427 |
|
else |
428 |
|
a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2; |
429 |
|
} else |
430 |
|
a = 0xc; |
431 |
|
temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2)); |
432 |
|
if (((temp >> 4) & 0xf) != a) |
433 |
|
hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2), (temp & 0xf) | ((a & 0xf) << 4)); |
434 |
|
|
435 |
|
vortex_src_persist_convratio(vortex, src, ratio); |
436 |
|
} |
437 |
|
|
438 |
|
int vortex_src_checkratio(vortex_t *vortex, unsigned char src, unsigned int desired_ratio) { |
439 |
|
int hw_ratio, lifeboat = 0; |
440 |
|
|
441 |
|
hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2)); |
442 |
|
|
443 |
|
while (hw_ratio != desired_ratio) { |
444 |
|
hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio); |
445 |
|
|
446 |
|
if ((lifeboat++) > 15){ |
447 |
|
printk(KERN_ERR "Vortex: could not set src-%d from %d to %d\n", src, hw_ratio, desired_ratio); |
448 |
|
break; |
449 |
|
} |
450 |
|
} |
451 |
|
|
452 |
|
return hw_ratio; |
453 |
|
} |
454 |
|
|
455 |
|
void vortex_src_setupchannel(vortex_t *card, unsigned char src, unsigned int cvr, |
456 |
|
unsigned int b, int c, int d, int dirplay, int f, unsigned int g, int thsource) { |
457 |
|
// noplayback: d=2,4,7,0xa,0xb when using first 2 src's. |
458 |
|
// c: enables pitch sweep. |
459 |
|
// looks like g is c related. Maybe g is a sweep parameter ? |
460 |
|
// g = cvr |
461 |
|
// dirplay: 0 = recording, 1 = playback |
462 |
|
// d = src hw index. |
463 |
|
|
464 |
|
int esi, ebp=0, esp10; |
465 |
|
|
466 |
|
vortex_src_flushbuffers(card, src); |
467 |
|
|
468 |
|
if (c) { |
469 |
|
if ((g & 0x10000) && (g != 0x10000)) { |
470 |
|
g = 0; |
471 |
|
esi = 0x7; |
472 |
|
} else { |
473 |
|
if ((((short)g) < 0) && (g != 0x8000)) { |
474 |
|
g = 0; |
475 |
|
esi = 0x8; |
476 |
|
} else { |
477 |
|
g = 1; |
478 |
|
esi = 0xc; |
479 |
|
} |
480 |
|
} |
481 |
|
} else { |
482 |
|
if ((cvr & 0x10000) && (cvr != 0x10000)) { |
483 |
|
g = 0; /*ebx = 0*/ |
484 |
|
esi = 0x11 - ((cvr >> 0xe) & 7); |
485 |
|
if (cvr & 0x3fff) |
486 |
|
esi -= 1; |
487 |
|
else |
488 |
|
esi -= 2; |
489 |
|
} else { |
490 |
|
g = 1; |
491 |
|
esi = 0xc; |
492 |
|
} |
493 |
|
} |
494 |
|
vortex_src_cleardrift(card, src); |
495 |
|
vortex_src_set_throttlesource(card, src, thsource); |
496 |
|
|
497 |
|
if ((dirplay == 0)&&(c == 0)) { |
498 |
|
if (g) |
499 |
|
esp10 = 0xf; |
500 |
|
else |
501 |
|
esp10 = 0xc; |
502 |
|
ebp = 0; |
503 |
|
} else { |
504 |
|
if (g) |
505 |
|
ebp = 0xf; |
506 |
|
else |
507 |
|
ebp = 0xc; |
508 |
|
esp10 = 0; |
509 |
|
} |
510 |
|
hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2), (f << 0x9) | (c << 0x8) | ((esi&0xf)<<4) | d); |
511 |
|
/* 0xc0 esi=0xc c=f=0 d=0*/ |
512 |
|
vortex_src_persist_convratio(card, src, cvr); |
513 |
|
hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff); |
514 |
|
/* 0 b=0 */ |
515 |
|
hwwrite(card->mmio, VORTEX_SRC_U3 + (src << 2), (g << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10); |
516 |
|
/* 0x30f00 e=g=1 esp10=0 ebp=f */ |
517 |
|
//printk(KERN_INFO "vortex: SRC %d, d=0x%x, esi=0x%x, esp10=0x%x, ebp=0x%x\n", src, d, esi, esp10, ebp); |
518 |
|
} |
519 |
|
|
520 |
|
void vortex_srcblock_init(vortex_t *vortex) { |
521 |
|
unsigned long addr; |
522 |
|
int x; |
523 |
|
hwwrite(vortex->mmio, VORTEX_SRC_SOURCE+4, 0x1ff); |
524 |
|
/* |
525 |
|
for (x=0; x<0x10; x++) { |
526 |
|
vortex_src_init(&vortex_src[x], x); |
527 |
|
} |
528 |
|
*/ |
529 |
|
//addr = 0xcc3c; |
530 |
|
//addr = 0x26c3c; |
531 |
|
addr = VORTEX_SRC_RTBASE + 0x3c; |
532 |
|
for (x = 0xf; x >= 0; x--) { |
533 |
|
hwwrite(vortex->mmio, addr, 0); |
534 |
|
addr -= 4; |
535 |
|
} |
536 |
|
//addr = 0xcc94; |
537 |
|
//addr = 0x26c94; |
538 |
|
addr = VORTEX_SRC_CHNBASE + 0x54; |
539 |
|
for (x = 0x15; x >= 0; x--) { |
540 |
|
hwwrite(vortex->mmio, addr, 0); |
541 |
|
addr -= 4; |
542 |
|
} |
543 |
|
} |
544 |
|
|
545 |
|
int vortex_src_addWTD(vortex_t *vortex, unsigned char src, unsigned char ch) { |
546 |
|
int temp, lifeboat = 0, prev; |
547 |
|
// esp13 = src |
548 |
|
|
549 |
|
temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR); |
550 |
|
if ((temp & (1 << ch)) == 0) { |
551 |
|
hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src); |
552 |
|
vortex_src_en_sr(vortex, ch); |
553 |
|
return 1; |
554 |
|
} |
555 |
|
prev = VORTEX_SRC_CHNBASE + (ch << 2); /*ebp*/ |
556 |
|
temp = hwread(vortex->mmio, prev); |
557 |
|
//while (temp & NR_SRC) { |
558 |
|
while (temp & 0x10) { |
559 |
|
prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12*/ |
560 |
|
//prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/ |
561 |
|
temp = hwread(vortex->mmio, prev); |
562 |
|
//printk(KERN_INFO "vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp); |
563 |
|
if ((++lifeboat) > 0xf) { |
564 |
|
printk(KERN_ERR "vortex_src_addWTD: lifeboat overflow\n"); |
565 |
|
return 0; |
566 |
|
} |
567 |
|
} |
568 |
|
hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src); |
569 |
|
//hwwrite(vortex->mmio, prev, (temp & (NR_SRC-1)) | NR_SRC); |
570 |
|
hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10); |
571 |
|
return 1; |
572 |
|
} |
573 |
|
|
574 |
|
int vortex_src_delWTD(vortex_t *vortex, unsigned char src, unsigned char ch) { |
575 |
|
int esp14=-1, esp18, eax, ebx, edx, ebp, esi=0; |
576 |
|
//int esp1f=edi(while)=src, esp10=ch; |
577 |
|
|
578 |
|
eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR); |
579 |
|
if (((1 << ch) & eax) == 0) { |
580 |
|
printk(KERN_ERR "src alarm\n"); |
581 |
|
return 0; |
582 |
|
} |
583 |
|
ebp = VORTEX_SRC_CHNBASE + (ch << 2); |
584 |
|
esp18 = hwread(vortex->mmio, ebp); |
585 |
|
if (esp18 & 0x10) { |
586 |
|
ebx = (esp18 & 0xf); |
587 |
|
if (src == ebx) { |
588 |
|
ebx = VORTEX_SRC_RTBASE + (src << 2); |
589 |
|
edx = hwread(vortex->mmio, ebx); |
590 |
|
//7b60 |
591 |
|
hwwrite(vortex->mmio, ebp, edx); |
592 |
|
hwwrite(vortex->mmio, ebx, 0); |
593 |
|
} else { |
594 |
|
//7ad3 |
595 |
|
edx = hwread(vortex->mmio, VORTEX_SRC_RTBASE + (ebx << 2)); |
596 |
|
//printk(KERN_INFO "vortex: srcdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src); |
597 |
|
while ((edx & 0xf) != src) { |
598 |
|
if ((esi) > 0xf) { |
599 |
|
printk("vortex: srcdelWTD: error, lifeboat overflow\n"); |
600 |
|
return 0; |
601 |
|
} |
602 |
|
esp14 = ebx; |
603 |
|
ebx = edx & 0xf; |
604 |
|
ebp = ebx << 2; |
605 |
|
edx = hwread(vortex->mmio, VORTEX_SRC_RTBASE + ebp); |
606 |
|
//printk(KERN_INFO "vortex: srcdelWTD: while addr=%x, val=%x\n", ebp, edx); |
607 |
|
esi++; |
608 |
|
} |
609 |
|
//7b30 |
610 |
|
ebp = ebx << 2; |
611 |
|
if (edx & 0x10) { /* Delete entry in between others */ |
612 |
|
ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2); |
613 |
|
edx = hwread(vortex->mmio, ebx); |
614 |
|
//7b60 |
615 |
|
hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ebp, edx); |
616 |
|
hwwrite(vortex->mmio, ebx, 0); |
617 |
|
//printk(KERN_INFO "vortex srcdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx); |
618 |
|
} else { /* Delete last entry */ |
619 |
|
//7b83 |
620 |
|
if (esp14 == -1) |
621 |
|
hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), esp18 & 0xef); |
622 |
|
else { |
623 |
|
ebx = (0xffffffe0 & edx) | (0xf & ebx); |
624 |
|
hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + (esp14 << 2), ebx); |
625 |
|
//printk(KERN_INFO"vortex srcdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx); |
626 |
|
} |
627 |
|
hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ebp, 0); |
628 |
|
return 1; |
629 |
|
} |
630 |
|
} |
631 |
|
} else { |
632 |
|
//7be0 |
633 |
|
vortex_src_dis_sr(vortex, ch); |
634 |
|
hwwrite(vortex->mmio, ebp, 0); |
635 |
|
} |
636 |
|
return 1; |
637 |
|
} |
638 |
|
|
639 |
|
/*FIFO*/ |
640 |
|
|
641 |
|
void vortex_fifo_clearadbdata(vortex_t *vortex, int fifo, int x) { |
642 |
|
for (x--; x >= 0; x--) |
643 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_ADBDATA + (((fifo << FIFO_SIZE_BITS) + x) << 2), 0); |
644 |
|
} |
645 |
|
|
646 |
|
void vortex_fifo_clearwtdata(vortex_t *vortex, int fifo, int x) { |
647 |
|
if (x < 1) |
648 |
|
return; |
649 |
|
for (x--; x >= 0; x--) |
650 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_WTDATA + (((fifo << FIFO_SIZE_BITS) + x) << 2), 0); |
651 |
|
} |
652 |
|
|
653 |
|
void vortex_fifo_init(vortex_t *vortex) { |
654 |
|
int x; |
655 |
|
unsigned long addr; |
656 |
|
|
657 |
|
/* ADB DMA channels fifos. */ |
658 |
|
addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB-1)*4); |
659 |
|
for (x = NR_ADB-1; x >= 0; x--) { |
660 |
|
hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1)); |
661 |
|
if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1)) |
662 |
|
printk(KERN_ERR "bad adb fifo reset!"); |
663 |
|
vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE); |
664 |
|
addr -= 4; |
665 |
|
} |
666 |
|
|
667 |
|
#ifndef CHIP_AU8810 |
668 |
|
/* WT DMA channels fifos. */ |
669 |
|
addr = VORTEX_FIFO_WTCTRL + ((NR_WT-1)*4); |
670 |
|
for (x = NR_WT-1; x >= 0; x--) { |
671 |
|
hwwrite(vortex->mmio, addr, FIFO_U0); |
672 |
|
if (hwread(vortex->mmio, addr) != FIFO_U0) |
673 |
|
printk(KERN_ERR "bad wt fifo reset (0x%08lx, 0x%08x)!\n", addr, hwread(vortex->mmio, addr)); |
674 |
|
vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE); |
675 |
|
addr -= 4; |
676 |
|
} |
677 |
|
#endif |
678 |
|
/* below is weird stuff... */ |
679 |
|
#ifndef CHIP_AU8820 |
680 |
|
hwwrite(vortex->mmio, 0xf8c0, 0xd03); //0x0843 0xd6b |
681 |
|
#else |
682 |
|
hwwrite(vortex->mmio, 0x17000, 0x61); |
683 |
|
hwwrite(vortex->mmio, 0x17004, 0x61); |
684 |
|
hwwrite(vortex->mmio, 0x17008, 0x61); |
685 |
|
#endif |
686 |
|
} |
687 |
|
|
688 |
|
void vortex_fifo_adbinitialize(vortex_t *vortex, int fifo, int j) { |
689 |
|
vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); |
690 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); |
691 |
|
} |
692 |
|
|
693 |
|
void vortex_fifo_wtinitialize(vortex_t *vortex, int fifo, int j) { |
694 |
|
vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); |
695 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); |
696 |
|
} |
697 |
|
|
698 |
|
void vortex_fifo_setadbvalid(vortex_t *vortex, int fifo, int en) { |
699 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), (hwread(vortex->mmio, |
700 |
|
VORTEX_FIFO_ADBCTRL + (fifo << 2)) & 0xffffffef) | ((1 & en) << 4) | FIFO_U1); |
701 |
|
} |
702 |
|
|
703 |
|
void vortex_fifo_setwtvalid(vortex_t *vortex, int fifo, int en) { |
704 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), (hwread(vortex->mmio, |
705 |
|
VORTEX_FIFO_WTCTRL + (fifo << 2)) & 0xffffffef) | ((en & 1) << 4) | FIFO_U1); |
706 |
|
} |
707 |
|
|
708 |
|
void vortex_fifo_setadbctrl(vortex_t *vortex, int fifo, int b, int priority, int empty, int valid, int f) { |
709 |
|
int temp, lifeboat=0; |
710 |
|
//int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */ |
711 |
|
int this_4=0x0; |
712 |
|
/* f seems priority related. |
713 |
|
* CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1 |
714 |
|
* every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority |
715 |
|
* is never called, thus the f related bits remain a mystery for now. |
716 |
|
*/ |
717 |
|
do { |
718 |
|
temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)); |
719 |
|
if (lifeboat++ > 0xff) { |
720 |
|
printk(KERN_ERR "Vortex: vortex_fifo_setadbctrl fail\n"); |
721 |
|
break; |
722 |
|
} |
723 |
|
} while (temp & FIFO_RDONLY); |
724 |
|
|
725 |
|
// AU8830 semes to take some special care about fifo content (data). |
726 |
|
// But i'm just to lazy to translate that :) |
727 |
|
if (valid) { |
728 |
|
if (!(temp & FIFO_VALID)) { |
729 |
|
//this_8[fifo] = 0; |
730 |
|
vortex_fifo_clearadbdata(vortex, fifo, this_4); |
731 |
|
#ifdef CHIP_AU8820 |
732 |
|
temp = (this_4 & 0x1f) << 0xb; |
733 |
|
#else |
734 |
|
temp = (this_4 & 0x3f) << 0xc; |
735 |
|
#endif |
736 |
|
temp = (temp & 0xfffffffd) | ((b & 1) << 1); |
737 |
|
temp = (temp & 0xfffffff3) | ((priority & 3) << 2); |
738 |
|
temp = (temp & 0xffffffef) | ((valid & 1) << 4); |
739 |
|
temp |= FIFO_U1; |
740 |
|
temp = (temp & 0xffffffdf) | ((empty & 1) << 5); |
741 |
|
#ifdef CHIP_AU8820 |
742 |
|
temp = (temp & 0xfffbffff) | ((f & 1) << 0x12); |
743 |
|
#endif |
744 |
|
#ifdef CHIP_AU8830 |
745 |
|
temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b); |
746 |
|
temp = (temp & 0xefffffff) | ((f & 1) << 0x1c); |
747 |
|
#endif |
748 |
|
#ifdef CHIP_AU8810 |
749 |
|
temp = (temp & 0xfeffffff) | ((f & 1) << 0x18); |
750 |
|
temp = (temp & 0xfdffffff) | ((f & 1) << 0x19); |
751 |
|
#endif |
752 |
|
} |
753 |
|
} else { |
754 |
|
if (temp & FIFO_VALID) { |
755 |
|
#ifdef CHIP_AU8820 |
756 |
|
temp = ((f & 1) << 0x12) | (temp & 0xfffbffef); |
757 |
|
#endif |
758 |
|
#ifdef CHIP_AU8830 |
759 |
|
temp = ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS; |
760 |
|
#endif |
761 |
|
#ifdef CHIP_AU8810 |
762 |
|
temp = ((f & 1) << 0x1b) | (temp & 0xfcffffef) | FIFO_BITS; |
763 |
|
#endif |
764 |
|
} else |
765 |
|
/*if (this_8[fifo])*/ vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); |
766 |
|
} |
767 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp); |
768 |
|
} |
769 |
|
|
770 |
|
void vortex_fifo_setwtctrl(vortex_t *vortex, int fifo, int b, int priority, int empty, int valid, int f) { |
771 |
|
int temp=0; |
772 |
|
int this_4=2; |
773 |
|
|
774 |
|
if (valid) { |
775 |
|
vortex_fifo_clearwtdata(vortex, fifo, 0x20); |
776 |
|
temp = (this_4 & 0x1f) << 0xb; |
777 |
|
} |
778 |
|
temp = (temp & 0xfffffffd) | ((b & 1) << 1); |
779 |
|
temp = (temp & 0xfffdffff) | ((f & 1) << 0x11); |
780 |
|
temp = (temp & 0xfffffff3) | ((priority & 3) << 2); |
781 |
|
temp = (temp & 0xffffffef) | ((valid & 1) << 4); |
782 |
|
temp = (temp & 0xffffffdf) | ((empty & 1) << 5); |
783 |
|
#ifdef FIFO_BITS |
784 |
|
temp |= FIFO_BITS; |
785 |
|
#endif |
786 |
|
hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); |
787 |
|
} |
788 |
|
|
789 |
|
/* ADBDMA */ |
790 |
|
|
791 |
|
void vortex_adbdma_init(vortex_t *vortex) { |
792 |
|
} |
793 |
|
|
794 |
|
void vortex_adbdma_setupbuffer(vortex_t *vortex, int adbdma, int sb, u32 addr, u32 size, int sb_next, int c) { |
795 |
|
// if "c" is 0, then DMA stops when reaching that buffer. |
796 |
|
|
797 |
|
int offset, shift, mask; |
798 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
799 |
|
int *cfg; |
800 |
|
|
801 |
|
if (sb_next == -1) { |
802 |
|
sb_next = sb; |
803 |
|
if (dma->dma_ctrl & IE_MASK) |
804 |
|
c = 0; |
805 |
|
} |
806 |
|
|
807 |
|
if ((sb >= 0)&&(sb < 4)) { |
808 |
|
if (sb & 1) { |
809 |
|
// subbuffer 1 and 3 |
810 |
|
shift = 0x0; |
811 |
|
mask = 0xf8fff000; |
812 |
|
} else { |
813 |
|
// subbuffer 0 and 2 |
814 |
|
shift = 0xc; |
815 |
|
mask = 0x8f000fff; |
816 |
|
} |
817 |
|
if (sb & 2) { |
818 |
|
// subbuffer 2 and 3 |
819 |
|
cfg = &dma->cfg1; |
820 |
|
offset = 4; |
821 |
|
} else { |
822 |
|
// subbuffer 0 and 1 |
823 |
|
cfg = &dma->cfg0; |
824 |
|
offset = 0; |
825 |
|
} |
826 |
|
*cfg = (*cfg & (mask|0xffffff)) | ((((sb_next & 3)<<4) | ((c&1)<<6))<<24) | 0x80; |
827 |
|
if (size) |
828 |
|
*cfg = (*cfg & (mask|0xff000000)) | (((size-1) & 0xfff) << shift); |
829 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + offset + (adbdma << 3), *cfg); |
830 |
|
} |
831 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma<<2)+sb)<<2), addr); |
832 |
|
} |
833 |
|
|
834 |
|
void vortex_adbdma_setfirstbuffer(vortex_t *vortex, int adbdma) { |
835 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
836 |
|
|
837 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
838 |
|
} |
839 |
|
|
840 |
|
void vortex_adbdma_setstartbuffer(vortex_t *vortex, int adbdma, int sb) { |
841 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
842 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), (sb << ((NR_ADB-adbdma)*2))); |
843 |
|
dma->period_real = dma->period_virt = sb; |
844 |
|
} |
845 |
|
|
846 |
|
void vortex_adbdma_setbuffers(vortex_t *vortex, int adbdma, unsigned int addr, int size, int count) { |
847 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
848 |
|
|
849 |
|
dma->period_bytes = size; |
850 |
|
dma->nr_periods = count; |
851 |
|
dma->buf_addr = addr; |
852 |
|
|
853 |
|
// Adb Buffers. Simple linear buffer. |
854 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (adbdma << 4), addr); |
855 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + 0x4 + (adbdma << 4), addr + size); |
856 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + 0x8 + (adbdma << 4), addr + (size*2)); |
857 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE + 0xc + (adbdma << 4), addr + (size*3)); |
858 |
|
|
859 |
|
size--; |
860 |
|
switch (count) { |
861 |
|
case 1: |
862 |
|
dma->cfg0 = 0x80000000 | 0x40000000 | 0x00000000 | (size << 0xc); |
863 |
|
dma->cfg1 = 0x00000000 | 0x00000000 | 0x00000000; |
864 |
|
break; |
865 |
|
case 2: |
866 |
|
dma->cfg0 = 0x88000000 | 0x44000000 | 0x10000000 | (size << 0xc) | size; |
867 |
|
dma->cfg1 = 0x00000000 | 0x00000000 | 0x00000000; |
868 |
|
break; |
869 |
|
case 3: |
870 |
|
dma->cfg0 = 0x88000000 | 0x44000000 | 0x12000000 | (size << 0xc) | size; |
871 |
|
dma->cfg1 = 0x80000000 | 0x40000000 | 0x00000000 | (size << 0xc); |
872 |
|
break; |
873 |
|
case 4: |
874 |
|
default: |
875 |
|
dma->cfg0 = 0x88000000 | 0x44000000 | 0x12000000 | (size << 0xc) | size; |
876 |
|
dma->cfg1 = 0x88000000 | 0x44000000 | 0x30000000 | (size << 0xc) | size; |
877 |
|
break; |
878 |
|
} |
879 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0); |
880 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1); |
881 |
|
|
882 |
|
vortex_adbdma_setfirstbuffer(vortex, adbdma); |
883 |
|
vortex_adbdma_setstartbuffer(vortex, adbdma, 0); |
884 |
|
} |
885 |
|
|
886 |
|
void vortex_adbdma_setmode(vortex_t *vortex, int adbdma, int ie, int dir, int fmt, int d, unsigned long offset) { |
887 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
888 |
|
|
889 |
|
dma->dma_unknown = d; |
890 |
|
dma->dma_ctrl = ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); |
891 |
|
/* Enable PCMOUT interrupts. */ |
892 |
|
dma->dma_ctrl = (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK); |
893 |
|
|
894 |
|
dma->dma_ctrl = (dma->dma_ctrl & ~U_MASK) | ((dir << U_SHIFT) & U_MASK); |
895 |
|
dma->dma_ctrl = (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK); |
896 |
|
|
897 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
898 |
|
} |
899 |
|
|
900 |
|
void vortex_adbdma_bufshift(vortex_t *vortex, int adbdma) { |
901 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
902 |
|
int page, p, pp, delta, i; |
903 |
|
|
904 |
|
page = (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT; |
905 |
|
if (dma->nr_periods >= 4) |
906 |
|
delta = (page - dma->period_real) & 3; |
907 |
|
else { |
908 |
|
delta = (page - dma->period_real); |
909 |
|
if (delta < 0) |
910 |
|
delta += dma->nr_periods; |
911 |
|
} |
912 |
|
if (delta == 0) |
913 |
|
return; |
914 |
|
|
915 |
|
/* refresh hw page table */ |
916 |
|
if (dma->nr_periods > 4) { |
917 |
|
for (i=0 ; i < delta; i++) { |
918 |
|
/* p: audio buffer page index */ |
919 |
|
p = dma->period_virt + i + 4; |
920 |
|
if (p >= dma->nr_periods) |
921 |
|
p -= dma->nr_periods; |
922 |
|
/* pp: hardware DMA page index. */ |
923 |
|
pp = dma->period_real + i; |
924 |
|
if (pp >= 4) |
925 |
|
pp -= 4; |
926 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->buf_addr+((dma->period_bytes)*p)); |
927 |
|
/* Force write thru cache. */ |
928 |
|
hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2)+pp) << 2)); |
929 |
|
} |
930 |
|
} |
931 |
|
dma->period_virt += delta; |
932 |
|
dma->period_real = page; |
933 |
|
if (dma->period_virt >= dma->nr_periods) |
934 |
|
dma->period_virt -= dma->nr_periods; |
935 |
|
if ((delta != 1) || (delta < 0)) |
936 |
|
printk(KERN_INFO "vortex: % d virt=0x%d, real=0x%x, delta = %d\n", dma->dma, dma->period_virt, dma->period_real, delta); |
937 |
|
} |
938 |
|
|
939 |
|
void vortex_adbdma_setctrl(vortex_t *vortex, int a, int b, int c, int d, int e, int f) { |
940 |
|
//FIXME |
941 |
|
} |
942 |
|
|
943 |
|
void vortex_adbdma_getposition(vortex_t *vortex, int adbdma, int *subbuf, int *pos) { |
944 |
|
int temp, edi, eax, ecx, esp10, edx; |
945 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
946 |
|
|
947 |
|
// dma->cfg0: this_7c, dma->cfg1: this_80. |
948 |
|
|
949 |
|
// Looks like several hardware bug workarounds are in here. |
950 |
|
// The most weird function. What a nightmare. |
951 |
|
do { |
952 |
|
// Potential lockup, no lifeboat. |
953 |
|
temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)); |
954 |
|
if (temp == -1) { |
955 |
|
// 3ae1 |
956 |
|
//*subbuf = this_88; |
957 |
|
//*pos = this_84; |
958 |
|
return; |
959 |
|
} |
960 |
|
esp10 = adbdma; |
961 |
|
if ((esp10 == ((temp >> 0x13) & 0xf)) && ((char)((temp >> 0x10) & 0xff) < 0)) |
962 |
|
continue; |
963 |
|
edx = temp >> 0x18; |
964 |
|
if ((edx & 0xf) != adbdma) |
965 |
|
break; |
966 |
|
} while (edx | 0x10); |
967 |
|
|
968 |
|
ecx = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (adbdma << 2)); |
969 |
|
*subbuf = (ecx >> 0xc) & 3; |
970 |
|
|
971 |
|
switch (*subbuf) { |
972 |
|
case 0: |
973 |
|
edi = (dma->cfg0 >> 0xc) & 0xfff; |
974 |
|
eax = (dma->cfg0 >> 24) & 0xff; |
975 |
|
break; |
976 |
|
case 1: |
977 |
|
edi = dma->cfg0 & 0xfff; |
978 |
|
eax = (dma->cfg0 >> 24) & 0xff; |
979 |
|
break; |
980 |
|
case 2: |
981 |
|
edi = (dma->cfg1 >> 0xc) & 0xfff; |
982 |
|
eax = (dma->cfg1 >> 24) & 0xff; |
983 |
|
break; |
984 |
|
case 3: |
985 |
|
edi = dma->cfg1 & 0xfff; |
986 |
|
eax = (dma->cfg1 >> 24) & 0xff; |
987 |
|
break; |
988 |
|
default: |
989 |
|
return; |
990 |
|
} |
991 |
|
edi++; |
992 |
|
if (dma->fifo_enabled == 0) |
993 |
|
*subbuf = 0; |
994 |
|
else { |
995 |
|
esp10 = dma->dma_unknown; |
996 |
|
temp = (temp & 0xfff83fff) | ((((temp >> 0xe) & 0x1f) & ~esp10) << 0xe); |
997 |
|
if (dma->dma_ctrl & 0x2000) { |
998 |
|
if (esp10) { |
999 |
|
if ((dma->dma_ctrl & 0x3c000) == 0x20000) /* if stereo */ |
1000 |
|
eax = (0x1c - ((temp >> 0xe) & 0x1f))*2; |
1001 |
|
else |
1002 |
|
eax = 0x1c - ((temp >> 0xe) & 0x1f); |
1003 |
|
} else { |
1004 |
|
if ((dma->dma_ctrl & 0x3c000) == 0x20000) /* if stereo */ |
1005 |
|
eax = ((~(temp >> 0xe)) & 0x1f)*2; |
1006 |
|
else |
1007 |
|
eax = (~(temp >> 0xe)) & 0x1f; |
1008 |
|
} |
1009 |
|
if (((ecx & 0x10) == 0) && (dma->fifo_status != FIFO_PAUSE)) |
1010 |
|
eax = edi - eax; |
1011 |
|
else |
1012 |
|
eax = (temp & 0xfff) - eax; |
1013 |
|
if (edi > eax) |
1014 |
|
eax = edi; |
1015 |
|
} else { |
1016 |
|
// 3a87 |
1017 |
|
if ((dma->dma_ctrl & 0x3c000) == 0x20000) /* if stereo */ |
1018 |
|
eax = (temp >> 0xd) & 0x3e; |
1019 |
|
else |
1020 |
|
eax = (temp >> 0xe) & 0x1f; |
1021 |
|
} |
1022 |
|
// 3aa8 |
1023 |
|
edi--; |
1024 |
|
if ((ecx & 0x10) == 0) { |
1025 |
|
if (dma->fifo_status == FIFO_PAUSE) { |
1026 |
|
edx = (temp & 0xfff) + eax; |
1027 |
|
eax = edi + 1; |
1028 |
|
if (eax < edx) |
1029 |
|
eax = edx; |
1030 |
|
} else |
1031 |
|
eax = ((ecx >> 5) & 1) + edi; |
1032 |
|
} else { |
1033 |
|
// 3ad3 |
1034 |
|
eax += temp & 0xfff; |
1035 |
|
if (edi >= eax) |
1036 |
|
eax = edi; // 3b00 |
1037 |
|
} |
1038 |
|
} |
1039 |
|
// 3b02 |
1040 |
|
*subbuf = eax; |
1041 |
|
// 3b08 |
1042 |
|
//this_84 = *pos; |
1043 |
|
//this_88 = *subbuf; |
1044 |
|
} |
1045 |
|
|
1046 |
|
int vortex_adbdma_getcursubuffer(vortex_t *vortex, int adbdma) { |
1047 |
|
return((hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT); |
1048 |
|
} |
1049 |
|
|
1050 |
|
int inline vortex_adbdma_getlinearpos(vortex_t *vortex, int adbdma) { |
1051 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
1052 |
|
int temp; |
1053 |
|
|
1054 |
|
temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)); |
1055 |
|
//temp = (temp & POS_MASK) + (((temp & ADB_SUBBUF_MASK)>>ADB_SUBBUF_SHIFT)*(dma->cfg0&POS_MASK)); |
1056 |
|
//temp = (dma->period_virt + (((((temp & ADB_SUBBUF_MASK)>>ADB_SUBBUF_SHIFT) - dma->period_real) & 3)*dma->period_bytes)) + (temp & POS_MASK); |
1057 |
|
//temp = ((dma->period_virt+(((temp & ADB_SUBBUF_MASK)>>ADB_SUBBUF_SHIFT) - dma->period_real)) * dma->period_bytes) + (temp & POS_MASK); |
1058 |
|
temp = (dma->period_virt * dma->period_bytes) + (temp & POS_MASK); |
1059 |
|
return (temp); |
1060 |
|
} |
1061 |
|
|
1062 |
|
void vortex_adbdma_startfifo(vortex_t *vortex, int adbdma) { |
1063 |
|
int this_8=0/*empty*/, this_4=0/*priority*/; |
1064 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
1065 |
|
|
1066 |
|
switch (dma->fifo_status) { |
1067 |
|
case FIFO_START: |
1068 |
|
vortex_fifo_setadbvalid(vortex, adbdma, dma->fifo_enabled ? 0xff:0); |
1069 |
|
break; |
1070 |
|
case FIFO_STOP: |
1071 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
1072 |
|
vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, |
1073 |
|
this_8, dma->fifo_enabled ? 0xff:0, 0); |
1074 |
|
break; |
1075 |
|
case FIFO_PAUSE: |
1076 |
|
vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, |
1077 |
|
this_8, dma->fifo_enabled ? 0xff:0, 0); |
1078 |
|
break; |
1079 |
|
} |
1080 |
|
dma->fifo_status = FIFO_START; |
1081 |
|
} |
1082 |
|
|
1083 |
|
void vortex_adbdma_resumefifo(vortex_t *vortex, int adbdma) { |
1084 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
1085 |
|
|
1086 |
|
int this_8=1, this_4=0; |
1087 |
|
switch (dma->fifo_status) { |
1088 |
|
case FIFO_STOP: |
1089 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
1090 |
|
vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, |
1091 |
|
dma->fifo_enabled ? 0xff:0, 0); |
1092 |
|
break; |
1093 |
|
case FIFO_PAUSE: |
1094 |
|
vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, |
1095 |
|
dma->fifo_enabled ? 0xff:0, 0); |
1096 |
|
break; |
1097 |
|
} |
1098 |
|
dma->fifo_status = FIFO_START; |
1099 |
|
} |
1100 |
|
|
1101 |
|
void vortex_adbdma_pausefifo(vortex_t *vortex, int adbdma) { |
1102 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
1103 |
|
|
1104 |
|
int this_8=0, this_4=0; |
1105 |
|
switch (dma->fifo_status) { |
1106 |
|
case FIFO_START: |
1107 |
|
vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, 0, 0); |
1108 |
|
break; |
1109 |
|
case FIFO_STOP: |
1110 |
|
hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), dma->dma_ctrl); |
1111 |
|
vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, 0, 0); |
1112 |
|
break; |
1113 |
|
} |
1114 |
|
dma->fifo_status = FIFO_PAUSE; |
1115 |
|
} |
1116 |
|
|
1117 |
|
void vortex_adbdma_stopfifo(vortex_t *vortex, int adbdma) { |
1118 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
1119 |
|
|
1120 |
|
int this_4=0, this_8=0; |
1121 |
|
if (dma->fifo_status == FIFO_START) |
1122 |
|
vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, this_4, this_8, 0, 0); |
1123 |
|
else if (dma->fifo_status == FIFO_STOP) |
1124 |
|
return; |
1125 |
|
dma->fifo_status = FIFO_STOP; |
1126 |
|
dma->fifo_enabled = 0; |
1127 |
|
} |
1128 |
|
|
1129 |
|
/* WTDMA */ |
1130 |
|
|
1131 |
|
void vortex_wtdma_init(vortex_t *vortex) { |
1132 |
|
} |
1133 |
|
|
1134 |
|
void vortex_wtdma_setupbuffer(vortex_t *vortex, int wtdma, int sb, u32 addr, u32 size, int sb_next, int c) { |
1135 |
|
int offset, shift, mask; |
1136 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1137 |
|
int *cfg; |
1138 |
|
|
1139 |
|
if (sb_next == -1) { |
1140 |
|
sb_next = sb; |
1141 |
|
if (dma->dma_ctrl & IE_MASK) |
1142 |
|
c = 0; |
1143 |
|
} |
1144 |
|
|
1145 |
|
if ((sb >= 0)&&(sb < 4)) { |
1146 |
|
if (sb & 1) { |
1147 |
|
/* subbuffer 1 and 3 */ |
1148 |
|
shift = 0x0; |
1149 |
|
mask = 0xf8fff000; |
1150 |
|
} else { |
1151 |
|
/* subbuffer 0 and 2 */ |
1152 |
|
shift = 0xc; |
1153 |
|
mask = 0x8f000fff; |
1154 |
|
} |
1155 |
|
if (sb & 2) { |
1156 |
|
/* subbuffer 2 and 3 */ |
1157 |
|
cfg = &dma->cfg1; |
1158 |
|
offset = 4; |
1159 |
|
} else { |
1160 |
|
/* subbuffer 0 and 1 */ |
1161 |
|
cfg = &dma->cfg0; |
1162 |
|
offset = 0; |
1163 |
|
} |
1164 |
|
*cfg = (*cfg & (mask|0xffffff)) | ((((sb_next & 3)<<4) | ((c&1)<<6))<<24) | 0x80; |
1165 |
|
if (size) |
1166 |
|
*cfg = (*cfg & (mask|0xff000000)) | (((size-1) & 0xfff) << shift); |
1167 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + offset + (wtdma << 3), *cfg); |
1168 |
|
} |
1169 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (((wtdma<<2)+sb)<<2), addr); |
1170 |
|
} |
1171 |
|
|
1172 |
|
void vortex_wtdma_setfirstbuffer(vortex_t *vortex, int wtdma) { |
1173 |
|
//int this_7c=dma_ctrl; |
1174 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1175 |
|
|
1176 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
1177 |
|
} |
1178 |
|
|
1179 |
|
void vortex_wtdma_setstartbuffer(vortex_t *vortex, int wtdma, int sb) { |
1180 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1181 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), (sb << ((~wtdma)&0xf)*2)); |
1182 |
|
dma->period_real = dma->period_virt = sb; |
1183 |
|
} |
1184 |
|
|
1185 |
|
void vortex_wtdma_setbuffers(vortex_t *vortex, int wtdma, unsigned int addr, int size, int count) { |
1186 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1187 |
|
|
1188 |
|
/* Wt buffer. */ |
1189 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4), addr); |
1190 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + 0x4 + (wtdma << 4), addr + size); |
1191 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + 0x8 + (wtdma << 4), addr + (size*2)); |
1192 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + 0xc + (wtdma << 4), addr + (size*3)); |
1193 |
|
|
1194 |
|
switch (count) { |
1195 |
|
case 1: |
1196 |
|
dma->cfg0 = 0xce000000; |
1197 |
|
dma->cfg1 = 0xfc000000; |
1198 |
|
break; |
1199 |
|
case 2: |
1200 |
|
dma->cfg0 = 0xdc000000; |
1201 |
|
dma->cfg1 = 0xfc000000; |
1202 |
|
break; |
1203 |
|
case 3: |
1204 |
|
dma->cfg0 = 0xde000000; |
1205 |
|
dma->cfg1 = 0xcc000000; |
1206 |
|
break; |
1207 |
|
case 4: |
1208 |
|
default: |
1209 |
|
dma->cfg0 = 0xde000000; |
1210 |
|
dma->cfg1 = 0xfc000000; |
1211 |
|
break; |
1212 |
|
} |
1213 |
|
size--; |
1214 |
|
dma->cfg0 |= (size << 0xc) | size; |
1215 |
|
dma->cfg1 |= (size << 0xc) | size; |
1216 |
|
//printk(KERN_INFO "vortex: wt buffer cfg: 0x%8x 0x%8x\n", dma->cfg0, dma->cfg1); |
1217 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0); |
1218 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1); |
1219 |
|
|
1220 |
|
vortex_wtdma_setfirstbuffer(vortex, wtdma); |
1221 |
|
vortex_wtdma_setstartbuffer(vortex, wtdma, 0); |
1222 |
|
} |
1223 |
|
|
1224 |
|
void vortex_wtdma_setmode(vortex_t *vortex, int wtdma, int ie, int dir, int fmt, int d, unsigned long offset) { |
1225 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1226 |
|
|
1227 |
|
dma->dma_unknown = d; |
1228 |
|
dma->dma_ctrl = ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); |
1229 |
|
/* PCMOUT interrupt */ |
1230 |
|
dma->dma_ctrl = (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK); |
1231 |
|
|
1232 |
|
dma->dma_ctrl = (dma->dma_ctrl & U_MASK) | ((dir << U_SHIFT) & U_MASK); |
1233 |
|
dma->dma_ctrl = (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK); |
1234 |
|
|
1235 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
1236 |
|
} |
1237 |
|
|
1238 |
|
void vortex_wtdma_bufshift(vortex_t *vortex, int wtdma) { |
1239 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1240 |
|
int page, p, delta, i; |
1241 |
|
|
1242 |
|
page = (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >> 0xc) & 0x3; |
1243 |
|
delta = (page - dma->period_real) & 3; |
1244 |
|
|
1245 |
|
/* refresh hw page table */ |
1246 |
|
if (dma->nr_periods > 4) { |
1247 |
|
for (i=0 ; i < delta; i++) { |
1248 |
|
p = dma->period_virt + i; |
1249 |
|
if (p >= dma->nr_periods) |
1250 |
|
p -= dma->nr_periods; |
1251 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE+(((wtdma << 2)+(p & 3)) << 2), dma->buf_addr + ((dma->period_bytes)*p)); |
1252 |
|
} |
1253 |
|
} |
1254 |
|
dma->period_virt += delta; |
1255 |
|
if (dma->period_virt >= dma->nr_periods) |
1256 |
|
dma->period_virt -= dma->nr_periods; |
1257 |
|
dma->period_real = page; |
1258 |
|
|
1259 |
|
if (delta != 1) |
1260 |
|
printk(KERN_WARNING "vortex: wt page = %d, delta = %d\n", dma->period_virt, delta); |
1261 |
|
} |
1262 |
|
|
1263 |
|
void vortex_wtdma_getposition(vortex_t *vortex, int wtdma, int *subbuf, int *pos) { |
1264 |
|
int temp; |
1265 |
|
temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)); |
1266 |
|
*subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK; |
1267 |
|
*pos = temp & POS_MASK; |
1268 |
|
} |
1269 |
|
|
1270 |
|
int vortex_wtdma_getcursubuffer(vortex_t *vortex, int wtdma) { |
1271 |
|
return((hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (wtdma << 2)) >> POS_SHIFT) & POS_MASK); |
1272 |
|
} |
1273 |
|
|
1274 |
|
int inline vortex_wtdma_getlinearpos(vortex_t *vortex, int wtdma) { |
1275 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1276 |
|
int temp; |
1277 |
|
|
1278 |
|
temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)); |
1279 |
|
//temp = (temp & POS_MASK) + (((temp>>WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK)*(dma->cfg0&POS_MASK)); |
1280 |
|
temp = (temp & POS_MASK) + ((dma->period_virt)*(dma->period_bytes)); |
1281 |
|
return temp; |
1282 |
|
} |
1283 |
|
|
1284 |
|
void vortex_wtdma_startfifo(vortex_t *vortex, int wtdma) { |
1285 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1286 |
|
int this_8=0, this_4=0; |
1287 |
|
|
1288 |
|
switch (dma->fifo_status) { |
1289 |
|
case FIFO_START: |
1290 |
|
vortex_fifo_setwtvalid(vortex, wtdma, dma->fifo_enabled ? 0xff:0); |
1291 |
|
break; |
1292 |
|
case FIFO_STOP: |
1293 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
1294 |
|
vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, |
1295 |
|
this_8, dma->fifo_enabled ? 0xff:0, 0); |
1296 |
|
break; |
1297 |
|
case FIFO_PAUSE: |
1298 |
|
vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, |
1299 |
|
this_8, dma->fifo_enabled ? 0xff:0, 0); |
1300 |
|
break; |
1301 |
|
} |
1302 |
|
dma->fifo_status = FIFO_START; |
1303 |
|
} |
1304 |
|
|
1305 |
|
void vortex_wtdma_resumefifo(vortex_t *vortex, int wtdma) { |
1306 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1307 |
|
|
1308 |
|
int this_8=0, this_4=0; |
1309 |
|
switch (dma->fifo_status) { |
1310 |
|
case FIFO_STOP: |
1311 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
1312 |
|
vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, |
1313 |
|
dma->fifo_enabled ? 0xff:0, 0); |
1314 |
|
break; |
1315 |
|
case FIFO_PAUSE: |
1316 |
|
vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, |
1317 |
|
dma->fifo_enabled ? 0xff:0, 0); |
1318 |
|
break; |
1319 |
|
} |
1320 |
|
dma->fifo_status = FIFO_START; |
1321 |
|
} |
1322 |
|
|
1323 |
|
void vortex_wtdma_pausefifo(vortex_t *vortex, int wtdma) { |
1324 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1325 |
|
|
1326 |
|
int this_8=0, this_4=0; |
1327 |
|
switch (dma->fifo_status) { |
1328 |
|
case FIFO_START: |
1329 |
|
vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, 0, 0); |
1330 |
|
break; |
1331 |
|
case FIFO_STOP: |
1332 |
|
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); |
1333 |
|
vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, 0, 0); |
1334 |
|
break; |
1335 |
|
} |
1336 |
|
dma->fifo_status = FIFO_PAUSE; |
1337 |
|
} |
1338 |
|
|
1339 |
|
void vortex_wtdma_stopfifo(vortex_t *vortex, int wtdma) { |
1340 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1341 |
|
|
1342 |
|
int this_4=0, this_8=0; |
1343 |
|
if (dma->fifo_status == FIFO_START) |
1344 |
|
vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, this_4, this_8, 0, 0); |
1345 |
|
else if (dma->fifo_status == FIFO_STOP) |
1346 |
|
return; |
1347 |
|
dma->fifo_status = FIFO_STOP; |
1348 |
|
dma->fifo_enabled = 0; |
1349 |
|
} |
1350 |
|
|
1351 |
|
void vortex_wtdma_chain(vortex_t *vortex, int wtdma, char sb1, char sb0) { |
1352 |
|
dma_t *dma = &vortex->dma_wt[wtdma]; |
1353 |
|
int *cfg; |
1354 |
|
int offset; |
1355 |
|
|
1356 |
|
if (sb0 == -1) |
1357 |
|
sb1 = sb0; |
1358 |
|
// this_0x80: cfg0, this_0x84: cfg1. |
1359 |
|
|
1360 |
|
switch (sb0) { |
1361 |
|
case 0: |
1362 |
|
dma->cfg0 = (dma->cfg0 & 0xcfffffff) | ((((sb1 & 0x3) | 4) <<4 ) << 24); |
1363 |
|
cfg = &dma->cfg0; |
1364 |
|
offset = VORTEX_WTDMA_BUFCFG0; |
1365 |
|
break; |
1366 |
|
case 1: |
1367 |
|
dma->cfg0 = (dma->cfg0 & 0xfcffffff) | (((sb1 & 0x3) | 0x4) << 24); |
1368 |
|
cfg = &dma->cfg0; |
1369 |
|
offset = VORTEX_WTDMA_BUFCFG0; |
1370 |
|
break; |
1371 |
|
case 2: |
1372 |
|
dma->cfg1 = (dma->cfg1 & 0xfcffffff) | ((((sb1 & 0x3) | 4) << 4) << 24); |
1373 |
|
cfg = &dma->cfg1; |
1374 |
|
offset = VORTEX_WTDMA_BUFCFG1; |
1375 |
|
break; |
1376 |
|
case 3: |
1377 |
|
dma->cfg1 = (dma->cfg1 & 0xfcffffff) | (((sb1 & 0x3) | 0x4) << 24); |
1378 |
|
cfg = &dma->cfg1; |
1379 |
|
offset = VORTEX_WTDMA_BUFCFG1; |
1380 |
|
break; |
1381 |
|
default: |
1382 |
|
return; |
1383 |
|
} |
1384 |
|
hwwrite(vortex->mmio, offset + (wtdma << 3), *cfg); |
1385 |
|
} |
1386 |
|
|
1387 |
|
/* WT */ |
1388 |
|
|
1389 |
|
void vortex_wt_setstereo(vortex_t *vortex, u32 wt, u32 stereo) { |
1390 |
|
int temp; |
1391 |
|
|
1392 |
|
temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2)); |
1393 |
|
temp = (temp & 0xfe) | (stereo & 1); |
1394 |
|
hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp); |
1395 |
|
} |
1396 |
|
|
1397 |
|
void vortex_wt_setdsout(vortex_t *vortex, u32 wt, int en) { |
1398 |
|
#ifndef CHIP_AU8820 |
1399 |
|
int temp; |
1400 |
|
|
1401 |
|
temp = hwread(vortex->mmio, ((wt >> 0x5)<< 0xf) + 0x8); |
1402 |
|
if (en) |
1403 |
|
temp |= (1 << (wt & 0x1f)); |
1404 |
|
else |
1405 |
|
temp &= (1 << ~(wt & 0x1f)); |
1406 |
|
hwwrite(vortex->mmio, ((wt >> 0x5)<< 0xf) + 0x8, temp); |
1407 |
|
#endif |
1408 |
|
} |
1409 |
|
|
1410 |
|
void vortex_wt_writereg(vortex_t *vortex, u32 wt, u32 reg, u32 data) { |
1411 |
|
hwwrite(vortex->mmio, (((wt >> 0x5)<< 0xf) + reg) , data); |
1412 |
|
} |
1413 |
|
|
1414 |
|
u32 vortex_wt_readreg(vortex_t *vortex, u32 wt, u32 reg) { |
1415 |
|
return hwread(vortex->mmio, (((wt >> 0x5)<< 0xf) + reg)); |
1416 |
|
} |
1417 |
|
|
1418 |
|
/* ADB */ |
1419 |
|
|
1420 |
|
typedef int ADBRamLink; |
1421 |
|
void vortex_adb_init(vortex_t *vortex) { |
1422 |
|
int i; |
1423 |
|
/* it looks like we are writing more than we need to... |
1424 |
|
* if we write what we are supposed to it breaks things... */ |
1425 |
|
hwwrite(vortex->mmio, VORTEX_ADB_SR, 0); |
1426 |
|
for(i=0; i<VORTEX_ADB_RTBASE_SIZE; i++) |
1427 |
|
hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i<<2), |
1428 |
|
hwread(vortex->mmio, VORTEX_ADB_RTBASE + (i<<2)) | ROUTE_MASK); |
1429 |
|
for(i=0; i<VORTEX_ADB_CHNBASE_SIZE; i++){ |
1430 |
|
hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i<<2), |
1431 |
|
hwread(vortex->mmio, VORTEX_ADB_CHNBASE + (i<<2)) | ROUTE_MASK); |
1432 |
|
} |
1433 |
|
} |
1434 |
|
|
1435 |
|
void vortex_adb_en_sr(vortex_t *vortex, int channel) { |
1436 |
|
hwwrite(vortex->mmio, VORTEX_ADB_SR, |
1437 |
|
hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel)); |
1438 |
|
} |
1439 |
|
|
1440 |
|
void vortex_adb_dis_sr(vortex_t *vortex, int channel) { |
1441 |
|
hwwrite(vortex->mmio, VORTEX_ADB_SR, |
1442 |
|
hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel)); |
1443 |
|
} |
1444 |
|
|
1445 |
|
void vortex_adb_addroutes(vortex_t *vortex, unsigned char channel, ADBRamLink *route, int rnum) { |
1446 |
|
int temp, prev, lifeboat = 0; |
1447 |
|
|
1448 |
|
if ((rnum <= 0)||(route == NULL)) |
1449 |
|
return; |
1450 |
|
/* Write last routes. */ |
1451 |
|
rnum--; |
1452 |
|
hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2), ROUTE_MASK); |
1453 |
|
while (rnum > 0) { |
1454 |
|
hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + ((route[rnum-1] & ADB_MASK) << 2), route[rnum]); |
1455 |
|
rnum--; |
1456 |
|
} |
1457 |
|
/* Write first route. */ |
1458 |
|
temp = hwread(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK; |
1459 |
|
if (temp == ADB_MASK) { |
1460 |
|
/* First entry on this channel. */ |
1461 |
|
hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2), route[0]); |
1462 |
|
vortex_adb_en_sr(vortex, channel); |
1463 |
|
return; |
1464 |
|
} |
1465 |
|
/* Not first entry on this channel. Need to link. */ |
1466 |
|
do { |
1467 |
|
prev = temp; |
1468 |
|
temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK; |
1469 |
|
if ((lifeboat++) > ADB_MASK) { |
1470 |
|
printk(KERN_ERR "vortex_adb_addroutes: unending route!\n"); |
1471 |
|
return; |
1472 |
|
} |
1473 |
|
} while (temp != ADB_MASK); |
1474 |
|
hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]); |
1475 |
|
} |
1476 |
|
|
1477 |
|
void vortex_adb_delroutes(vortex_t *vortex, unsigned char channel, ADBRamLink route0, ADBRamLink route1) { |
1478 |
|
int temp, lifeboat = 0, prev; |
1479 |
|
|
1480 |
|
/* Find route. */ |
1481 |
|
temp = hwread(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK; |
1482 |
|
if (temp == (route0 & ADB_MASK)) { |
1483 |
|
temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2)); |
1484 |
|
if ((temp & ADB_MASK) == ADB_MASK) |
1485 |
|
vortex_adb_dis_sr(vortex, channel); |
1486 |
|
hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2), temp); |
1487 |
|
return; |
1488 |
|
} |
1489 |
|
do { |
1490 |
|
prev = temp; |
1491 |
|
temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK; |
1492 |
|
if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) { |
1493 |
|
printk(KERN_ERR "vortex_adb_delroutes: route not found!\n"); |
1494 |
|
return; |
1495 |
|
} |
1496 |
|
} while (temp != (route0 & ADB_MASK)); |
1497 |
|
temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2)); |
1498 |
|
if ((temp & ADB_MASK) == route1) |
1499 |
|
temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2)); |
1500 |
|
/* Make bridge over deleted route. */ |
1501 |
|
hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp); |
1502 |
|
} |
1503 |
|
|
1504 |
|
void vortex_route(vortex_t *vortex, int en, unsigned char channel, unsigned char source, unsigned char dest) { |
1505 |
|
ADBRamLink route; |
1506 |
|
|
1507 |
|
route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK); |
1508 |
|
if (en) { |
1509 |
|
vortex_adb_addroutes(vortex, channel, &route, 1); |
1510 |
|
if ((source < (OFFSET_SRCOUT+NR_SRC)) && (source >= OFFSET_SRCOUT)) |
1511 |
|
vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT), channel); |
1512 |
|
else if ((source < (OFFSET_MIXOUT+NR_MIXOUT)) && (source >= OFFSET_MIXOUT)) |
1513 |
|
vortex_mixer_addWTD(vortex, (source - OFFSET_MIXOUT), channel); |
1514 |
|
} else { |
1515 |
|
vortex_adb_delroutes(vortex, channel, route, route); |
1516 |
|
if ((source < (OFFSET_SRCOUT+NR_SRC)) && (source >= OFFSET_SRCOUT)) |
1517 |
|
vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT), channel); |
1518 |
|
else if ((source < (OFFSET_MIXOUT+NR_MIXOUT)) && (source >= OFFSET_MIXOUT)) |
1519 |
|
vortex_mixer_delWTD(vortex, (source - OFFSET_MIXOUT), channel); |
1520 |
|
} |
1521 |
|
} |
1522 |
|
|
1523 |
|
void vortex_routes(vortex_t *vortex, int en, unsigned char channel, unsigned char source, |
1524 |
|
unsigned char dest0, unsigned char dest1) { |
1525 |
|
ADBRamLink route[2]; |
1526 |
|
|
1527 |
|
route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK); |
1528 |
|
route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK); |
1529 |
|
|
1530 |
|
if (en) { |
1531 |
|
vortex_adb_addroutes(vortex, channel, route, 2); |
1532 |
|
if ((source < (OFFSET_SRCOUT+NR_SRC)) && (source >= (OFFSET_SRCOUT))) |
1533 |
|
vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT), channel); |
1534 |
|
else if ((source < (OFFSET_MIXOUT+NR_MIXOUT)) && (source >= (OFFSET_MIXOUT))) |
1535 |
|
vortex_mixer_addWTD(vortex, (source - OFFSET_MIXOUT), channel); |
1536 |
|
} else { |
1537 |
|
vortex_adb_delroutes(vortex, channel, route[0], route[1]); |
1538 |
|
if ((source < (OFFSET_SRCOUT+NR_SRC)) && (source >= (OFFSET_SRCOUT))) |
1539 |
|
vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT), channel); |
1540 |
|
else if ((source < (OFFSET_MIXOUT+NR_MIXOUT)) && (source >= (OFFSET_MIXOUT))) |
1541 |
|
vortex_mixer_delWTD(vortex, (source - OFFSET_MIXOUT), channel); |
1542 |
|
} |
1543 |
|
} |
1544 |
|
|
1545 |
|
/* Route two sources to same target. Sources must be of same class !!! */ |
1546 |
|
void vortex_routeLRT(vortex_t *vortex, int en, unsigned char ch, unsigned char source0, |
1547 |
|
unsigned char source1, unsigned char dest) { |
1548 |
|
ADBRamLink route[2]; |
1549 |
|
|
1550 |
|
route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK); |
1551 |
|
route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK); |
1552 |
|
|
1553 |
|
if (dest < 0x10) |
1554 |
|
route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20); |
1555 |
|
|
1556 |
|
if (en) { |
1557 |
|
vortex_adb_addroutes(vortex, ch, route, 2); |
1558 |
|
if ((source0 < (OFFSET_SRCOUT+NR_SRC)) && (source0 >= OFFSET_SRCOUT)) { |
1559 |
|
vortex_src_addWTD(vortex, (source0 - OFFSET_SRCOUT), ch); |
1560 |
|
vortex_src_addWTD(vortex, (source1 - OFFSET_SRCOUT), ch); |
1561 |
|
} |
1562 |
|
else if ((source0 < (OFFSET_MIXOUT+NR_MIXOUT)) && (source0 >= OFFSET_MIXOUT)) { |
1563 |
|
vortex_mixer_addWTD(vortex, (source0 - OFFSET_MIXOUT), ch); |
1564 |
|
vortex_mixer_addWTD(vortex, (source1 - OFFSET_MIXOUT), ch); |
1565 |
|
} |
1566 |
|
} else { |
1567 |
|
vortex_adb_delroutes(vortex, ch, route[0], route[1]); |
1568 |
|
if ((source0 < (OFFSET_SRCOUT+NR_SRC)) && (source0 >= OFFSET_SRCOUT)) { |
1569 |
|
vortex_src_delWTD(vortex, (source0 - OFFSET_SRCOUT), ch); |
1570 |
|
vortex_src_delWTD(vortex, (source1 - OFFSET_SRCOUT), ch); |
1571 |
|
} |
1572 |
|
else if ((source0 < (OFFSET_MIXOUT+NR_MIXOUT)) && (source0 >= OFFSET_MIXOUT)) { |
1573 |
|
vortex_mixer_delWTD(vortex, (source0 - OFFSET_MIXOUT), ch); |
1574 |
|
vortex_mixer_delWTD(vortex, (source1 - OFFSET_MIXOUT), ch); |
1575 |
|
} |
1576 |
|
} |
1577 |
|
} |
1578 |
|
|
1579 |
|
/* Connection stuff */ |
1580 |
|
|
1581 |
|
// Connect adbdma to src('s). |
1582 |
|
void vortex_connection_adbdma_src(vortex_t *vortex, int en, unsigned char ch, |
1583 |
|
unsigned char adbdma, unsigned char src) { |
1584 |
|
vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src)); |
1585 |
|
} |
1586 |
|
|
1587 |
|
void vortex_connection_adbdma_src_src(vortex_t *vortex, int en, unsigned char channel, |
1588 |
|
unsigned char adbdma, unsigned char src0, unsigned char src1) { |
1589 |
|
vortex_routes(vortex, en, channel, ADB_DMA(adbdma), ADB_SRCIN(src0), ADB_SRCIN(src1)); |
1590 |
|
} |
1591 |
|
|
1592 |
|
// Connect SRC to mixin. |
1593 |
|
void vortex_connection_src_mixin(vortex_t *vortex, int en, unsigned char channel, |
1594 |
|
unsigned char src, unsigned char mixin) { |
1595 |
|
vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin)); |
1596 |
|
} |
1597 |
|
|
1598 |
|
// Connect mixin with mix output. |
1599 |
|
void vortex_connection_mixin_mix(vortex_t *vortex, int en, unsigned char mixin, unsigned char mix, int a) { |
1600 |
|
if (en) { |
1601 |
|
vortex_mix_enableinput(vortex, mix, mixin); |
1602 |
|
vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN); // added to original code. |
1603 |
|
} else |
1604 |
|
vortex_mix_disableinput(vortex, mix, mixin, a); |
1605 |
|
} |
1606 |
|
|
1607 |
|
// Connect absolut address to mixin. |
1608 |
|
void vortex_connection_adb_mixin(vortex_t *vortex, int en, unsigned char channel, |
1609 |
|
unsigned char source, unsigned char mixin) { |
1610 |
|
vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin)); |
1611 |
|
} |
1612 |
|
|
1613 |
|
// Connect two mix to AdbDma. |
1614 |
|
void vortex_connection_mix_mix_adbdma(vortex_t *vortex, int en, unsigned char ch, |
1615 |
|
unsigned char mix0, unsigned char mix1, unsigned char adbdma) { |
1616 |
|
|
1617 |
|
ADBRamLink routes[2]; |
1618 |
|
routes[0] = (((mix0 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK); |
1619 |
|
routes[1] = (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma + 0x20 /*OFFSET_MIXOUT*/) & ADB_MASK); |
1620 |
|
if (en) { |
1621 |
|
vortex_adb_addroutes(vortex, ch, routes, 0x2); |
1622 |
|
vortex_mixer_addWTD(vortex, mix0, ch); |
1623 |
|
vortex_mixer_addWTD(vortex, mix1, ch); |
1624 |
|
} |
1625 |
|
else { |
1626 |
|
vortex_adb_delroutes(vortex, ch, routes[0], routes[1]); |
1627 |
|
vortex_mixer_delWTD(vortex, mix0, ch); |
1628 |
|
vortex_mixer_delWTD(vortex, mix1, ch); |
1629 |
|
} |
1630 |
|
} |
1631 |
|
|
1632 |
|
void vortex_connection_src_adbdma(vortex_t *vortex, int en, unsigned char ch, |
1633 |
|
unsigned char src, unsigned char adbdma) { |
1634 |
|
vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma)); |
1635 |
|
} |
1636 |
|
|
1637 |
|
void vortex_connection_src_src_adbdma(vortex_t *vortex, int en, unsigned char ch, |
1638 |
|
unsigned char src0, unsigned char src1, unsigned char adbdma) { |
1639 |
|
|
1640 |
|
vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1), ADB_DMA(adbdma)); |
1641 |
|
} |
1642 |
|
|
1643 |
|
// mix to absolut address. |
1644 |
|
void vortex_connection_mix_adb(vortex_t *vortex, int en, unsigned char ch, |
1645 |
|
unsigned char mix, unsigned char dest) { |
1646 |
|
vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest); |
1647 |
|
vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code. |
1648 |
|
} |
1649 |
|
|
1650 |
|
// mixer to src. |
1651 |
|
void vortex_connection_mix_src(vortex_t *vortex, int en, unsigned char ch, |
1652 |
|
unsigned char mix, unsigned char src) { |
1653 |
|
vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src)); |
1654 |
|
vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code. |
1655 |
|
} |
1656 |
|
|
1657 |
|
/* CODEC connect. */ |
1658 |
|
void vortex_connect_codecplay(vortex_t *vortex, int en, unsigned char mix0, unsigned char mix1) { |
1659 |
|
#ifdef CHIP_AU8820 |
1660 |
|
vortex_connection_mix_adb(vortex, en, 0x11, mix0, ADB_CODECOUT(0)); |
1661 |
|
vortex_connection_mix_adb(vortex, en, 0x11, mix1, ADB_CODECOUT(1)); |
1662 |
|
#else |
1663 |
|
#if 1 |
1664 |
|
//Connect EQ. |
1665 |
|
vortex_connection_mix_adb(vortex, en, 0x11, mix0, ADB_EQIN(0)); |
1666 |
|
vortex_connection_mix_adb(vortex, en, 0x11, mix1, ADB_EQIN(1)); |
1667 |
|
vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0)); |
1668 |
|
vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1)); |
1669 |
|
#else |
1670 |
|
// Use plain direct output to codec, since EQ still doesnt work. |
1671 |
|
vortex_connection_mix_adb(vortex, en, 0x11, mix0, ADB_CODECOUT(0)); |
1672 |
|
vortex_connection_mix_adb(vortex, en, 0x11, mix1, ADB_CODECOUT(1)); |
1673 |
|
#endif |
1674 |
|
#endif |
1675 |
|
} |
1676 |
|
|
1677 |
|
void vortex_connect_codecrec(vortex_t *vortex, int en, unsigned char mixin0, unsigned char mixin1) { |
1678 |
|
/* |
1679 |
|
Enable: 0x1, 0x1 |
1680 |
|
Channel: 0x11, 0x11 |
1681 |
|
ADB Source address: 0x48, 0x49 |
1682 |
|
Destination Asp4Topology_0x9c,0x98 |
1683 |
|
*/ |
1684 |
|
vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0); |
1685 |
|
vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1); |
1686 |
|
} |
1687 |
|
|
1688 |
|
// Higher level audio path (de)allocator. |
1689 |
|
|
1690 |
|
void vortex_connect_default(vortex_t *vortex, int en) { |
1691 |
|
// Connect codec. |
1692 |
|
vortex_connect_codecplay(vortex, en, MIX_OUTL, MIX_OUTR); |
1693 |
|
vortex_connect_codecrec(vortex, en, MIX_INL, MIX_INR); |
1694 |
|
} |
1695 |
|
|
1696 |
|
int vortex_getadb(vortex_t *vortex) { |
1697 |
|
int adb = 1; /* FIXME why do we get chip'n dale bug if setting this to 0???*/ |
1698 |
|
while (vortex->dma_adb[adb].nr_ch) { |
1699 |
|
adb++; |
1700 |
|
if (adb >= NR_ADB) |
1701 |
|
return -EBUSY; |
1702 |
|
} |
1703 |
|
vortex->dma_adb[adb].nr_ch = -1; |
1704 |
|
vortex->dma_adb[adb].dma = adb; |
1705 |
|
return adb; |
1706 |
|
} |
1707 |
|
|
1708 |
|
int vortex_getwt(vortex_t *vortex) { |
1709 |
|
int wt = 0; |
1710 |
|
while (vortex->dma_wt[wt].nr_ch) { |
1711 |
|
wt++; |
1712 |
|
if (wt >= NR_WT) |
1713 |
|
return -EBUSY; |
1714 |
|
} |
1715 |
|
vortex->dma_wt[wt].nr_ch = -1; |
1716 |
|
vortex->dma_adb[wt].dma = wt; |
1717 |
|
return wt; |
1718 |
|
} |
1719 |
|
|
1720 |
|
/* |
1721 |
|
Allocate nr_ch pcm audio routes. If nr_ch is 0, existing routes |
1722 |
|
are deallocated. |
1723 |
|
*/ |
1724 |
|
int vortex_adb_waveroute(vortex_t *vortex, int adbdma, int nr_ch) { |
1725 |
|
dma_t *dma = &vortex->dma_adb[adbdma]; |
1726 |
|
int n, en; |
1727 |
|
|
1728 |
|
n = adbdma*2; |
1729 |
|
if (nr_ch == 0) { |
1730 |
|
if (dma->nr_ch <= 0) |
1731 |
|
return -EBUSY; |
1732 |
|
printk(KERN_INFO "vortex: de alloc %d\n", adbdma); |
1733 |
|
en = 0; |
1734 |
|
nr_ch = dma->nr_ch; |
1735 |
|
dma->nr_ch = -1; |
1736 |
|
vortex_fifo_setadbvalid(vortex, adbdma, 0); |
1737 |
|
} else { |
1738 |
|
if (dma->nr_ch > 0) |
1739 |
|
return -EBUSY; |
1740 |
|
printk(KERN_INFO "vortex: alloc %d\n", adbdma); |
1741 |
|
en = 1; |
1742 |
|
dma->nr_ch = nr_ch; |
1743 |
|
vortex_fifo_adbinitialize(vortex, adbdma, FIFO_SIZE-1); |
1744 |
|
} |
1745 |
|
if (dma->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
1746 |
|
vortex_connection_src_mixin(vortex, en, 0x11, n, n); |
1747 |
|
vortex_connection_mixin_mix(vortex, en, n, MIX_OUTL, 0); |
1748 |
|
} else { |
1749 |
|
vortex_connection_mixin_mix(vortex, en, MIX_INL, n, 0); |
1750 |
|
vortex_mix_setvolumebyte(vortex, n, MIX_DEFOGAIN); |
1751 |
|
vortex_mix_setinputvolumebyte(vortex, n, MIX_INL, MIX_DEFIGAIN); |
1752 |
|
vortex_connection_mix_src(vortex, en, 0x11, n, n); |
1753 |
|
} |
1754 |
|
if (nr_ch == 1) { |
1755 |
|
if (dma->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
1756 |
|
vortex_connection_adbdma_src(vortex, en, n, adbdma, n); |
1757 |
|
vortex_connection_mixin_mix(vortex, en, n, MIX_OUTR, 0); |
1758 |
|
} else { |
1759 |
|
vortex_connection_src_adbdma(vortex, en, n, n, adbdma); |
1760 |
|
vortex_connection_mixin_mix(vortex, en, MIX_INR, n, 0); |
1761 |
|
} |
1762 |
|
} |
1763 |
|
if (nr_ch == 2) { |
1764 |
|
if (dma->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
1765 |
|
vortex_connection_src_mixin(vortex, en, 0x11, n+1, n+1); |
1766 |
|
vortex_connection_mixin_mix(vortex, en, n+1, MIX_OUTR, 0); |
1767 |
|
vortex_connection_adbdma_src_src(vortex, en, n, adbdma, n, n+1); |
1768 |
|
} else { |
1769 |
|
vortex_connection_mixin_mix(vortex, en, MIX_INR, n+1, 0); |
1770 |
|
vortex_mix_setvolumebyte(vortex, n+1, MIX_DEFOGAIN); |
1771 |
|
vortex_mix_setinputvolumebyte(vortex, n+1, MIX_INR, MIX_DEFIGAIN); |
1772 |
|
vortex_connection_mix_src(vortex, en, 0x11, n+1, n+1); |
1773 |
|
vortex_connection_src_src_adbdma(vortex, en, n, n, n+1, adbdma); |
1774 |
|
} |
1775 |
|
} |
1776 |
|
return 0; |
1777 |
|
} |
1778 |
|
|
1779 |
|
void vortex_adb_setsrc(vortex_t *vortex, int adbdma, unsigned int rate, int dir) { |
1780 |
|
dma_t *dma = &(vortex->dma_adb[adbdma]); |
1781 |
|
int i, cvrt; |
1782 |
|
|
1783 |
|
/* dir=1:play ; dir=0:rec*/ |
1784 |
|
if (dir) |
1785 |
|
cvrt = SRC_RATIO(rate); |
1786 |
|
else |
1787 |
|
cvrt = SRC_RATIO2(rate); |
1788 |
|
for (i=0; i<(dma->nr_ch); i++) { |
1789 |
|
vortex_src_setupchannel(vortex, i+((dma->dma)*2),cvrt,0,0,((dma->dma)*2)+(dma->nr_ch)-1, |
1790 |
|
dir, 0, cvrt, dir); |
1791 |
|
} |
1792 |
|
} |
1793 |
|
// WT routing is still a mistery. |
1794 |
|
int vortex_wt_waveroute(vortex_t *vortex, int wtdma, int nr_ch) { |
1795 |
|
//FIXME: WT audio routing. |
1796 |
|
if (nr_ch) { |
1797 |
|
vortex_fifo_wtinitialize(vortex, wtdma, 1); |
1798 |
|
vortex_wt_setstereo(vortex, wtdma, nr_ch-1); |
1799 |
|
} else |
1800 |
|
vortex_fifo_setwtvalid(vortex, wtdma, 0); |
1801 |
|
return 0; |
1802 |
|
} |
1803 |
|
|
1804 |
|
// Timer and ISR functions. |
1805 |
|
|
1806 |
|
void vortex_settimer(vortex_t *vortex, int period) { |
1807 |
|
//set the timer period to <period> 48000ths of a second. |
1808 |
|
hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period); |
1809 |
|
} |
1810 |
|
|
1811 |
|
void vortex_enable_timer_int(vortex_t *card){ |
1812 |
|
hwwrite(card->mmio, VORTEX_IRQ_CTRL, hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60); |
1813 |
|
} |
1814 |
|
|
1815 |
|
void vortex_disable_timer_int(vortex_t *card){ |
1816 |
|
hwwrite(card->mmio, VORTEX_IRQ_CTRL, hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER); |
1817 |
|
} |
1818 |
|
|
1819 |
|
void vortex_enable_int(vortex_t *card){ |
1820 |
|
// CAsp4ISR__EnableVortexInt_void_ |
1821 |
|
hwwrite(card->mmio, VORTEX_CTRL, hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE); |
1822 |
|
hwwrite(card->mmio, VORTEX_IRQ_CTRL, (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24); |
1823 |
|
} |
1824 |
|
|
1825 |
|
void vortex_disable_int(vortex_t *card){ |
1826 |
|
hwwrite(card->mmio, VORTEX_CTRL, hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE); |
1827 |
|
} |
1828 |
|
|
1829 |
|
irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs) { |
1830 |
|
vortex_t *vortex = snd_magic_cast(vortex_t, dev_id, return IRQ_NONE); |
1831 |
|
int i, handled; |
1832 |
|
u32 source; |
1833 |
|
//check if the interrupt is ours. |
1834 |
|
if (!(hwread(vortex->mmio, VORTEX_IRQ_U0) & 0x1)) |
1835 |
|
return IRQ_NONE; |
1836 |
|
|
1837 |
|
// This is the Interrrupt Enable flag we set before (consistency check). |
1838 |
|
if ((hwread(vortex->mmio, VORTEX_CTRL) & 0x0000ff00) == CTRL_IRQ_ENABLE) |
1839 |
|
return IRQ_HANDLED; |
1840 |
|
|
1841 |
|
source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE); |
1842 |
|
// Reset IRQ flags. |
1843 |
|
hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source); |
1844 |
|
hwread(vortex->mmio, VORTEX_IRQ_SOURCE); |
1845 |
|
// Is at least one IRQ flag set? |
1846 |
|
if (source == 0) { |
1847 |
|
printk(KERN_ERR "vortex: missing irq source\n"); |
1848 |
|
return IRQ_NONE; |
1849 |
|
} |
1850 |
|
|
1851 |
|
//printk(KERN_INFO "IRQ: 0x%x\n", source); |
1852 |
|
|
1853 |
|
handled = 0; |
1854 |
|
// Attend every interrupt source. |
1855 |
|
if (source & IRQ_FATAL) { |
1856 |
|
printk(KERN_ERR "vortex: IRQ fatal error\n"); |
1857 |
|
handled = 1; |
1858 |
|
} |
1859 |
|
if (source & IRQ_PARITY) { |
1860 |
|
printk(KERN_ERR "vortex: IRQ parity error\n"); |
1861 |
|
handled = 1; |
1862 |
|
} |
1863 |
|
if (source & IRQ_PCMOUT) { |
1864 |
|
/* ALSA period acknowledge. */ |
1865 |
|
for (i=0; i<NR_ADB; i++) { |
1866 |
|
if (vortex->dma_adb[i].fifo_status == FIFO_START) { |
1867 |
|
vortex_adbdma_bufshift(vortex, i); |
1868 |
|
snd_pcm_period_elapsed(vortex->dma_adb[i].substream); |
1869 |
|
} |
1870 |
|
} |
1871 |
|
for (i=0; i<NR_WT; i++) { |
1872 |
|
if (vortex->dma_wt[i].fifo_status == FIFO_START) { |
1873 |
|
vortex_wtdma_bufshift(vortex, i); |
1874 |
|
snd_pcm_period_elapsed(vortex->dma_wt[i].substream); |
1875 |
|
} |
1876 |
|
} |
1877 |
|
handled = 1; |
1878 |
|
} |
1879 |
|
//Acknowledge the Timer interrupt |
1880 |
|
if (source & IRQ_TIMER) { |
1881 |
|
hwread(vortex->mmio, VORTEX_IRQ_STAT); |
1882 |
|
handled = 1; |
1883 |
|
} |
1884 |
|
if (source & IRQ_MIDI) { |
1885 |
|
snd_mpu401_uart_interrupt(vortex->irq, vortex->rmidi->private_data, regs); |
1886 |
|
handled = 1; |
1887 |
|
} |
1888 |
|
|
1889 |
|
if (!handled) { |
1890 |
|
printk(KERN_ERR "vortex: unknown irq source %x\n", source); |
1891 |
|
} |
1892 |
|
return IRQ_RETVAL(handled); |
1893 |
|
} |
1894 |
|
|
1895 |
|
/* Codec */ |
1896 |
|
|
1897 |
|
#define POLL_COUNT 1000 |
1898 |
|
void vortex_codec_init(vortex_t *vortex) { |
1899 |
|
int i; |
1900 |
|
|
1901 |
|
for(i =0; i<32; i++){ |
1902 |
|
hwwrite(vortex->mmio,(VORTEX_CODEC_CHN+(i<<2)),0); |
1903 |
|
udelay(5000); |
1904 |
|
} |
1905 |
|
if (0) { |
1906 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x8068); |
1907 |
|
udelay(1000); |
1908 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x00e8); |
1909 |
|
udelay(1000); |
1910 |
|
} else { |
1911 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x00a8); |
1912 |
|
udelay(1000); |
1913 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x80a8); |
1914 |
|
udelay(1000); |
1915 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x80e8); |
1916 |
|
udelay(1000); |
1917 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x80a8); |
1918 |
|
udelay(1000); |
1919 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x00a8); |
1920 |
|
udelay(1000); |
1921 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0x00e8); |
1922 |
|
} |
1923 |
|
for(i =0; i<32; i++){ |
1924 |
|
hwwrite(vortex->mmio,(VORTEX_CODEC_CHN+(i<<2)),0); |
1925 |
|
udelay(5000); |
1926 |
|
} |
1927 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_CTRL,0xe8); |
1928 |
|
udelay(1000); |
1929 |
|
/* Enable codec channels 0 and 1. */ |
1930 |
|
hwwrite(vortex->mmio,VORTEX_CODEC_EN, hwread(vortex->mmio,VORTEX_CODEC_EN) | 0x300); |
1931 |
|
} |
1932 |
|
|
1933 |
|
void vortex_codec_write(ac97_t *codec, unsigned short addr, unsigned short data){ |
1934 |
|
|
1935 |
|
vortex_t *card = (vortex_t*)codec->private_data; |
1936 |
|
unsigned long flags; |
1937 |
|
unsigned int lifeboat = 0; |
1938 |
|
unsigned long read_addr; |
1939 |
|
spin_lock_irqsave(&card->lock, flags); |
1940 |
|
|
1941 |
|
/* wait for transactions to clear */ |
1942 |
|
while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) { |
1943 |
|
udelay(100); |
1944 |
|
if (lifeboat++ > POLL_COUNT) { |
1945 |
|
printk(KERN_ERR "vortex: ac97 codec stuck busy\n"); |
1946 |
|
spin_unlock_irqrestore(&card->lock, flags); |
1947 |
|
return; |
1948 |
|
} |
1949 |
|
} |
1950 |
|
|
1951 |
|
/* write register */ |
1952 |
|
hwwrite(card->mmio, VORTEX_CODEC_IO, ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) | |
1953 |
|
((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) | VORTEX_CODEC_WRITE); |
1954 |
|
|
1955 |
|
/* this is necessary to flush the write */ |
1956 |
|
lifeboat = 0; |
1957 |
|
while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) { |
1958 |
|
udelay(100); |
1959 |
|
if (lifeboat++ > POLL_COUNT) { |
1960 |
|
printk(KERN_ERR "vortex: ac97 codec stuck busy\n"); |
1961 |
|
spin_unlock_irqrestore(&card->lock, flags); |
1962 |
|
return; |
1963 |
|
} |
1964 |
|
} |
1965 |
|
|
1966 |
|
read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK); |
1967 |
|
hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr); |
1968 |
|
spin_unlock_irqrestore(&card->lock, flags); |
1969 |
|
} |
1970 |
|
|
1971 |
|
unsigned short vortex_codec_read(ac97_t *codec, unsigned short addr) { |
1972 |
|
|
1973 |
|
u32 read_addr; |
1974 |
|
vortex_t *card = (vortex_t*)codec->private_data; |
1975 |
|
unsigned long flags; |
1976 |
|
unsigned lifeboat = 0; |
1977 |
|
u16 x; |
1978 |
|
|
1979 |
|
spin_lock_irqsave(&card->lock, flags); |
1980 |
|
|
1981 |
|
/* wait for transactions to clear */ |
1982 |
|
while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) { |
1983 |
|
udelay(100); |
1984 |
|
if (lifeboat++ > POLL_COUNT) { |
1985 |
|
printk(KERN_ERR "vortex: ac97 codec stuck busy\n"); |
1986 |
|
spin_unlock_irqrestore(&card->lock, flags); |
1987 |
|
return 0xffff; |
1988 |
|
} |
1989 |
|
} |
1990 |
|
|
1991 |
|
/* set up read address */ |
1992 |
|
read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK); |
1993 |
|
hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr); |
1994 |
|
|
1995 |
|
/* wait for address */ |
1996 |
|
lifeboat = 0; |
1997 |
|
while ((hwread(card->mmio, VORTEX_CODEC_IO) & VORTEX_CODEC_ADDMASK) != (addr << VORTEX_CODEC_ADDSHIFT)) { |
1998 |
|
udelay(100); |
1999 |
|
if (lifeboat++ > POLL_COUNT) { |
2000 |
|
printk(KERN_ERR "vortex: ac97 address never arrived\n"); |
2001 |
|
spin_unlock_irqrestore(&card->lock, flags); |
2002 |
|
return 0xffff; |
2003 |
|
} |
2004 |
|
} |
2005 |
|
|
2006 |
|
/* read codec */ |
2007 |
|
x = hwread(card->mmio, VORTEX_CODEC_IO) & VORTEX_CODEC_DATMASK; |
2008 |
|
spin_unlock_irqrestore(&card->lock, flags); |
2009 |
|
|
2010 |
|
return x; |
2011 |
|
} |
2012 |
|
|
2013 |
|
/* Initialization */ |
2014 |
|
|
2015 |
|
int vortex_core_init(vortex_t *vortex) { |
2016 |
|
|
2017 |
|
printk(KERN_INFO "Vortex: hardware init.... "); |
2018 |
|
/* Hardware Init. */ |
2019 |
|
hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff); |
2020 |
|
udelay(5000); |
2021 |
|
hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff); |
2022 |
|
udelay(5000); |
2023 |
|
/* Reset IRQ flags */ |
2024 |
|
hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff); |
2025 |
|
hwread(vortex->mmio, VORTEX_IRQ_STAT); |
2026 |
|
|
2027 |
|
vortex_codec_init(vortex); |
2028 |
|
|
2029 |
|
/* Audio engine init. */ |
2030 |
|
vortex_fifo_init(vortex); |
2031 |
|
hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58 |
2032 |
|
vortex_adb_init(vortex); |
2033 |
|
/* Routing blocks init. */ |
2034 |
|
vortex_adbdma_init(vortex); |
2035 |
|
vortex_mixer_init(vortex); |
2036 |
|
vortex_srcblock_init(vortex); |
2037 |
|
#ifndef CHIP_AU8820 |
2038 |
|
vortex_eq_init(vortex); |
2039 |
|
#endif |
2040 |
|
vortex_connect_default(vortex, 1); |
2041 |
|
|
2042 |
|
vortex_settimer(vortex, 0x90); |
2043 |
|
// Enable Interrupts. |
2044 |
|
// vortex_enable_int() must be first !! |
2045 |
|
// hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0); |
2046 |
|
// vortex_enable_int(vortex); |
2047 |
|
//vortex_enable_timer_int(vortex); |
2048 |
|
//vortex_disable_timer_int(vortex); |
2049 |
|
|
2050 |
|
printk(KERN_INFO "done.\n"); |
2051 |
|
spin_lock_init(&vortex->lock); |
2052 |
|
|
2053 |
|
return 0; |
2054 |
|
} |
2055 |
|
|
2056 |
|
int vortex_core_shutdown(vortex_t *vortex) { |
2057 |
|
|
2058 |
|
printk(KERN_INFO "Vortex: hardware shutdown..."); |
2059 |
|
#ifndef CHIP_AU8820 |
2060 |
|
vortex_eq_free(vortex); |
2061 |
|
#endif |
2062 |
|
vortex_disable_timer_int(vortex); |
2063 |
|
vortex_disable_int(vortex); |
2064 |
|
vortex_connect_default(vortex, 0); |
2065 |
|
/* Reset all DMA fifos. */ |
2066 |
|
vortex_fifo_init(vortex); |
2067 |
|
/* Erase all audio routes. */ |
2068 |
|
vortex_adb_init(vortex); |
2069 |
|
|
2070 |
|
/* Disable MPU401 */ |
2071 |
|
//hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) & ~IRQ_MIDI); |
2072 |
|
//hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_EN); |
2073 |
|
|
2074 |
|
hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0); |
2075 |
|
hwwrite(vortex->mmio, VORTEX_CTRL, 0); |
2076 |
|
udelay(5000); |
2077 |
|
hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0); |
2078 |
|
|
2079 |
|
printk(KERN_INFO "done.\n"); |
2080 |
|
return 0; |
2081 |
|
} |
2082 |
|
|
2083 |
|
/* Alsa support. */ |
2084 |
|
|
2085 |
|
int vortex_alsafmt_aspfmt(int alsafmt) { |
2086 |
|
int fmt; |
2087 |
|
|
2088 |
|
switch (alsafmt) { |
2089 |
|
case SNDRV_PCM_FORMAT_U8: fmt = 0x1; |
2090 |
|
break; |
2091 |
|
case SNDRV_PCM_FORMAT_MU_LAW: fmt = 0x2; |
2092 |
|
break; |
2093 |
|
case SNDRV_PCM_FORMAT_A_LAW: fmt = 0x3; |
2094 |
|
break; |
2095 |
|
case SNDRV_PCM_FORMAT_SPECIAL: fmt = 0x4; /* guess. */ |
2096 |
|
break; |
2097 |
|
case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: fmt = 0x5; /* guess. */ |
2098 |
|
break; |
2099 |
|
case SNDRV_PCM_FORMAT_S16_LE: fmt = 0x8; |
2100 |
|
break; |
2101 |
|
default: fmt = 0x8; |
2102 |
|
printk(KERN_ERR "vortex: format unsupported %d\n", alsafmt); |
2103 |
|
break; |
2104 |
|
} |
2105 |
|
return fmt; |
2106 |
|
} |
2107 |
|
|
2108 |
|
/* Some not yet useful translations. */ |
2109 |
|
|
2110 |
|
typedef enum { |
2111 |
|
ASPFMTLINEAR16 = 0, /* 0x8 */ |
2112 |
|
ASPFMTLINEAR8, /* 0x1 */ |
2113 |
|
ASPFMTULAW, /* 0x2 */ |
2114 |
|
ASPFMTALAW, /* 0x3 */ |
2115 |
|
ASPFMTSPORT, /* ? */ |
2116 |
|
ASPFMTSPDIF, /* ? */ |
2117 |
|
} ASPENCODING; |
2118 |
|
|
2119 |
|
int vortex_translateformat(vortex_t *vortex, char bits, char nch, int encod) { |
2120 |
|
int a, this_194; |
2121 |
|
|
2122 |
|
if ((bits != 8) || (bits != 16)) |
2123 |
|
return -1; |
2124 |
|
|
2125 |
|
switch (encod) { |
2126 |
|
case 0: |
2127 |
|
if (bits == 0x10) |
2128 |
|
a = 8; // 16 bit |
2129 |
|
break; |
2130 |
|
case 1: |
2131 |
|
if (bits == 8) |
2132 |
|
a = 1; // 8 bit |
2133 |
|
break; |
2134 |
|
case 2: a = 2; // U_LAW |
2135 |
|
break; |
2136 |
|
case 3: a = 3; // A_LAW |
2137 |
|
break; |
2138 |
|
} |
2139 |
|
switch (nch) { |
2140 |
|
case 1: this_194 = 0; |
2141 |
|
break; |
2142 |
|
case 2: this_194 = 1; |
2143 |
|
break; |
2144 |
|
case 4: this_194 = 1; |
2145 |
|
break; |
2146 |
|
case 6: this_194 = 1; |
2147 |
|
break; |
2148 |
|
} |
2149 |
|
return(a); |
2150 |
|
} |
2151 |
|
|
2152 |
|
void vortex_cdmacore_setformat(vortex_t *vortex, int bits, int nch) { |
2153 |
|
short int d, this_148; |
2154 |
|
|
2155 |
|
d = ((bits >> 3)*nch); |
2156 |
|
this_148 = 0xbb80 / d; |
2157 |
|
} |