14 |
to help to understand how does the AU88X0 chips work. Keep them in, because |
to help to understand how does the AU88X0 chips work. Keep them in, because |
15 |
they could be used somewhere in the future. |
they could be used somewhere in the future. |
16 |
|
|
17 |
This code hasn't been tested or prove read thoroughly. If you wanna help, |
This code hasn't been tested or proof read thoroughly. If you wanna help, |
18 |
take a look at the AU88X0 assembler and check if this matches. |
take a look at the AU88X0 assembly and check if this matches. |
19 |
Functions tested ok so far are (they show the desired effect |
Functions tested ok so far are (they show the desired effect |
20 |
at least): |
at least): |
21 |
vortex_routes(); (1 bug fixed). |
vortex_routes(); (1 bug fixed). |
29 |
vortex_fifo_setadbctrl(); note: still some unknown arguments! |
vortex_fifo_setadbctrl(); note: still some unknown arguments! |
30 |
vortex_mix_setinputvolumebyte(); |
vortex_mix_setinputvolumebyte(); |
31 |
vortex_mix_enableinput(); |
vortex_mix_enableinput(); |
32 |
vortex_mixer_addWTD(); (broken) |
vortex_mixer_addWTD(); (fixed) |
33 |
vortex_connection_adbdma_src_src(); |
vortex_connection_adbdma_src_src(); |
34 |
vortex_connection_adbdma_src(); |
vortex_connection_adbdma_src(); |
35 |
vortex_src_change_convratio(); |
vortex_src_change_convratio(); |
36 |
vortex_src_addWTD(); (broken) |
vortex_src_addWTD(); (fixed) |
37 |
|
|
38 |
History: |
History: |
39 |
|
|
49 |
12-03-2003 ALSA driver starts working (2 channels). |
12-03-2003 ALSA driver starts working (2 channels). |
50 |
16-03-2003 More srcblock_setupchannel discoveries. |
16-03-2003 More srcblock_setupchannel discoveries. |
51 |
12-04-2003 AU8830 playback support. Recording in the works. |
12-04-2003 AU8830 playback support. Recording in the works. |
52 |
|
17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording |
53 |
|
works now, but chipn' dale effect is still there. |
54 |
*/ |
*/ |
55 |
|
|
56 |
#include "au88x0.h" |
#include "au88x0.h" |
57 |
#include <linux/delay.h> |
#include <linux/delay.h> |
58 |
|
|
59 |
/* MIXER (CAsp4Mix.s and CAsp4Mixer.s) */ |
/* MIXER (CAsp4Mix.s and CAsp4Mixer.s) */ |
60 |
|
|
61 |
// FIXME: get rid of this. |
// FIXME: get rid of this. |
63 |
int rampchs[NR_MIXIN]; |
int rampchs[NR_MIXIN]; |
64 |
|
|
65 |
void vortex_mixer_en_sr(vortex_t *vortex, int channel) { |
void vortex_mixer_en_sr(vortex_t *vortex, int channel) { |
66 |
hwwrite(vortex->mmio, VORTEX_MIXER_SR, |
hwwrite(vortex->mmio, VORTEX_MIXER_SR, hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); |
|
hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); |
|
67 |
} |
} |
68 |
void vortex_mixer_dis_sr(vortex_t *vortex, int channel) { |
void vortex_mixer_dis_sr(vortex_t *vortex, int channel) { |
69 |
hwwrite(vortex->mmio, VORTEX_MIXER_SR, |
hwwrite(vortex->mmio, VORTEX_MIXER_SR, |
182 |
int vortex_mixer_addWTD(vortex_t *vortex, unsigned char mix, unsigned char ch) { |
int vortex_mixer_addWTD(vortex_t *vortex, unsigned char mix, unsigned char ch) { |
183 |
int temp, lifeboat = 0, prev; |
int temp, lifeboat = 0, prev; |
184 |
|
|
185 |
|
|
186 |
temp = hwread(vortex->mmio, VORTEX_MIXER_SR); |
temp = hwread(vortex->mmio, VORTEX_MIXER_SR); |
187 |
if ((temp & (1 << ch)) == 0) { |
if ((temp & (1 << ch)) == 0) { |
188 |
hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix); |
hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix); |
194 |
while (temp & 0x10) { |
while (temp & 0x10) { |
195 |
prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2); |
prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2); |
196 |
temp = hwread(vortex->mmio, prev); |
temp = hwread(vortex->mmio, prev); |
197 |
|
//printk("vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp); |
198 |
if ((++lifeboat) > 0xf) { |
if ((++lifeboat) > 0xf) { |
199 |
printk("vortex_mixer_addWTD: lifeboat overflow\n"); |
printk("vortex_mixer_addWTD: lifeboat overflow\n"); |
200 |
return 0; |
return 0; |
210 |
//int esp1f=edi(while)=src, esp10=ch; |
//int esp1f=edi(while)=src, esp10=ch; |
211 |
|
|
212 |
eax = hwread(vortex->mmio, VORTEX_MIXER_SR); |
eax = hwread(vortex->mmio, VORTEX_MIXER_SR); |
213 |
if (((1 << ch) & eax) == 0) |
if (((1 << ch) & eax) == 0) { |
214 |
|
printk("mix ALARM %x\n", eax); |
215 |
return 0; |
return 0; |
216 |
|
} |
217 |
ebp = VORTEX_MIXER_CHNBASE + (ch << 2); |
ebp = VORTEX_MIXER_CHNBASE + (ch << 2); |
218 |
esp18 = hwread(vortex->mmio, ebp); |
esp18 = hwread(vortex->mmio, ebp); |
219 |
if (esp18 & 0x10) { |
if (esp18 & 0x10) { |
263 |
} |
} |
264 |
} |
} |
265 |
} else { |
} else { |
266 |
|
printk("removed last mix\n"); |
267 |
//7be0 |
//7be0 |
268 |
vortex_mixer_dis_sr(vortex, ch); |
vortex_mixer_dis_sr(vortex, ch); |
269 |
hwwrite(vortex->mmio, ebp, 0); |
hwwrite(vortex->mmio, ebp, 0); |
302 |
memset(mchannels, 0, NR_MIXOUT*sizeof(int)); |
memset(mchannels, 0, NR_MIXOUT*sizeof(int)); |
303 |
memset(rampchs, 0, NR_MIXOUT*sizeof(int)); |
memset(rampchs, 0, NR_MIXOUT*sizeof(int)); |
304 |
|
|
|
|
|
|
//addr = 0x9d7c; /* 0x9c00 0x180*/ |
|
|
//addr=0x21d7c; /* 0x21c00 0x180*/ |
|
305 |
addr = VORTEX_MIX_U0 + 0x17c; |
addr = VORTEX_MIX_U0 + 0x17c; |
306 |
for (x = 0x5f; x >= 0; x--) { |
for (x = 0x5f; x >= 0; x--) { |
307 |
hwwrite(vortex->mmio, addr, 0); |
hwwrite(vortex->mmio, addr, 0); |
308 |
addr -= 4; |
addr -= 4; |
309 |
} |
} |
|
|
|
|
//addr = 0x9bfc; /* 0x9a00 0x200*/ |
|
|
//addr = 0x21bfc; /* 0x21a00 0x200*/ |
|
310 |
addr = VORTEX_MIX_ENIN + 0x1fc; |
addr = VORTEX_MIX_ENIN + 0x1fc; |
311 |
for (x = 0x7f; x >= 0; x--) { |
for (x = 0x7f; x >= 0; x--) { |
312 |
hwwrite(vortex->mmio, addr, 0); |
hwwrite(vortex->mmio, addr, 0); |
313 |
addr -= 4; |
addr -= 4; |
314 |
} |
} |
|
|
|
|
//addr = 0x9d7c; /* 0x9c00 again? why? */ |
|
|
//addr=0x21d7c; /* 0x21c00 0x180*/ |
|
315 |
addr = VORTEX_MIX_U0 + 0x17c; |
addr = VORTEX_MIX_U0 + 0x17c; |
316 |
for (x = 0x5f; x >= 0; x--) { |
for (x = 0x5f; x >= 0; x--) { |
317 |
hwwrite(vortex->mmio, addr, 0); |
hwwrite(vortex->mmio, addr, 0); |
318 |
addr -= 4; |
addr -= 4; |
319 |
} |
} |
|
|
|
|
//addr = 0x97fc; /* 0x9000 0x800*/ |
|
|
//addr = 0x217fc; /* 0x21000 0x800*/ |
|
320 |
addr = VORTEX_MIX_INVOL_A + 0x7fc; |
addr = VORTEX_MIX_INVOL_A + 0x7fc; |
321 |
for (x = 0x1ff; x >= 0; x--) { |
for (x = 0x1ff; x >= 0; x--) { |
322 |
hwwrite(vortex->mmio, addr, 0x80); |
hwwrite(vortex->mmio, addr, 0x80); |
323 |
addr -= 4; |
addr -= 4; |
324 |
} |
} |
|
|
|
|
//addr = 0x983c; /* 0x9800 */ |
|
|
//addr = 0x2183c; /* 0x21800 */ |
|
325 |
addr = VORTEX_MIX_VOL_A + 0x3c; |
addr = VORTEX_MIX_VOL_A + 0x3c; |
326 |
for (x = 0xf; x >= 0; x--) { |
for (x = 0xf; x >= 0; x--) { |
327 |
hwwrite(vortex->mmio, addr, 0x80); |
hwwrite(vortex->mmio, addr, 0x80); |
328 |
addr -= 4; |
addr -= 4; |
329 |
} |
} |
|
|
|
|
//addr = 0x87fc; /* 0x8000 */ |
|
|
//addr = 0x207fc; /* 0x20000 */ |
|
330 |
addr = VORTEX_MIX_INVOL_B + 0x7fc; |
addr = VORTEX_MIX_INVOL_B + 0x7fc; |
331 |
for (x = 0x1ff; x >= 0; x--) { |
for (x = 0x1ff; x >= 0; x--) { |
332 |
hwwrite(vortex->mmio, addr, 0x80); |
hwwrite(vortex->mmio, addr, 0x80); |
333 |
addr -= 4; |
addr -= 4; |
334 |
} |
} |
|
|
|
|
//addr = 0x883c; /* 0x8800 */ |
|
|
//addr = 0x2083c; /* 0x20800 */ |
|
335 |
addr = VORTEX_MIX_VOL_B + 0x3c; |
addr = VORTEX_MIX_VOL_B + 0x3c; |
336 |
for (x = 0xf; x >= 0; x--) { |
for (x = 0xf; x >= 0; x--) { |
337 |
hwwrite(vortex->mmio, addr, 0x80); |
hwwrite(vortex->mmio, addr, 0x80); |
338 |
addr -= 4; |
addr -= 4; |
339 |
} |
} |
|
|
|
|
//addr = 0x9e94; /* 0x9e00 / More than offset diff. */ |
|
|
//addr = 0x21edc; /* 0x21e00 / More than offset diff. */ |
|
340 |
addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE-1)*4; |
addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE-1)*4; |
|
//for (x = 0x25; x >= 0; x--) { |
|
|
//for (x = 0x37; x >= 0; x--) { |
|
341 |
for (x = (MIXER_RTBASE_SIZE-1); x >= 0; x--) { |
for (x = (MIXER_RTBASE_SIZE-1); x >= 0; x--) { |
342 |
hwwrite(vortex->mmio, addr, 0x0); |
hwwrite(vortex->mmio, addr, 0x0); |
343 |
addr -= 4; |
addr -= 4; |
344 |
} |
} |
|
|
|
345 |
hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0); |
hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0); |
346 |
/* |
/* |
347 |
call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____ |
call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____ |
348 |
Register ISR callback for volume smoth fade out. |
Register ISR callback for volume smooth fade out. |
349 |
maybe this avoids clicks when press "stop" ? |
Maybe this avoids clicks when press "stop" ? |
350 |
*/ |
*/ |
351 |
} |
} |
352 |
|
|
353 |
/* SRC (CAsp4Src.s and CAsp4SrcBlock) */ |
/* SRC (CAsp4Src.s and CAsp4SrcBlock) */ |
354 |
|
|
355 |
void vortex_src_en_sr(vortex_t *vortex, int channel) { |
void vortex_src_en_sr(vortex_t *vortex, int channel) { |
356 |
hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, |
hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel)); |
|
hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel)); |
|
357 |
} |
} |
358 |
void vortex_src_dis_sr(vortex_t *vortex, int channel) { |
void vortex_src_dis_sr(vortex_t *vortex, int channel) { |
359 |
hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, |
hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel)); |
|
hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel)); |
|
360 |
} |
} |
361 |
|
|
362 |
void vortex_src_flushbuffers(vortex_t *vortex, unsigned char src) { |
void vortex_src_flushbuffers(vortex_t *vortex, unsigned char src) { |
417 |
a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2; |
a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2; |
418 |
} else |
} else |
419 |
a = 0xc; |
a = 0xc; |
420 |
temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2)); |
temp = hwread(vortex->mmio, 0xce00 + (src << 2)); |
421 |
if (((temp >> 4) & 0xf) != a) |
if (((temp >> 4) & 0xf) != a) |
422 |
hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2), (temp & 0xf) | ((a & 0xf) << 4)); |
hwwrite(vortex->mmio, 0xce00 + (src << 2), (temp & 0xf) | ((a & 0xf) << 4)); |
423 |
|
|
424 |
vortex_src_persist_convratio(vortex, src, ratio); |
vortex_src_persist_convratio(vortex, src, ratio); |
425 |
} |
} |
541 |
prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12*/ |
prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12*/ |
542 |
//prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/ |
//prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/ |
543 |
temp = hwread(vortex->mmio, prev); |
temp = hwread(vortex->mmio, prev); |
544 |
|
//printk("vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp); |
545 |
if ((++lifeboat) > 0xf) { |
if ((++lifeboat) > 0xf) { |
546 |
printk("vortex_src_addWTD: lifeboat overflow\n"); |
printk("vortex_src_addWTD: lifeboat overflow\n"); |
547 |
return 0; |
return 0; |
558 |
//int esp1f=edi(while)=src, esp10=ch; |
//int esp1f=edi(while)=src, esp10=ch; |
559 |
|
|
560 |
eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR); |
eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR); |
561 |
if (((1 << ch) & eax) == 0) |
if (((1 << ch) & eax) == 0) { |
562 |
|
printk("src alarm\n"); |
563 |
return 0; |
return 0; |
564 |
|
} |
565 |
ebp = VORTEX_SRC_CHNBASE + (ch << 2); |
ebp = VORTEX_SRC_CHNBASE + (ch << 2); |
566 |
esp18 = hwread(vortex->mmio, ebp); |
esp18 = hwread(vortex->mmio, ebp); |
567 |
if (esp18 & 0x10) { |
if (esp18 & 0x10) { |
645 |
vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE); |
vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE); |
646 |
addr -= 4; |
addr -= 4; |
647 |
} |
} |
|
|
|
648 |
/* WT DMA channels fifos. */ |
/* WT DMA channels fifos. */ |
649 |
addr = VORTEX_FIFO_WTCTRL + ((NR_WT-1)*4); |
addr = VORTEX_FIFO_WTCTRL + ((NR_WT-1)*4); |
650 |
for (x = NR_WT-1; x >= 0; x--) { |
for (x = NR_WT-1; x >= 0; x--) { |
657 |
// FIXME |
// FIXME |
658 |
#ifndef CONFIG_SND_AU8820 |
#ifndef CONFIG_SND_AU8820 |
659 |
//temp = ebp; // = 0 ? |
//temp = ebp; // = 0 ? |
660 |
//hwwrite(dma->mmio, 0xf8c0, ((temp | 0x03 )&= 0xffffff83) | 0xd00); |
//hwwrite(dma->mmio, 0xf8c0, ((temp | 0x03 )& 0xffffff83) | 0xd00); |
661 |
hwwrite(vortex->mmio, 0xf8c0, 0x0843); //0xd03 0xd6b |
hwwrite(vortex->mmio, 0xf8c0, 0x0843); //0xd03 0xd6b |
662 |
#else |
#else |
663 |
hwwrite(vortex->mmio, 0x17000, 0x61); |
hwwrite(vortex->mmio, 0x17000, 0x61); |
715 |
} |
} |
716 |
} else { |
} else { |
717 |
if (temp & FIFO_VALID) |
if (temp & FIFO_VALID) |
|
//FIXME: AU8820 / AU8830 |
|
718 |
#ifdef CONFIG_SND_AU8820 |
#ifdef CONFIG_SND_AU8820 |
719 |
temp = ((f & 1) << 0x12) | (temp & 0xfffbffef); |
temp = ((f & 1) << 0x12) | (temp & 0xfffbffef); |
720 |
#else |
#else |
|
//temp = ((f & 1) << 0x1b) | (temp & 0xffffffef) | FIFO_BITS; |
|
721 |
temp = ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS; |
temp = ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS; |
722 |
#endif |
#endif |
723 |
else |
else |
1167 |
size--; |
size--; |
1168 |
dma->cfg0 |= (size << 0xc) | size; |
dma->cfg0 |= (size << 0xc) | size; |
1169 |
dma->cfg1 |= (size << 0xc) | size; |
dma->cfg1 |= (size << 0xc) | size; |
1170 |
printk("vortex: wt buffer cfg: 0x%8x 0x%8x\n", dma->cfg0, dma->cfg1); |
//printk("vortex: wt buffer cfg: 0x%8x 0x%8x\n", dma->cfg0, dma->cfg1); |
1171 |
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0); |
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0); |
1172 |
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1); |
hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1); |
1173 |
|
|
1335 |
hwwrite(vortex->mmio, offset + (wtdma << 3), *cfg); |
hwwrite(vortex->mmio, offset + (wtdma << 3), *cfg); |
1336 |
} |
} |
1337 |
|
|
1338 |
|
/* WT */ |
1339 |
|
|
1340 |
|
void vortex_wt_setstereo(vortex_t *vortex, u32 wt, u32 stereo) { |
1341 |
|
int temp; |
1342 |
|
|
1343 |
|
temp = hwread(vortex->mmio, 0x80 + ((((wt >> 0x5)<< 0xf) + ((wt & 0x1f) >> 1)) << 2)); |
1344 |
|
temp = (temp & 0xfe) | (stereo & 1); |
1345 |
|
hwwrite(vortex->mmio, 0x80 + ((((wt >> 0x5)<< 0xf) + ((wt & 0x1f) >> 1)) << 2), temp); |
1346 |
|
} |
1347 |
|
|
1348 |
|
void vortex_wt_setdsout(vortex_t *vortex, u32 wt, int en) { |
1349 |
|
int temp; |
1350 |
|
|
1351 |
|
temp = hwread(vortex->mmio, ((wt >> 0x5)<< 0xf) << 2); |
1352 |
|
if (en) |
1353 |
|
temp |= 1 << (wt & 0x1f); |
1354 |
|
else |
1355 |
|
temp &= 1 << ~(wt & 0x1f); |
1356 |
|
hwwrite(vortex->mmio, ((wt >> 0x5)<< 0xf) << 2, temp); |
1357 |
|
} |
1358 |
|
|
1359 |
|
void vortex_wt_writereg(vortex_t *vortex, u32 wt, u32 reg, u32 data) { |
1360 |
|
hwwrite(vortex->mmio, (((wt >> 0x5)<< 0xf) + reg) , data); |
1361 |
|
} |
1362 |
|
|
1363 |
|
u32 vortex_wt_readreg(vortex_t *vortex, u32 wt, u32 reg) { |
1364 |
|
return hwread(vortex->mmio, (((wt >> 0x5)<< 0xf) + reg)); |
1365 |
|
} |
1366 |
|
|
1367 |
/* ADB */ |
/* ADB */ |
1368 |
|
|
1369 |
typedef int ADBRamLink; |
typedef int ADBRamLink; |
1459 |
vortex_mixer_addWTD(vortex, (source - OFFSET_MIXOUT), channel); |
vortex_mixer_addWTD(vortex, (source - OFFSET_MIXOUT), channel); |
1460 |
} else { |
} else { |
1461 |
vortex_adb_delroutes(vortex, channel, route, route); |
vortex_adb_delroutes(vortex, channel, route, route); |
1462 |
if ((source < (OFFSET_SRCOUT+NR_ADB)) && (source >= OFFSET_SRCOUT)) |
if ((source < (OFFSET_SRCOUT+NR_SRC)) && (source >= OFFSET_SRCOUT)) |
1463 |
vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT), channel); |
vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT), channel); |
1464 |
else if ((source < (OFFSET_MIXOUT+NR_ADB)) && (source >= OFFSET_MIXOUT)) |
else if ((source < (OFFSET_MIXOUT+NR_MIXOUT)) && (source >= OFFSET_MIXOUT)) |
1465 |
vortex_mixer_delWTD(vortex, (source - OFFSET_MIXOUT), channel); |
vortex_mixer_delWTD(vortex, (source - OFFSET_MIXOUT), channel); |
1466 |
} |
} |
1467 |
} |
} |
1561 |
|
|
1562 |
ADBRamLink routes[2]; |
ADBRamLink routes[2]; |
1563 |
routes[0] = (((mix0 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK); |
routes[0] = (((mix0 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK); |
1564 |
routes[1] = (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma + OFFSET_MIXOUT) & ADB_MASK); |
routes[1] = (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma + 0x20 /*OFFSET_MIXOUT*/) & ADB_MASK); |
1565 |
if (en) { |
if (en) { |
1566 |
vortex_adb_addroutes(vortex, ch, routes, 0x2); |
vortex_adb_addroutes(vortex, ch, routes, 0x2); |
1567 |
vortex_mixer_addWTD(vortex, mix0, ch); |
vortex_mixer_addWTD(vortex, mix0, ch); |
1576 |
|
|
1577 |
void vortex_connection_src_adbdma(vortex_t *vortex, int en, unsigned char ch, |
void vortex_connection_src_adbdma(vortex_t *vortex, int en, unsigned char ch, |
1578 |
unsigned char src, unsigned char adbdma) { |
unsigned char src, unsigned char adbdma) { |
1579 |
vortex_route(vortex, en, ch, ADB_SRCIN(src), ADB_DMA(adbdma)); |
vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma)); |
1580 |
} |
} |
1581 |
|
|
1582 |
void vortex_connection_src_src_adbdma(vortex_t *vortex, int en, unsigned char ch, |
void vortex_connection_src_src_adbdma(vortex_t *vortex, int en, unsigned char ch, |
1709 |
if (dma->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
if (dma->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
1710 |
vortex_connection_src_mixin(vortex, en, 0x11, n+1, n+1); |
vortex_connection_src_mixin(vortex, en, 0x11, n+1, n+1); |
1711 |
vortex_connection_mixin_mix(vortex, en, n+1, MIX_OUTR, 0); |
vortex_connection_mixin_mix(vortex, en, n+1, MIX_OUTR, 0); |
1712 |
//vortex_connection_adbdma_src_src(vortex, en, n, adbdma, n, n+1); |
vortex_connection_adbdma_src_src(vortex, en, n, adbdma, n, n+1); |
|
vortex_connection_adbdma_src_src(vortex, en, n, adbdma, n+1, n); |
|
1713 |
if (en) |
if (en) |
1714 |
#ifdef CONFIG_SND_AU8820 |
#ifdef CONFIG_SND_AU8820 |
1715 |
vortex_src_setupchannel(vortex, n+1, SRC_RATIO(44100), 0, 0, n, 1, 0, 0, n); |
vortex_src_setupchannel(vortex, n+1, SRC_RATIO(44100), 0, 0, n, 1, 0, 0, n); |
1731 |
// WT routing is still a mistery. |
// WT routing is still a mistery. |
1732 |
int vortex_wt_waveroute(vortex_t *vortex, int wtdma, int nr_ch) { |
int vortex_wt_waveroute(vortex_t *vortex, int wtdma, int nr_ch) { |
1733 |
//FIXME: WT audio routing. |
//FIXME: WT audio routing. |
1734 |
if (nr_ch) |
if (nr_ch) { |
1735 |
vortex_fifo_wtinitialize(vortex, wtdma, 1); |
vortex_fifo_wtinitialize(vortex, wtdma, 1); |
1736 |
else |
vortex_wt_setstereo(vortex, wtdma, nr_ch-1); |
1737 |
|
} else |
1738 |
vortex_fifo_setwtvalid(vortex, wtdma, 0); |
vortex_fifo_setwtvalid(vortex, wtdma, 0); |
1739 |
return 0; |
return 0; |
1740 |
} |
} |
1774 |
// This is the Interrrupt Enable flag we set before (consistency check). |
// This is the Interrrupt Enable flag we set before (consistency check). |
1775 |
if (!((hwread(vortex->mmio, VORTEX_CTRL) & 0x0000ff00) != CTRL_IRQ_ENABLE)) |
if (!((hwread(vortex->mmio, VORTEX_CTRL) & 0x0000ff00) != CTRL_IRQ_ENABLE)) |
1776 |
return; |
return; |
|
// Is at least one IRQ flag set? |
|
1777 |
source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE); |
source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE); |
1778 |
// Reset IRQ flags |
// Reset IRQ flags. |
1779 |
hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source & 0xffffffff); |
hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source & 0xffffffff); |
1780 |
hwread(vortex->mmio, VORTEX_IRQ_SOURCE); |
hwread(vortex->mmio, VORTEX_IRQ_SOURCE); |
1781 |
|
// Is at least one IRQ flag set? |
1782 |
if (source == 0) |
if (source == 0) |
1783 |
return; |
return; |
1784 |
//printk("IRQ: 0x%x\n", source); |
//printk("IRQ: 0x%x\n", source); |
1785 |
|
|
1786 |
// Attend every interrupt source. |
// Attend every interrupt source. |
1787 |
if (source & IRQ_FATAL) |
if (source & IRQ_FATAL) |
1788 |
printk(KERN_ERR "vortex: IRQ fatal error\n"); |
printk(KERN_ERR "vortex: IRQ fatal error\n"); |
1789 |
if (source & IRQ_PARITY) |
if (source & IRQ_PARITY) |
1790 |
printk(KERN_ERR "vortex: IRQ parity error\n"); |
printk(KERN_ERR "vortex: IRQ parity error\n"); |
1791 |
if (source & IRQ_PCMOUT) { |
if (source & IRQ_PCMOUT) { |
1910 |
|
|
1911 |
/* Initialization */ |
/* Initialization */ |
1912 |
|
|
|
//static int vortex_core_is_up = 0; |
|
1913 |
int vortex_core_init(vortex_t *vortex) { |
int vortex_core_init(vortex_t *vortex) { |
|
//if (vortex_core_is_up == 1) |
|
|
// return -ENODEV; |
|
1914 |
|
|
1915 |
printk("Vortex: hardware init.... "); |
printk("Vortex: hardware init.... "); |
1916 |
/* Hardware Init. */ |
/* Hardware Init. */ |
1944 |
//vortex_disable_timer_int(vortex); |
//vortex_disable_timer_int(vortex); |
1945 |
|
|
1946 |
printk("done.\n"); |
printk("done.\n"); |
|
//vortex_core_is_up = 1; |
|
1947 |
spin_lock_init(&vortex->lock); |
spin_lock_init(&vortex->lock); |
1948 |
|
|
1949 |
return 0; |
return 0; |
1950 |
} |
} |
1951 |
|
|
1952 |
int vortex_core_shutdown(vortex_t *vortex) { |
int vortex_core_shutdown(vortex_t *vortex) { |
|
//if (vortex_core_is_up == 0) |
|
|
// return -ENODEV; |
|
1953 |
|
|
1954 |
printk("Vortex: hardware shutdown..."); |
printk("Vortex: hardware shutdown..."); |
1955 |
|
|
1971 |
hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0); |
hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0); |
1972 |
|
|
1973 |
printk("done.\n"); |
printk("done.\n"); |
|
//vortex_core_is_up = 0; |
|
1974 |
return 0; |
return 0; |
1975 |
} |
} |
1976 |
|
|