658 |
vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE); |
vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE); |
659 |
addr -= 4; |
addr -= 4; |
660 |
} |
} |
661 |
|
|
662 |
|
#ifndef CHIP_AU8810 |
663 |
/* WT DMA channels fifos. */ |
/* WT DMA channels fifos. */ |
664 |
addr = VORTEX_FIFO_WTCTRL + ((NR_WT-1)*4); |
addr = VORTEX_FIFO_WTCTRL + ((NR_WT-1)*4); |
665 |
for (x = NR_WT-1; x >= 0; x--) { |
for (x = NR_WT-1; x >= 0; x--) { |
669 |
vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE); |
vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE); |
670 |
addr -= 4; |
addr -= 4; |
671 |
} |
} |
672 |
|
#endif |
673 |
|
/* below is weird stuff... */ |
674 |
#ifndef CHIP_AU8820 |
#ifndef CHIP_AU8820 |
675 |
hwwrite(vortex->mmio, 0xf8c0, 0xd03); //0x0843 0xd6b |
hwwrite(vortex->mmio, 0xf8c0, 0xd03); //0x0843 0xd6b |
676 |
#else |
#else |