/[openvortex]/alsa/pci/au88x0/au88x0_core.c
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Diff of /alsa/pci/au88x0/au88x0_core.c

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revision 1.12 by mjander, Sat May 24 03:16:46 2003 UTC revision 1.13 by mjander, Sat May 24 18:25:32 2003 UTC
# Line 696  void vortex_fifo_setadbctrl(vortex_t *vo Line 696  void vortex_fifo_setadbctrl(vortex_t *vo
696      int temp, lifeboat=0;      int temp, lifeboat=0;
697      //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */      //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */
698          int     this_4=0x2;          int     this_4=0x2;
699            /* f seems priority related.
700             * CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1
701             * every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority
702             * is never called, thus the f related bits remain a mystery for now.
703             */
704      do {      do {
705                  temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));                  temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
706                  if (lifeboat++ > 0xff) {                  if (lifeboat++ > 0xff) {
# Line 723  void vortex_fifo_setadbctrl(vortex_t *vo Line 727  void vortex_fifo_setadbctrl(vortex_t *vo
727                          temp = (temp & 0xffffffdf) | ((empty & 1) << 5);                          temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
728  #ifdef CHIP_AU8820  #ifdef CHIP_AU8820
729                          temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);                          temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
730  #else  #endif
731    #ifdef CHIP_AU8830
732                          temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);                          temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
733                          temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);                          temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
734  #endif  #endif
735    #ifdef CHIP_AU8810
736                            temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
737                            temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
738    #endif
739                  }                  }
740      } else {      } else {
741                  if (temp & FIFO_VALID) {                  if (temp & FIFO_VALID) {
742  #ifdef CHIP_AU8820  #ifdef CHIP_AU8820
743                          temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);                          temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
 #else  
                         temp = (temp & 0xf7ffffef) | ((f & 1) << 0x1b);  
                         //temp = ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;  
744  #endif  #endif
745    #ifdef CHIP_AU8830
746                            temp = ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
747    #endif
748    #ifdef CHIP_AU8810
749                            temp = ((f & 1) << 0x1b) | (temp & 0xfcffffef) | FIFO_BITS;
750    #endif                  
751                  } else                  } else
752                          /*if (this_8[fifo])*/ vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);                          /*if (this_8[fifo])*/ vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
753          }          }

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