129 |
#define VORTEX_SRC_DRIFT1 0x26ec0 |
#define VORTEX_SRC_DRIFT1 0x26ec0 |
130 |
#define VORTEX_SRC_DRIFT2 0x26f40 |
#define VORTEX_SRC_DRIFT2 0x26f40 |
131 |
#define VORTEX_SRC_U0 0x26e00 |
#define VORTEX_SRC_U0 0x26e00 |
132 |
|
#define U0_SLOWLOCK 0x200 |
133 |
#define VORTEX_SRC_U1 0x26f00 |
#define VORTEX_SRC_U1 0x26f00 |
134 |
#define VORTEX_SRC_U3 0x26f80 |
#define VORTEX_SRC_U3 0x26f80 |
135 |
#define VORTEX_SRC_DATA 0x26800 /* 0xc800 */ |
#define VORTEX_SRC_DATA 0x26800 /* 0xc800 */ |
144 |
#define FIFO_EMPTY 0x00000020 |
#define FIFO_EMPTY 0x00000020 |
145 |
#define FIFO_U0 0x00002000 /* Unknown. */ |
#define FIFO_U0 0x00002000 /* Unknown. */ |
146 |
#define FIFO_U1 0x00040000 |
#define FIFO_U1 0x00040000 |
147 |
#define FIFO_MASK 0x3f /* at shift left 0xc */ |
#define FIFO_SIZE_BITS 6 |
148 |
#define FIFO_SIZE 0x40 |
#define FIFO_SIZE (1<<(FIFO_SIZE_BITS)) // 0x40 |
149 |
|
#define FIFO_MASK (FIFO_SIZE-1) //0x3f /* at shift left 0xc */ |
150 |
|
//#define FIFO_MASK 0x3f /* at shift left 0xc */ |
151 |
|
//#define FIFO_SIZE 0x40 |
152 |
#define FIFO_BITS 0x1c400000 |
#define FIFO_BITS 0x1c400000 |
153 |
#define VORTEX_FIFO_ADBDATA 0x14000 |
#define VORTEX_FIFO_ADBDATA 0x14000 |
154 |
#define VORTEX_FIFO_WTDATA 0x10000 |
#define VORTEX_FIFO_WTDATA 0x10000 |