/[openvortex]/alsa/pci/au88x0/au8830.h
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Diff of /alsa/pci/au88x0/au8830.h

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revision 1.12 by mjander, Thu Aug 7 01:58:51 2003 UTC revision 1.13 by vizard, Sun Aug 10 20:00:33 2003 UTC
# Line 1  Line 1 
1  #define __NO_VERSION__  /*
2  #include "../../alsa-kernel/pci/au88x0/au8830.h"      Aureal Vortex Soundcard driver.
3    
4        IO addr collected from asp4core.vxd:
5        function    address
6        0005D5A0    13004
7        00080674    14004
8        00080AFF    12818
9    
10     */
11    
12    #define CHIP_AU8830
13    
14    #define CARD_NAME "Aureal Vortex 2 3D Sound Processor"
15    #define CARD_NAME_SHORT "au8830"
16    
17    #ifndef PCI_VENDOR_ID_AUREAL
18    #define PCI_VENDOR_ID_AUREAL 0x12eb
19    #endif
20    #ifndef PCI_VENDOR_ID_AUREAL_VORTEX2
21    #define PCI_DEVICE_ID_AUREAL_VORTEX2 0x0002
22    #endif
23    
24    #define hwread(x,y) readl((x)+((y)>>2))
25    #define hwwrite(x,y,z) writel((z),(x)+((y)>>2))
26    
27    #define NR_ADB 0x20
28    #define NR_SRC 0x10
29    #define NR_A3D 0x10
30    #define NR_MIXIN 0x20
31    #define NR_MIXOUT 0x10
32    #define NR_WT 0x40
33    
34    /* ADBDMA */
35    #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
36    #define         POS_MASK 0x00000fff
37    #define     POS_SHIFT 0x0
38    #define         ADB_SUBBUF_MASK 0x00003000  /* ADB only. */
39    #define     ADB_SUBBUF_SHIFT 0xc        /* ADB only. */
40    #define VORTEX_ADBDMA_CTRL 0x27a00              /* write only; format, flags, DMA pos */
41    #define         OFFSET_MASK 0x00000fff
42    #define     OFFSET_SHIFT 0x0
43    #define         IE_MASK 0x00001000 /* interrupt enable. */
44    #define     IE_SHIFT 0xc
45    #define     U_MASK 0x00002000  /* Unknown. If you know, tell me. */
46    #define     U_SHIFT 0xd
47    #define         FMT_MASK 0x0003c000
48    #define         FMT_SHIFT 0xe
49    #define         ADB_FIFO_EN_SHIFT       0x15
50    #define         ADB_FIFO_EN                     (1 << 0x15)
51    // The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
52    #define VORTEX_ADBDMA_BUFCFG0 0x27800
53    #define VORTEX_ADBDMA_BUFCFG1 0x27804
54    #define VORTEX_ADBDMA_BUFBASE 0x27400
55    #define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */
56    
57    /* WTDMA */
58    #define VORTEX_WTDMA_CTRL 0x27900 /* format, DMA pos */
59    #define VORTEX_WTDMA_STAT 0x27d00 /* DMA subbuf, DMA pos */
60    #define     WT_SUBBUF_MASK 0x3
61    #define     WT_SUBBUF_SHIFT 0xc
62    #define VORTEX_WTDMA_BUFBASE 0x27000
63    #define VORTEX_WTDMA_BUFCFG0 0x27600
64    #define VORTEX_WTDMA_BUFCFG1 0x27604
65    #define VORTEX_WTDMA_START 0x27b00 /* which subbuffer is first */
66    
67    /* ADB */
68    #define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */
69    #define VORTEX_ADB_RTBASE 0x28000
70    #define VORTEX_ADB_RTBASE_SIZE (VORTEX_ADB_CHNBASE - VORTEX_ADB_RTBASE)
71    #define VORTEX_ADB_CHNBASE 0x282b4
72    #define VORTEX_ADB_CHNBASE_SIZE (ADB_MASK - VORTEX_ADB_RTBASE_SIZE)
73    #define         ROUTE_MASK      0xffff
74    #define         SOURCE_MASK     0xff00
75    #define     ADB_MASK   0xff
76    #define         ADB_SHIFT 0x8
77    /* ADB address */
78    #define         OFFSET_ADBDMA   0x00
79    #define         OFFSET_SRCIN    0x40
80    #define         OFFSET_SRCOUT   0x20
81    #define         OFFSET_MIXIN    0x50
82    #define         OFFSET_MIXOUT   0x30
83    #define         OFFSET_CODECIN  0x70 /* adb source */
84    #define         OFFSET_CODECOUT 0x88 /* adb target */
85    #define         OFFSET_SPORTIN  0x78 /* ch 0x13 */
86    #define         OFFSET_SPORTOUT 0x90
87    #define         OFFSET_EQIN             0xa0
88    #define         OFFSET_EQOUT    0x7e /* 2 routes on ch 0x11 */
89    #define         OFFSET_WTOUT    0xa2
90    
91    /* ADB route translate helper */
92    #define ADB_DMA(x) (x)
93    #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
94    #define ADB_SRCIN(x) (x + OFFSET_SRCIN)
95    #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
96    #define ADB_MIXIN(x) (x + OFFSET_MIXIN)
97    #define ADB_CODECIN(x) (x + OFFSET_CODECIN)
98    #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
99    #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
100    #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
101    #define ADB_EQIN(x) (x + OFFSET_EQIN)
102    #define ADB_EQOUT(x) (x + OFFSET_EQOUT)
103    #define ADB_A3DOUT(x) (x + 0x50) /* 0x10 A3D blocks */
104    #define ADB_A3DIN(x) (x + 0x70)
105    
106    #define MIX_OUTL    0xe
107    #define MIX_OUTR    0xf
108    #define MIX_INL     0x1e
109    #define MIX_INR     0x1f
110    #define MIX_DEFIGAIN 0x00
111    #define MIX_DEFOGAIN 0x00 /* 0x8->6dB  (6dB = x4) 16 to 18 bit conversion? */
112    
113    /* MIXER */
114    #define VORTEX_MIXER_SR 0x21f00
115    #define VORTEX_MIXER_CHNBASE 0x21e40
116    #define VORTEX_MIXER_RTBASE 0x21e00
117    #define         MIXER_RTBASE_SIZE 0x38
118    #define VORTEX_MIX_U0 0x21c00 /* AU8820: 0x9c00 */
119    
120    /* MIX */
121    #define VORTEX_MIX_INVOL_A 0x21000 /* in? */
122    #define VORTEX_MIX_INVOL_B 0x20000 /* out? */
123    #define VORTEX_MIX_VOL_A 0x21800
124    #define VORTEX_MIX_VOL_B 0x20800
125    #define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */
126    #define         VOL_MIN 0x80 /* Input volume when muted. */
127    #define         VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
128    
129    /* SRC */
130    #define VORTEX_SRCBLOCK_SR      0x26cc0
131    #define VORTEX_SRC_CHNBASE      0x26c40
132    #define VORTEX_SRC_RTBASE       0x26c00
133    #define VORTEX_SRC_SOURCE       0x26cc4
134    #define VORTEX_SRC_CONVRATIO 0x26e40
135    #define VORTEX_SRC_DRIFT0       0x26e80
136    #define VORTEX_SRC_DRIFT1       0x26ec0
137    #define VORTEX_SRC_DRIFT2       0x26f40
138    #define VORTEX_SRC_U0           0x26e00
139    #define         U0_SLOWLOCK             0x200
140    #define VORTEX_SRC_U1           0x26f00
141    #define VORTEX_SRC_U3           0x26f80
142    #define VORTEX_SRC_DATA         0x26800 /* 0xc800 */
143    #define VORTEX_SRC_DATA0        0x26000
144    
145    /* FIFO */
146    #define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */
147    #define VORTEX_FIFO_WTCTRL 0x16000
148    #define         FIFO_RDONLY     0x00000001
149    #define         FIFO_CTRL       0x00000002 /* Allow ctrl. ? */
150    #define         FIFO_VALID      0x00000010
151    #define         FIFO_EMPTY      0x00000020
152    #define         FIFO_U0         0x00002000 /* Unknown. */
153    #define         FIFO_U1         0x00040000
154    #define         FIFO_SIZE_BITS 6
155    #define         FIFO_SIZE       (1<<(FIFO_SIZE_BITS)) // 0x40
156    #define         FIFO_MASK       (FIFO_SIZE-1) //0x3f    /* at shift left 0xc */
157    //#define       FIFO_MASK       0x3f    /* at shift left 0xc */
158    //#define               FIFO_SIZE       0x40
159    #define         FIFO_BITS       0x1c400000
160    #define VORTEX_FIFO_ADBDATA 0x14000
161    #define VORTEX_FIFO_WTDATA 0x10000
162    
163    /* CODEC */
164    #define VORTEX_CODEC_CTRL 0x29184
165    #define VORTEX_CODEC_EN 0x29190
166    #define         EN_CODEC        0x00000300
167    #define         EN_CODEC2       0x00003000
168    #define         EN_SPORT        0x00030000
169    #define         EN_SPDIF        0x000c0000
170    #define VORTEX_CODEC_CHN 0x29080
171    #define VORTEX_CODEC_WRITE 0x00800000
172    #define VORTEX_CODEC_ADDSHIFT 16
173    #define VORTEX_CODEC_ADDMASK 0x7f0000 /* 0x000f0000*/
174    #define VORTEX_CODEC_DATSHIFT 0
175    #define VORTEX_CODEC_DATMASK 0xffff
176    #define VORTEX_CODEC_IO 0x29188
177    
178    /* Sample timer */
179    #define VORTEX_SMP_TIME  0x29198
180    
181    /* IRQ */
182    #define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */
183    #define         IRQ_FATAL    0x0001
184    #define         IRQ_PARITY   0x0002
185    #define         IRQ_PCMOUT   0x0020 /* ?? */
186    #define         IRQ_TIMER    0x1000
187    #define         IRQ_MIDI     0x2000
188    #define         IRQ_MODEM       0x4000
189    
190    #define VORTEX_IRQ_U0   0x2a008 /* ?? */
191    
192    #define VORTEX_CTRL             0x2a00c
193    #define         CTRL_MIDI_EN    0x00000001
194    #define         CTRL_MIDI_PORT  0x00000060
195    #define         CTRL_GAME_EN    0x00000008
196    #define         CTRL_GAME_PORT  0x00000e00
197    #define         CTRL_SPORT              0x00200000
198    #define         CTRL_UNKNOWN    0x01000000
199    #define         CTRL_IRQ_ENABLE 0x00004000
200    
201    #define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */
202    #define         IRQ_FATAL       0x0001
203    #define         IRQ_PARITY      0x0002
204    #define         IRQ_PCMOUT      0x0020 /* PCM OUT page crossing */
205    #define         IRQ_TIMER       0x1000
206    #define         IRQ_MIDI        0x2000
207    #define         IRQ_MODEM       0x4000
208    
209    /* write: Timer period config / read: TIMER IRQ ack. */
210    #define VORTEX_IRQ_STAT 0x2919c
211    
212    /* DMA */
213    #define VORTEX_ENGINE_CTRL 0x27ae8
214    #define         ENGINE_INIT 0x1380000
215    
216    /* MIDI */ /* GAME. */
217    #define VORTEX_MIDI_DATA 0x28800
218    #define VORTEX_MIDI_CMD 0x28804  /* Write command / Read status */
219    
220    #define VORTEX_CTRL2 0x2880c
221    #define         CTRL2_GAME_ADCMODE 0x40
222    #define VORTEX_GAME_LEGACY 0x28808
223    #define VORTEX_GAME_AXIS 0x28810
224    #define         AXIS_SIZE 4
225    #define         AXIS_RANGE 0x1fff

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