68 |
#define OFFSET_SRCIN 0x10 /* on channel 0x00 */ |
#define OFFSET_SRCIN 0x10 /* on channel 0x00 */ |
69 |
#define OFFSET_MIXOUT 0x20 |
#define OFFSET_MIXOUT 0x20 |
70 |
#define OFFSET_MIXIN 0x30 |
#define OFFSET_MIXIN 0x30 |
71 |
|
#define OFFSET_CODECIN 0x48 |
72 |
|
#define OFFSET_CODECOUT 0x58 |
73 |
|
#define OFFSET_SPORTOUT 0x60 |
74 |
|
#define OFFSET_SPORTIN 0x78 |
75 |
|
#define OFFSET_A3DOUT 0x50 |
76 |
|
#define OFFSET_A3DIN 0x70 |
77 |
|
|
78 |
|
/* ADB route translate helper */ |
79 |
|
#define ADB_DMA(x) (x + OFFSET_ADBDMA) |
80 |
|
#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) |
81 |
|
#define ADB_SRCIN(x) (x + OFFSET_SRCIN) |
82 |
|
#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) |
83 |
|
#define ADB_MIXIN(x) (x + OFFSET_MIXIN) |
84 |
|
#define ADB_CODECIN(x) (x + OFFSET_CODECIN) |
85 |
|
#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) |
86 |
|
#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) |
87 |
|
#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* 0x72 ? */ |
88 |
|
#define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */ |
89 |
|
#define ADB_A3DIN(x) (x + OFFSET_A3DIN) |
90 |
|
|
91 |
/* WTDMA */ |
/* WTDMA */ |
92 |
#define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */ |
#define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */ |
114 |
#define VOL_MIN 0x80 /* Input volume when muted. */ |
#define VOL_MIN 0x80 /* Input volume when muted. */ |
115 |
#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ |
#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ |
116 |
|
|
117 |
|
#define MIX_OUTL 0xe |
118 |
|
#define MIX_OUTR 0xf |
119 |
|
#define MIX_INL 0xe |
120 |
|
#define MIX_INR 0xf |
121 |
|
#define MIX_DEFIGAIN 0x00 /* 0x8 => 6dB */ |
122 |
|
#define MIX_DEFOGAIN 0x00 |
123 |
|
|
124 |
/* SRC */ |
/* SRC */ |
125 |
#define VORTEX_SRCBLOCK_SR 0xccc0 |
#define VORTEX_SRCBLOCK_SR 0xccc0 |
126 |
#define VORTEX_SRC_CHNBASE 0xcc40 |
#define VORTEX_SRC_CHNBASE 0xcc40 |
138 |
//#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */ |
//#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */ |
139 |
//#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */ |
//#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */ |
140 |
|
|
|
/* ADB route translate helper */ |
|
|
#define ADB_DMA(x) (x) |
|
|
#define ADB_SRCOUT(x) (x + 0x10) |
|
|
#define ADB_SRCIN(x) (x + 0x10) |
|
|
#define ADB_MIXOUT(x) (x + 0x20) |
|
|
#define ADB_MIXIN(x) (x + 0x30) |
|
|
#define ADB_CODECIN(x) (x + 0x48) |
|
|
#define ADB_CODECOUT(x) (x + 0x58) |
|
|
#define ADB_SPORTOUT(x) (x + 0x60) |
|
|
#define ADB_SPORTIN(x) (x + 0x78) /* 0x72 ? */ |
|
|
#define ADB_A3DOUT(x) (x + 0x50) /* 8 A3D blocks */ |
|
|
#define ADB_A3DIN(x) (x + 0x70) |
|
|
|
|
|
#define MIX_OUTL 0xe |
|
|
#define MIX_OUTR 0xf |
|
|
#define MIX_INL 0xe |
|
|
#define MIX_INR 0xf |
|
141 |
|
|
142 |
/* FIFO */ |
/* FIFO */ |
143 |
#define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */ |
#define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */ |