24 |
#define PCI_DEVICE_ID_AUREAL_VORTEX 0x0001 |
#define PCI_DEVICE_ID_AUREAL_VORTEX 0x0001 |
25 |
#endif |
#endif |
26 |
|
|
|
|
|
27 |
/* Number of ADB and WT channels */ |
/* Number of ADB and WT channels */ |
28 |
#define NR_ADB 0x10 |
#define NR_ADB 0x10 |
29 |
#define NR_WT 0x20 |
#define NR_WT 0x20 |
54 |
#define VORTEX_ADBDMA_BUFBASE 0x10200 |
#define VORTEX_ADBDMA_BUFBASE 0x10200 |
55 |
#define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */ |
#define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */ |
56 |
|
|
|
|
|
57 |
/* ADB */ |
/* ADB */ |
58 |
#define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */ |
#define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */ |
59 |
#define VORTEX_ADB_RTBASE 0x10800 |
#define VORTEX_ADB_RTBASE 0x10800 |
71 |
#define OFFSET_MIXOUT 0x20 |
#define OFFSET_MIXOUT 0x20 |
72 |
#define OFFSET_MIXIN 0x30 |
#define OFFSET_MIXIN 0x30 |
73 |
|
|
|
|
|
74 |
/* WTDMA */ |
/* WTDMA */ |
75 |
#define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */ |
#define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */ |
76 |
#define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */ |
#define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */ |
81 |
#define VORTEX_WTDMA_BUFCFG1 0x10304 |
#define VORTEX_WTDMA_BUFCFG1 0x10304 |
82 |
#define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */ |
#define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */ |
83 |
|
|
|
|
|
84 |
/* MIXER */ |
/* MIXER */ |
85 |
#define VORTEX_MIXER_SR 0x9f00 |
#define VORTEX_MIXER_SR 0x9f00 |
86 |
#define VORTEX_MIXER_CHNBASE 0x9e40 |
#define VORTEX_MIXER_CHNBASE 0x9e40 |
132 |
#define MIX_INL 0xe |
#define MIX_INL 0xe |
133 |
#define MIX_INR 0xf |
#define MIX_INR 0xf |
134 |
|
|
|
|
|
135 |
/* FIFO */ |
/* FIFO */ |
136 |
#define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */ |
#define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */ |
137 |
#define VORTEX_FIFO_WTCTRL 0xf840 |
#define VORTEX_FIFO_WTCTRL 0xf840 |
171 |
#define IRQ_FATAL 0x0001 |
#define IRQ_FATAL 0x0001 |
172 |
#define IRQ_PARITY 0x0002 |
#define IRQ_PARITY 0x0002 |
173 |
#define IRQ_PCMOUT 0x0020 /* ?? */ |
#define IRQ_PCMOUT 0x0020 /* ?? */ |
174 |
#define IRQ_TIMER 0x1000 |
#define IRQ_TIMER 0x1000 |
175 |
#define IRQ_MIDI 0x2000 |
#define IRQ_MIDI 0x2000 |
176 |
|
|
177 |
#define VORTEX_IRQ_U0 0x12808 /* ?? */ |
#define VORTEX_IRQ_U0 0x12808 /* ?? */ |
187 |
#define IRQ_FATAL 0x0001 |
#define IRQ_FATAL 0x0001 |
188 |
#define IRQ_PARITY 0x0002 |
#define IRQ_PARITY 0x0002 |
189 |
#define IRQ_PCMOUT 0x0020 /* PCM OUT page crossing */ |
#define IRQ_PCMOUT 0x0020 /* PCM OUT page crossing */ |
190 |
#define IRQ_TIMER 0x1000 |
#define IRQ_TIMER 0x1000 |
191 |
#define IRQ_MIDI 0x2000 |
#define IRQ_MIDI 0x2000 |
192 |
|
|
193 |
/* write: Timer period config / read: TIMER IRQ ack. */ |
/* write: Timer period config / read: TIMER IRQ ack. */ |
194 |
#define VORTEX_IRQ_STAT 0x1199c |
#define VORTEX_IRQ_STAT 0x1199c |
195 |
|
|
196 |
/* DMA */ |
/* DMA */ |
197 |
#define VORTEX_DMA_BUFFER 0x10200 |
#define VORTEX_DMA_BUFFER 0x10200 |