/[openvortex]/alsa/pci/au88x0/au8820.h
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Diff of /alsa/pci/au88x0/au8820.h

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revision 1.12 by mjander, Thu Aug 7 01:58:50 2003 UTC revision 1.13 by vizard, Sun Aug 10 20:00:33 2003 UTC
# Line 1  Line 1 
1  #define __NO_VERSION__  /*
2  #include "../../alsa-kernel/pci/au88x0/au8820.h"      Aureal Vortex Soundcard driver.
3    
4        IO addr collected from asp4core.vxd:
5        function    address
6        0005D5A0    13004
7        00080674    14004
8        00080AFF    12818
9    
10     */
11    
12    #define CHIP_AU8820
13    
14    #define CARD_NAME "Aureal Vortex 3D Sound Processor"
15    #define CARD_NAME_SHORT "au8820"
16    
17    #ifndef PCI_VENDOR_ID_AUREAL
18    #define PCI_VENDOR_ID_AUREAL 0x12eb
19    #endif
20    
21    #ifndef PCI_VENDOR_ID_AUREAL_VORTEX
22    #define PCI_DEVICE_ID_AUREAL_VORTEX 0x0001
23    #endif
24    
25    /* Number of ADB and WT channels */
26    #define NR_ADB 0x10
27    #define NR_WT 0x20
28    #define NR_SRC 0x10
29    #define NR_A3D 0x8
30    #define NR_MIXIN 0x10
31    #define NR_MIXOUT 0x10
32    #define NR_WT 0x20
33    
34    /* ADBDMA */
35    #define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */
36    #define         POS_MASK 0x00000fff
37    #define     POS_SHIFT 0x0
38    #define         ADB_SUBBUF_MASK 0x00003000  /* ADB only. */
39    #define     ADB_SUBBUF_SHIFT 0xc        /* ADB only. */
40    #define VORTEX_ADBDMA_CTRL 0x10580  /* write only, format, flags, DMA pos */
41    #define         OFFSET_MASK 0x00000fff
42    #define     OFFSET_SHIFT 0x0
43    #define         IE_MASK 0x00001000 /* interrupt enable. */
44    #define     IE_SHIFT 0xc
45    #define     U_MASK 0x00002000  /* Unknown. If you know tell me. */
46    #define     U_SHIFT 0xd
47    #define         FMT_MASK 0x0003c000
48    #define         FMT_SHIFT 0xe
49    // The masks and shift also work for the wtdma, if not specified otherwise.
50    #define VORTEX_ADBDMA_BUFCFG0 0x10400
51    #define VORTEX_ADBDMA_BUFCFG1 0x10404
52    #define VORTEX_ADBDMA_BUFBASE 0x10200
53    #define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */
54    
55    /* ADB */
56    #define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */
57    #define VORTEX_ADB_RTBASE 0x10800
58    #define VORTEX_ADB_RTBASE_SIZE (VORTEX_ADB_CHNBASE - VORTEX_ADB_RTBASE)
59    #define VORTEX_ADB_CHNBASE 0x1099c
60    #define VORTEX_ADB_CHNBASE_SIZE (ADB_MASK - VORTEX_ADB_RTBASE_SIZE)
61    #define         ROUTE_MASK      0x3fff
62    #define     ADB_MASK   0x7f
63    #define         ADB_SHIFT 0x7
64    //#define     ADB_MIX_MASK 0xf
65    /* ADB address */
66    #define         OFFSET_ADBDMA   0x00
67    #define         OFFSET_SRCOUT   0x10  /* on channel 0x11 */
68    #define         OFFSET_SRCIN    0x10  /* on channel < 0x11 */
69    #define         OFFSET_MIXOUT   0x20
70    #define         OFFSET_MIXIN    0x30
71    #define         OFFSET_CODECIN  0x48 /* ADB source */
72    #define         OFFSET_CODECOUT 0x58 /* ADB sink/target */
73    #define         OFFSET_SPORTOUT 0x60
74    #define         OFFSET_SPORTIN  0x78
75    #define         OFFSET_A3DOUT   0x50
76    #define         OFFSET_A3DIN    0x70
77    #define         OFFSET_WTOUT    0x00 /* FIXME */
78    
79    /* ADB route translate helper */
80    #define ADB_DMA(x) (x + OFFSET_ADBDMA)
81    #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
82    #define ADB_SRCIN(x) (x + OFFSET_SRCIN)
83    #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
84    #define ADB_MIXIN(x) (x + OFFSET_MIXIN)
85    #define ADB_CODECIN(x) (x + OFFSET_CODECIN)
86    #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
87    #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
88    #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* 0x72 ? */
89    #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */
90    #define ADB_A3DIN(x) (x + OFFSET_A3DIN)
91    #define ADB_WTOUT(x) (x + OFFSET_WTOUT)
92    
93    /* WTDMA */
94    #define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */
95    #define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */
96    #define     WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT)
97    #define     WT_SUBBUF_SHIFT 0x15
98    #define VORTEX_WTDMA_BUFBASE 0x10000
99    #define VORTEX_WTDMA_BUFCFG0 0x10300
100    #define VORTEX_WTDMA_BUFCFG1 0x10304
101    #define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */
102    
103    /* MIXER */
104    #define VORTEX_MIXER_SR 0x9f00
105    #define VORTEX_MIXER_CHNBASE 0x9e40
106    #define VORTEX_MIXER_RTBASE 0x9e00
107    #define         MIXER_RTBASE_SIZE 0x26
108    #define VORTEX_MIX_U0 0x9c00
109    
110    /* MIX */
111    #define VORTEX_MIX_INVOL_A 0x9000 /* in? */
112    #define VORTEX_MIX_INVOL_B 0x8000 /* out? */
113    #define VORTEX_MIX_VOL_A 0x9800
114    #define VORTEX_MIX_VOL_B 0x8800
115    #define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */
116    #define         VOL_MIN 0x80 /* Input volume when muted. */
117    #define         VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
118    
119    #define MIX_OUTL    0xe
120    #define MIX_OUTR    0xf
121    #define MIX_INL     0xe
122    #define MIX_INR     0xf
123    #define MIX_DEFIGAIN 0x00 /* 0x8 => 6dB */
124    #define MIX_DEFOGAIN 0x00
125    
126    /* SRC */
127    #define VORTEX_SRCBLOCK_SR      0xccc0
128    #define VORTEX_SRC_CHNBASE      0xcc40
129    #define VORTEX_SRC_RTBASE       0xcc00
130    #define VORTEX_SRC_SOURCE       0xccc4
131    #define VORTEX_SRC_U0           0xce00
132    #define VORTEX_SRC_DRIFT0       0xce80
133    #define VORTEX_SRC_DRIFT1       0xcec0
134    #define VORTEX_SRC_U1           0xcf00
135    #define VORTEX_SRC_DRIFT2       0xcf40
136    #define VORTEX_SRC_U3           0xcf80
137    #define VORTEX_SRC_DATA         0xc800
138    #define VORTEX_SRC_DATA0        0xc000
139    #define VORTEX_SRC_CONVRATIO 0xce40
140    //#define     SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */
141    //#define     SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */
142    
143    
144    /* FIFO */
145    #define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */
146    #define VORTEX_FIFO_WTCTRL 0xf840
147    #define         FIFO_RDONLY     0x00000001
148    #define         FIFO_CTRL       0x00000002 /* Allow ctrl. ? */
149    #define         FIFO_VALID      0x00000010
150    #define         FIFO_EMPTY      0x00000020
151    #define         FIFO_U0         0x00001000 /* Unknown. */
152    #define         FIFO_U1         0x00010000
153    #define         FIFO_SIZE_BITS 5
154    #define         FIFO_SIZE       (1<<FIFO_SIZE_BITS) // 0x20
155    #define         FIFO_MASK       (FIFO_SIZE-1) //0x1f    /* at shift left 0xc */
156    #define VORTEX_FIFO_ADBDATA 0xe000
157    #define VORTEX_FIFO_WTDATA 0xe800
158    
159    /* CODEC */
160    #define VORTEX_CODEC_CTRL 0x11984
161    #define VORTEX_CODEC_EN 0x11990
162    #define         EN_CODEC        0x00000300
163    #define         EN_SPORT        0x00030000
164    #define         EN_SPDIF        0x000c0000
165    #define VORTEX_CODEC_CHN 0x11880
166    #define VORTEX_CODEC_WRITE 0x00800000
167    #define VORTEX_CODEC_ADDSHIFT 16
168    #define VORTEX_CODEC_ADDMASK 0x7f0000 /* 0x000f0000*/
169    #define VORTEX_CODEC_DATSHIFT 0
170    #define VORTEX_CODEC_DATMASK 0xffff
171    #define VORTEX_CODEC_IO 0x11988
172    
173    /* Sample timer */
174    #define VORTEX_SMP_TIME 0x11998
175    
176    /* IRQ */
177    #define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */
178    #define         IRQ_FATAL    0x0001
179    #define         IRQ_PARITY   0x0002
180    #define         IRQ_PCMOUT   0x0020 /* ?? */
181    #define         IRQ_TIMER    0x1000
182    #define         IRQ_MIDI     0x2000
183    
184    #define VORTEX_IRQ_U0   0x12808 /* ?? */
185    
186    #define VORTEX_CTRL 0x1280c
187    #define         CTRL_MIDI_EN 0x00000001
188    #define         CTRL_MIDI_PORT 0x00000060
189    #define         CTRL_GAME_EN 0x00000008
190    #define         CTRL_GAME_PORT 0x00000e00
191    #define         CTRL_IRQ_ENABLE 0x4000
192    
193    #define VORTEX_IRQ_CTRL 0x12804 /* Interrupt source mask. */
194    #define         IRQ_FATAL    0x0001
195    #define         IRQ_PARITY   0x0002
196    #define         IRQ_PCMOUT   0x0020 /* PCM OUT page crossing */
197    #define         IRQ_TIMER    0x1000
198    #define         IRQ_MIDI     0x2000
199    
200    /* write: Timer period config / read: TIMER IRQ ack. */
201    #define VORTEX_IRQ_STAT 0x1199c
202    
203    /* DMA */
204    #define VORTEX_DMA_BUFFER 0x10200
205    #define VORTEX_ENGINE_CTRL 0x1060c
206    #define         ENGINE_INIT 0x0L
207    
208    /* MIDI */ /* GAME. */
209    #define VORTEX_MIDI_DATA 0x11000
210    #define VORTEX_MIDI_CMD 0x11004  /* Write command / Read status */
211    #define VORTEX_GAME_LEGACY 0x11008
212    #define VORTEX_CTRL2 0x1100c
213    #define         CTRL2_GAME_ADCMODE 0x40
214    #define VORTEX_GAME_AXIS 0x11010
215    #define         AXIS_SIZE 4
216    #define         AXIS_RANGE 0x1fff

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