/[openvortex]/alsa/pci/au88x0/au8810.h
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Diff of /alsa/pci/au88x0/au8810.h

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revision 1.2 by vizard, Wed Apr 16 01:12:29 2003 UTC revision 1.3 by mjander, Fri Apr 18 23:47:50 2003 UTC
# Line 1  Line 1 
1  /*  /*
2      Aureal Vortex Soundcard driver.      Aureal Advantage Soundcard driver.
   
     IO addr collected from asp4core.vxd:  
     function    address  
     0005D5A0    13004  
     00080674    14004  
     00080AFF    12818  
3    
4   */   */
5    
   
   
6  #define CONFIG_SND_AU8810  #define CONFIG_SND_AU8810
7  #undef CONFIG_SND_AU8820  #undef CONFIG_SND_AU8820
8  #undef CONFIG_SND_AU8830  #undef CONFIG_SND_AU8830
9    
10    #define CARD_NAME "Aureal Advantage 3D Sound Processor"
11    #define CARD_NAME_SHORT "au8810"
12    
13  #ifndef PCI_VENDOR_ID_AUREAL  #ifndef PCI_VENDOR_ID_AUREAL
14  #define PCI_VENDOR_ID_AUREAL 0x12eb  #define PCI_VENDOR_ID_AUREAL 0x12eb
15  #endif  #endif
16  #ifndef PCI_VENDOR_ID_AUREAL_VORTEX2  #ifndef PCI_VENDOR_ID_AUREAL_ADVANTAGE
17  #define PCI_DEVICE_ID_AUREAL_VORTEX2 0x0002  #define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003
18  #endif  #endif
19    
20  #define hwread(x,y) readl((x)+((y)>>2))  #define hwread(x,y) readl((x)+((y)>>2))
# Line 48  Line 43 
43  #define         FMT_MASK 0x0003c000  #define         FMT_MASK 0x0003c000
44  #define         FMT_SHIFT 0xe  #define         FMT_SHIFT 0xe
45  // The ADB masks and shift also are valid for the wtdma, except if specified otherwise.  // The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
46  #define VORTEX_ADBDMA_BUFCFG0 0x27100  #define VORTEX_ADBDMA_BUFCFG0 0x27800
47  #define VORTEX_ADBDMA_BUFCFG1 0x27104  #define VORTEX_ADBDMA_BUFCFG1 0x27804
48  #define VORTEX_ADBDMA_BUFBASE 0x27fc0  #define VORTEX_ADBDMA_BUFBASE 0x27400
49  #define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */  #define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */
50    
51    
52  /* WTDMA */  /* WTDMA */
53  #define VORTEX_WTDMA_CTRL 0x27fd8 /* format, DMA pos */  #define VORTEX_WTDMA_CTRL 0x27900 /* format, DMA pos */
54  #define VORTEX_WTDMA_STAT 0x27fe8 /* DMA subbuf, DMA pos */  #define VORTEX_WTDMA_STAT 0x27d00 /* DMA subbuf, DMA pos */
55  #define     WT_SUBBUF_MASK 0x3  #define     WT_SUBBUF_MASK 0x3
56  #define     WT_SUBBUF_SHIFT 0xc  #define     WT_SUBBUF_SHIFT 0xc
57  #define VORTEX_WTDMA_BUFBASE 0x27fc0  #define VORTEX_WTDMA_BUFBASE 0x27000
58  #define VORTEX_WTDMA_BUFCFG0 0x27fd0  #define VORTEX_WTDMA_BUFCFG0 0x27600
59  #define VORTEX_WTDMA_BUFCFG1 0x27fd4  #define VORTEX_WTDMA_BUFCFG1 0x27604
60  #define VORTEX_WTDMA_START 0x27fe4 /* which subbuffer is first */  #define VORTEX_WTDMA_START 0x27b00 /* which subbuffer is first */
61    
62    
63  /* ADB */  /* ADB */
# Line 83  Line 78 
78  #define         OFFSET_MIXOUT   0x30  #define         OFFSET_MIXOUT   0x30
79  #define         OFFSET_CODECIN  0x70  #define         OFFSET_CODECIN  0x70
80  #define         OFFSET_CODECOUT 0x88  #define         OFFSET_CODECOUT 0x88
81  #define         OFFSET_SPORTIN  0x78  #define         OFFSET_SPORTIN  0x78 /* ch 0x13 */
82  #define         OFFSET_SPORTOUT 0x90  #define         OFFSET_SPORTOUT 0x90
83  #define         OFFSET_EQIN             0x00  #define         OFFSET_EQIN             0x0 /* ?? */
84  #define         OFFSET_EQOUT    0x7e  #define         OFFSET_EQOUT    0x7e /* ch 0x11 */
85    
86  /* ADB route translate helper */  /* ADB route translate helper */
87  #define ADB_DMA(x) (x)  #define ADB_DMA(x) (x)
# Line 147  Line 142 
142  #define         FIFO_EMPTY      0x00000020  #define         FIFO_EMPTY      0x00000020
143  #define         FIFO_U0         0x00002000 /* Unknown. */  #define         FIFO_U0         0x00002000 /* Unknown. */
144  #define         FIFO_U1         0x00040000  #define         FIFO_U1         0x00040000
145  #define         FIFO_MASK       0x1f    /* at shift left 0xc */  #define         FIFO_MASK       0x3f    /* at shift left 0xc */
146  #define         FIFO_SIZE       0x40  #define         FIFO_SIZE       0x40
147  #define         FIFO_BITS       0x1c400000  #define         FIFO_BITS       0x1c400000
148  #define VORTEX_FIFO_ADBDATA 0x14000  #define VORTEX_FIFO_ADBDATA 0x14000
# Line 188  Line 183 
183  #define         CTRL_MIDI_PORT  0x00000060  #define         CTRL_MIDI_PORT  0x00000060
184  #define         CTRL_GAME_EN    0x00000008  #define         CTRL_GAME_EN    0x00000008
185  #define         CTRL_GAME_PORT  0x00000e00  #define         CTRL_GAME_PORT  0x00000e00
186  #define         CTRL_IRQ_ENABLE 0x01004000  //#define       CTRL_IRQ_ENABLE 0x01004000
187    #define         CTRL_IRQ_ENABLE 0x00004000
188    
189  #define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */  #define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */
190  #define         IRQ_FATAL       0x0001  #define         IRQ_FATAL       0x0001

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