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/* |
/* |
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Aureal Vortex Soundcard driver. |
Aureal Advantage Soundcard driver. |
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IO addr collected from asp4core.vxd: |
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function address |
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0005D5A0 13004 |
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00080674 14004 |
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00080AFF 12818 |
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*/ |
*/ |
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#define CONFIG_SND_AU8810 |
#define CONFIG_SND_AU8810 |
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#undef CONFIG_SND_AU8820 |
#undef CONFIG_SND_AU8820 |
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#undef CONFIG_SND_AU8830 |
#undef CONFIG_SND_AU8830 |
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#define CARD_NAME "Aureal Advantage 3D Sound Processor" |
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#define CARD_NAME_SHORT "au8810" |
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#ifndef PCI_VENDOR_ID_AUREAL |
#ifndef PCI_VENDOR_ID_AUREAL |
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#define PCI_VENDOR_ID_AUREAL 0x12eb |
#define PCI_VENDOR_ID_AUREAL 0x12eb |
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#endif |
#endif |
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#ifndef PCI_VENDOR_ID_AUREAL_VORTEX2 |
#ifndef PCI_VENDOR_ID_AUREAL_ADVANTAGE |
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#define PCI_DEVICE_ID_AUREAL_VORTEX2 0x0002 |
#define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003 |
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#endif |
#endif |
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#define hwread(x,y) readl((x)+((y)>>2)) |
#define hwread(x,y) readl((x)+((y)>>2)) |
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#define FMT_MASK 0x0003c000 |
#define FMT_MASK 0x0003c000 |
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#define FMT_SHIFT 0xe |
#define FMT_SHIFT 0xe |
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// The ADB masks and shift also are valid for the wtdma, except if specified otherwise. |
// The ADB masks and shift also are valid for the wtdma, except if specified otherwise. |
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#define VORTEX_ADBDMA_BUFCFG0 0x27100 |
#define VORTEX_ADBDMA_BUFCFG0 0x27800 |
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#define VORTEX_ADBDMA_BUFCFG1 0x27104 |
#define VORTEX_ADBDMA_BUFCFG1 0x27804 |
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#define VORTEX_ADBDMA_BUFBASE 0x27fc0 |
#define VORTEX_ADBDMA_BUFBASE 0x27400 |
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#define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */ |
#define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */ |
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/* WTDMA */ |
/* WTDMA */ |
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#define VORTEX_WTDMA_CTRL 0x27fd8 /* format, DMA pos */ |
#define VORTEX_WTDMA_CTRL 0x27900 /* format, DMA pos */ |
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#define VORTEX_WTDMA_STAT 0x27fe8 /* DMA subbuf, DMA pos */ |
#define VORTEX_WTDMA_STAT 0x27d00 /* DMA subbuf, DMA pos */ |
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#define WT_SUBBUF_MASK 0x3 |
#define WT_SUBBUF_MASK 0x3 |
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#define WT_SUBBUF_SHIFT 0xc |
#define WT_SUBBUF_SHIFT 0xc |
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#define VORTEX_WTDMA_BUFBASE 0x27fc0 |
#define VORTEX_WTDMA_BUFBASE 0x27000 |
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#define VORTEX_WTDMA_BUFCFG0 0x27fd0 |
#define VORTEX_WTDMA_BUFCFG0 0x27600 |
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#define VORTEX_WTDMA_BUFCFG1 0x27fd4 |
#define VORTEX_WTDMA_BUFCFG1 0x27604 |
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#define VORTEX_WTDMA_START 0x27fe4 /* which subbuffer is first */ |
#define VORTEX_WTDMA_START 0x27b00 /* which subbuffer is first */ |
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/* ADB */ |
/* ADB */ |
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#define OFFSET_MIXOUT 0x30 |
#define OFFSET_MIXOUT 0x30 |
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#define OFFSET_CODECIN 0x70 |
#define OFFSET_CODECIN 0x70 |
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#define OFFSET_CODECOUT 0x88 |
#define OFFSET_CODECOUT 0x88 |
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#define OFFSET_SPORTIN 0x78 |
#define OFFSET_SPORTIN 0x78 /* ch 0x13 */ |
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#define OFFSET_SPORTOUT 0x90 |
#define OFFSET_SPORTOUT 0x90 |
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#define OFFSET_EQIN 0x00 |
#define OFFSET_EQIN 0x0 /* ?? */ |
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#define OFFSET_EQOUT 0x7e |
#define OFFSET_EQOUT 0x7e /* ch 0x11 */ |
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/* ADB route translate helper */ |
/* ADB route translate helper */ |
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#define ADB_DMA(x) (x) |
#define ADB_DMA(x) (x) |
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#define FIFO_EMPTY 0x00000020 |
#define FIFO_EMPTY 0x00000020 |
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#define FIFO_U0 0x00002000 /* Unknown. */ |
#define FIFO_U0 0x00002000 /* Unknown. */ |
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#define FIFO_U1 0x00040000 |
#define FIFO_U1 0x00040000 |
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#define FIFO_MASK 0x1f /* at shift left 0xc */ |
#define FIFO_MASK 0x3f /* at shift left 0xc */ |
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#define FIFO_SIZE 0x40 |
#define FIFO_SIZE 0x40 |
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#define FIFO_BITS 0x1c400000 |
#define FIFO_BITS 0x1c400000 |
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#define VORTEX_FIFO_ADBDATA 0x14000 |
#define VORTEX_FIFO_ADBDATA 0x14000 |
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#define CTRL_MIDI_PORT 0x00000060 |
#define CTRL_MIDI_PORT 0x00000060 |
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#define CTRL_GAME_EN 0x00000008 |
#define CTRL_GAME_EN 0x00000008 |
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#define CTRL_GAME_PORT 0x00000e00 |
#define CTRL_GAME_PORT 0x00000e00 |
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#define CTRL_IRQ_ENABLE 0x01004000 |
//#define CTRL_IRQ_ENABLE 0x01004000 |
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#define CTRL_IRQ_ENABLE 0x00004000 |
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#define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */ |
#define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */ |
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#define IRQ_FATAL 0x0001 |
#define IRQ_FATAL 0x0001 |