/[openvortex]/alsa/pci/au88x0/au8810.h
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Diff of /alsa/pci/au88x0/au8810.h

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revision 1.14 by mjander, Thu Aug 7 01:58:50 2003 UTC revision 1.15 by vizard, Sun Aug 10 20:00:33 2003 UTC
# Line 1  Line 1 
1  #define __NO_VERSION__  /*
2  #include "../../alsa-kernel/pci/au88x0/au8810.h"      Aureal Advantage Soundcard driver.
3     */
4    
5    #define CHIP_AU8810
6    
7    #define CARD_NAME "Aureal Advantage 3D Sound Processor"
8    #define CARD_NAME_SHORT "au8810"
9    
10    #ifndef PCI_VENDOR_ID_AUREAL
11    #define PCI_VENDOR_ID_AUREAL 0x12eb
12    #endif
13    #ifndef PCI_VENDOR_ID_AUREAL_ADVANTAGE
14    #define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003
15    #endif
16    
17    #define hwread(x,y) readl((x)+((y)>>2))
18    #define hwwrite(x,y,z) writel((z),(x)+((y)>>2))
19    
20    #define NR_ADB 0x10
21    #define NR_SRC 0x10
22    #define NR_A3D 0x10
23    #define NR_MIXIN 0x20
24    #define NR_MIXOUT 0x10
25    #define NR_WT 0x20
26    
27    /* ADBDMA */
28    #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
29    #define         POS_MASK 0x00000fff
30    #define     POS_SHIFT 0x0
31    #define         ADB_SUBBUF_MASK 0x00003000  /* ADB only. */
32    #define     ADB_SUBBUF_SHIFT 0xc        /* ADB only. */
33    #define VORTEX_ADBDMA_CTRL 0x27180      /* write only; format, flags, DMA pos */
34    #define         OFFSET_MASK 0x00000fff
35    #define     OFFSET_SHIFT 0x0
36    #define         IE_MASK 0x00001000 /* interrupt enable. */
37    #define     IE_SHIFT 0xc
38    #define     U_MASK 0x00002000  /* Unknown. If you know, tell me. */
39    #define     U_SHIFT 0xd
40    #define         FMT_MASK 0x0003c000
41    #define         FMT_SHIFT 0xe
42    // The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
43    #define VORTEX_ADBDMA_BUFCFG0 0x27100
44    #define VORTEX_ADBDMA_BUFCFG1 0x27104
45    #define VORTEX_ADBDMA_BUFBASE 0x27000
46    #define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */
47    
48    /* WTDMA */
49    #define VORTEX_WTDMA_CTRL 0x27fd8  /* format, DMA pos */
50    #define VORTEX_WTDMA_STAT 0x27fe8  /* DMA subbuf, DMA pos */
51    #define     WT_SUBBUF_MASK 0x3
52    #define     WT_SUBBUF_SHIFT 0xc
53    #define VORTEX_WTDMA_BUFBASE 0x27fc0
54    #define VORTEX_WTDMA_BUFCFG0 0x27fd0
55    #define VORTEX_WTDMA_BUFCFG1 0x27fd4
56    #define VORTEX_WTDMA_START 0x27fe4 /* which subbuffer is first */
57    
58    /* ADB */
59    #define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */
60    #define VORTEX_ADB_RTBASE 0x28000
61    #define VORTEX_ADB_RTBASE_SIZE (VORTEX_ADB_CHNBASE - VORTEX_ADB_RTBASE)
62    #define VORTEX_ADB_CHNBASE 0x282b4
63    #define VORTEX_ADB_CHNBASE_SIZE (ADB_MASK - VORTEX_ADB_RTBASE_SIZE)
64    #define         ROUTE_MASK      0xffff
65    #define         SOURCE_MASK     0xff00
66    #define     ADB_MASK   0xff
67    #define         ADB_SHIFT 0x8
68    /* ADB address */
69    #define         OFFSET_ADBDMA   0x00
70    #define         OFFSET_SRCIN    0x40
71    #define         OFFSET_SRCOUT   0x20
72    #define         OFFSET_MIXIN    0x50
73    #define         OFFSET_MIXOUT   0x30
74    #define         OFFSET_CODECIN  0x70
75    #define         OFFSET_CODECOUT 0x88
76    #define         OFFSET_SPORTIN  0x78 /* ch 0x13 */
77    #define         OFFSET_SPORTOUT 0x90
78    #define         OFFSET_EQIN             0xa0
79    #define         OFFSET_EQOUT    0x7e /* 2 routes on ch 0x11 */
80    
81    /* ADB route translate helper */
82    #define ADB_DMA(x) (x)
83    #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
84    #define ADB_SRCIN(x) (x + OFFSET_SRCIN)
85    #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
86    #define ADB_MIXIN(x) (x + OFFSET_MIXIN)
87    #define ADB_CODECIN(x) (x + OFFSET_CODECIN)
88    #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
89    #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
90    #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
91    #define ADB_EQIN(x) (x + OFFSET_EQIN)
92    #define ADB_EQOUT(x) (x + OFFSET_EQOUT)
93    #define ADB_A3DOUT(x) (x + 0x50) /* A3D blocks */
94    #define ADB_A3DIN(x) (x + 0x70)
95    
96    #define MIX_OUTL    0xe
97    #define MIX_OUTR    0xf
98    #define MIX_INL     0x1e
99    #define MIX_INR     0x1f
100    #define MIX_DEFIGAIN 0x00 /* 0x8 => 6dB */
101    #define MIX_DEFOGAIN 0x00
102    
103    /* MIXER */
104    #define VORTEX_MIXER_SR 0x21f00
105    #define VORTEX_MIXER_CHNBASE 0x21e40
106    #define VORTEX_MIXER_RTBASE 0x21e00
107    #define         MIXER_RTBASE_SIZE 0x38
108    #define VORTEX_MIX_U0 0x21c00 /* AU8820: 0x9c00 */
109    
110    /* MIX */
111    #define VORTEX_MIX_INVOL_A 0x21000 /* in? */
112    #define VORTEX_MIX_INVOL_B 0x20000 /* out? */
113    #define VORTEX_MIX_VOL_A 0x21800
114    #define VORTEX_MIX_VOL_B 0x20800
115    #define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */
116    #define         VOL_MIN 0x80 /* Input volume when muted. */
117    #define         VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
118    
119    /* SRC */
120    #define VORTEX_SRCBLOCK_SR      0x26cc0
121    #define VORTEX_SRC_CHNBASE      0x26c40
122    #define VORTEX_SRC_RTBASE       0x26c00
123    #define VORTEX_SRC_SOURCE       0x26cc4
124    #define VORTEX_SRC_CONVRATIO 0x26e40
125    #define VORTEX_SRC_DRIFT0       0x26e80
126    #define VORTEX_SRC_DRIFT1       0x26ec0
127    #define VORTEX_SRC_DRIFT2       0x26f40
128    #define VORTEX_SRC_U0           0x26e00
129    #define VORTEX_SRC_U1           0x26f00
130    #define VORTEX_SRC_U3           0x26f80
131    #define VORTEX_SRC_DATA         0x26800 /* 0xc800 */
132    #define VORTEX_SRC_DATA0        0x26000
133    
134    /* FIFO */
135    #define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */
136    #define VORTEX_FIFO_WTCTRL 0x16000
137    #define         FIFO_RDONLY     0x00000001
138    #define         FIFO_CTRL       0x00000002 /* Allow ctrl. ? */
139    #define         FIFO_VALID      0x00000010
140    #define         FIFO_EMPTY      0x00000020
141    #define         FIFO_U0         0x00001000 /* Unknown. */
142    #define         FIFO_U1         0x00010000
143    #define         FIFO_SIZE_BITS 5
144    #define         FIFO_SIZE       (1<<FIFO_SIZE_BITS) // 0x20
145    #define         FIFO_MASK       (FIFO_SIZE-1) //0x1f    /* at shift left 0xc */
146    //#define       FIFO_MASK       0x1f    /* at shift left 0xb */
147    //#define               FIFO_SIZE       0x20
148    #define         FIFO_BITS       0x03880000
149    #define VORTEX_FIFO_ADBDATA 0x14000
150    #define VORTEX_FIFO_WTDATA 0x10000
151    
152    /* CODEC */
153    #define VORTEX_CODEC_CTRL 0x29184
154    #define VORTEX_CODEC_EN 0x29190
155    #define         EN_CODEC0       0x00000300
156    #define         EN_CODEC1       0x00003000
157    #define         EN_CODEC        (EN_CODEC0 | EN_CODEC1)
158    #define         EN_SPORT        0x00030000
159    #define         EN_SPDIF        0x000c0000
160    #define VORTEX_CODEC_CHN 0x29080
161    #define VORTEX_CODEC_WRITE 0x00800000
162    #define VORTEX_CODEC_ADDSHIFT 16
163    #define VORTEX_CODEC_ADDMASK 0x7f0000 /* 0x000f0000*/
164    #define VORTEX_CODEC_DATSHIFT 0
165    #define VORTEX_CODEC_DATMASK 0xffff
166    #define VORTEX_CODEC_IO 0x29188
167    
168    /* Sample timer */
169    #define VORTEX_SMP_TIME  0x29198
170    
171    /* IRQ */
172    #define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */
173    #define         IRQ_FATAL    0x0001
174    #define         IRQ_PARITY   0x0002
175    #define         IRQ_PCMOUT   0x0020 /* ?? */
176    #define         IRQ_TIMER    0x1000
177    #define         IRQ_MIDI     0x2000
178    #define         IRQ_MODEM       0x4000
179    
180    #define VORTEX_IRQ_U0   0x2a008 /* ?? */
181    
182    #define VORTEX_CTRL             0x2a00c
183    #define         CTRL_MIDI_EN    0x00000001
184    #define         CTRL_MIDI_PORT  0x00000060
185    #define         CTRL_GAME_EN    0x00000008
186    #define         CTRL_GAME_PORT  0x00000e00
187    //#define       CTRL_IRQ_ENABLE 0x01004000
188    #define         CTRL_IRQ_ENABLE 0x00004000
189    
190    #define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */
191    #define         IRQ_FATAL       0x0001
192    #define         IRQ_PARITY      0x0002
193    #define         IRQ_PCMOUT      0x0020 /* PCM OUT page crossing */
194    #define         IRQ_TIMER       0x1000
195    #define         IRQ_MIDI        0x2000
196    #define         IRQ_MODEM       0x4000
197    
198    /* write: Timer period config / read: TIMER IRQ ack. */
199    #define VORTEX_IRQ_STAT 0x2919c
200    
201    /* DMA */
202    #define VORTEX_ENGINE_CTRL 0x27ae8
203    #define         ENGINE_INIT 0x1380000
204    
205    /* MIDI */ /* GAME. */
206    #define VORTEX_MIDI_DATA 0x28800
207    #define VORTEX_MIDI_CMD 0x28804  /* Write command / Read status */
208    
209    #define VORTEX_CTRL2 0x2880c
210    #define         CTRL2_GAME_ADCMODE 0x40
211    #define VORTEX_GAME_LEGACY 0x28808
212    #define VORTEX_GAME_AXIS 0x28810
213    #define         AXIS_SIZE 4
214    #define         AXIS_RANGE 0x1fff

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