86 |
* Indirect registers |
* Indirect registers |
87 |
*/ |
*/ |
88 |
|
|
89 |
#define ICE1712_IREG_PBK_COUNT_HI 0x00 |
#define ICE1712_IREG_PBK_COUNT_LO 0x00 |
90 |
#define ICE1712_IREG_PBK_COUNT_LO 0x01 |
#define ICE1712_IREG_PBK_COUNT_HI 0x01 |
91 |
#define ICE1712_IREG_PBK_CTRL 0x02 |
#define ICE1712_IREG_PBK_CTRL 0x02 |
92 |
#define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */ |
#define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */ |
93 |
#define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */ |
#define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */ |
95 |
#define ICE1712_IREG_PBK_RATE_LO 0x06 |
#define ICE1712_IREG_PBK_RATE_LO 0x06 |
96 |
#define ICE1712_IREG_PBK_RATE_MID 0x07 |
#define ICE1712_IREG_PBK_RATE_MID 0x07 |
97 |
#define ICE1712_IREG_PBK_RATE_HI 0x08 |
#define ICE1712_IREG_PBK_RATE_HI 0x08 |
98 |
#define ICE1712_IREG_CAP_COUNT_HI 0x10 |
#define ICE1712_IREG_CAP_COUNT_LO 0x10 |
99 |
#define ICE1712_IREG_CAP_COUNT_LO 0x11 |
#define ICE1712_IREG_CAP_COUNT_HI 0x11 |
100 |
#define ICE1712_IREG_CAP_CTRL 0x12 |
#define ICE1712_IREG_CAP_CTRL 0x12 |
101 |
#define ICE1712_IREG_GPIO_DATA 0x20 |
#define ICE1712_IREG_GPIO_DATA 0x20 |
102 |
#define ICE1712_IREG_GPIO_WRITE_MASK 0x21 |
#define ICE1712_IREG_GPIO_WRITE_MASK 0x21 |