2743 |
* gameport interface |
* gameport interface |
2744 |
*/ |
*/ |
2745 |
|
|
2746 |
#if defined(CONFIG_GAMEPORT) || defined(CONFIG_GAMEPORT_MODULE) |
#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) |
2747 |
|
|
2748 |
typedef struct snd_cs46xx_gameport { |
typedef struct snd_cs46xx_gameport { |
2749 |
struct gameport info; |
struct gameport info; |
2960 |
if (chip->active_ctrl) |
if (chip->active_ctrl) |
2961 |
chip->active_ctrl(chip, 1); |
chip->active_ctrl(chip, 1); |
2962 |
|
|
2963 |
#if defined(CONFIG_GAMEPORT) || defined(CONFIG_GAMEPORT_MODULE) |
#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) |
2964 |
if (chip->gameport) { |
if (chip->gameport) { |
2965 |
gameport_unregister_port(&chip->gameport->info); |
gameport_unregister_port(&chip->gameport->info); |
2966 |
kfree(chip->gameport); |
kfree(chip->gameport); |
3010 |
/* |
/* |
3011 |
* initialize chip |
* initialize chip |
3012 |
*/ |
*/ |
3013 |
static int snd_cs46xx_chip_init(cs46xx_t *chip, int busywait) |
static int snd_cs46xx_chip_init(cs46xx_t *chip) |
3014 |
{ |
{ |
3015 |
int timeout; |
int timeout; |
3016 |
|
|
3090 |
/* |
/* |
3091 |
* Wait until the PLL has stabilized. |
* Wait until the PLL has stabilized. |
3092 |
*/ |
*/ |
3093 |
mdelay(100); /* FIXME: schedule? */ |
set_current_state(TASK_UNINTERRUPTIBLE); |
3094 |
|
schedule_timeout(HZ/10); /* 100ms */ |
3095 |
|
|
3096 |
/* |
/* |
3097 |
* Turn on clocking of the core so that we can setup the serial ports. |
* Turn on clocking of the core so that we can setup the serial ports. |
3144 |
*/ |
*/ |
3145 |
if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) |
if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) |
3146 |
goto ok1; |
goto ok1; |
3147 |
if (busywait) |
set_current_state(TASK_UNINTERRUPTIBLE); |
3148 |
mdelay(10); |
schedule_timeout((HZ+99)/100); |
|
else { |
|
|
set_current_state(TASK_UNINTERRUPTIBLE); |
|
|
schedule_timeout((HZ+99)/100); |
|
|
} |
|
3149 |
} |
} |
3150 |
|
|
3151 |
|
|
3194 |
*/ |
*/ |
3195 |
if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) |
if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) |
3196 |
goto ok2; |
goto ok2; |
3197 |
if (busywait) |
set_current_state(TASK_UNINTERRUPTIBLE); |
3198 |
mdelay(10); |
schedule_timeout((HZ+99)/100); |
|
else { |
|
|
set_current_state(TASK_UNINTERRUPTIBLE); |
|
|
schedule_timeout((HZ+99)/100); |
|
|
} |
|
3199 |
} |
} |
3200 |
|
|
3201 |
#ifndef CONFIG_SND_CS46XX_NEW_DSP |
#ifndef CONFIG_SND_CS46XX_NEW_DSP |
3804 |
chip->amplifier = 0; |
chip->amplifier = 0; |
3805 |
chip->active_ctrl(chip, 1); /* force to on */ |
chip->active_ctrl(chip, 1); /* force to on */ |
3806 |
|
|
3807 |
snd_cs46xx_chip_init(chip, 1); |
snd_cs46xx_chip_init(chip); |
3808 |
|
|
3809 |
#if 0 |
#if 0 |
3810 |
snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE, |
snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE, |
3985 |
} |
} |
3986 |
#endif |
#endif |
3987 |
|
|
3988 |
err = snd_cs46xx_chip_init(chip, 0); |
err = snd_cs46xx_chip_init(chip); |
3989 |
if (err < 0) { |
if (err < 0) { |
3990 |
snd_cs46xx_free(chip); |
snd_cs46xx_free(chip); |
3991 |
return err; |
return err; |