/[hurd]/hurd-l4/README
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revision 1.5 by marcus, Fri Sep 12 18:45:56 2003 UTC revision 1.6 by marcus, Tue Sep 16 19:24:05 2003 UTC
# Line 24  $ cp physmem/physmem /l4/boot Line 24  $ cp physmem/physmem /l4/boot
24    
25  Note that use of optimization is mandatory, not optional.  Note that use of optimization is mandatory, not optional.
26    
27  You also need the L4 kernel and sigma0.  sigma0 must be built with a  
28  different link base than the default value 0x20000, because that  Installation
29  conflicts with GRUB (on ia32).  I have successfully used a link base  ------------
30  of 0x40000.  Then set up GRUB to boot laden as the kernel, and the L4  
31  kernel, sigma0, wortel (the rootserver) and physmem as its modules.  Prerequisites: Pistachio-0.2 with the patch you can find at the end of
32    this file.
33    
34    Furthermore, sigma0 must be built with a different link base than the
35    default value 0x20000, because that conflicts with GRUB (on ia32).  I
36    have successfully used a link base of 0x40000.
37    
38    Then set up GRUB to boot laden as the kernel, and the L4 kernel,
39    sigma0, wortel (the rootserver) and physmem as its modules.
40    
41  Try the debug option (-D) to laden and wortel to see some output from  Try the debug option (-D) to laden and wortel to see some output from
42  them.  They are silent by default.  them.  They are silent by default.
43    
44    
45    sigma0 Patch
46    ------------
47    
48    sigma0 in pistachio 0.2 is a bit buggy.  The following patch fixes the
49    problems that the bugs cause to wortel.
50    
51    --- pistachio-0.2/user/serv/sigma0/sigma0.cc.prev       2003-09-16 20:29:14.000000000 +0200
52    +++ pistachio-0.2/user/serv/sigma0/sigma0.cc    2003-09-16 21:03:09.000000000 +0200
53    @@ -506,7 +506,8 @@
54         L4_Word_t low_a = (low + size - 1) & ~(size-1);
55         L4_Fpage_t ret;
56    
57    -    if ((high_a - low_a) < size || (owner != tid && owner != L4_anythread))
58    +    if (low_a > high_a || (high_a - low_a) < size
59    +       || (owner != tid && owner != L4_anythread))
60         {
61            // Allocation failed
62            ret = L4_Nilpage;
63    @@ -530,7 +531,7 @@
64         {
65            // Allocate from middle of region
66            ret = L4_FpageLog2 (low_a, log2size) + L4_FullyAccessible;
67    -       memregion_t * r = new memregion_t (high_a, high, owner);
68    +       memregion_t * r = new memregion_t (low_a + size, high, owner);
69            r->next = next;
70            r->prev = this;
71            r->next->prev = next = r;
72    @@ -1246,7 +1247,7 @@
73         {
74            if ((fp = r->allocate (log2size)).raw != L4_Nilpage.raw)
75            {
76    -           map = L4_MapItem (fp, 0);
77    +           map = L4_MapItem (fp, L4_Address (fp));
78                alloc_pool.insert
79                    (new memregion_t (L4_Address (fp), L4_Address (fp) +
80                                      (1UL << log2size), tid));

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