/[grub]/grub/netboot/pci.h
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revision 1.7 by okuji, Sat Jul 29 19:22:54 2000 UTC revision 1.8 by okuji, Wed Jan 2 21:56:40 2002 UTC
# Line 22  Line 22 
22   */   */
23    
24  #define PCI_COMMAND_IO                  0x1     /* Enable response in I/O space */  #define PCI_COMMAND_IO                  0x1     /* Enable response in I/O space */
25    #define PCI_COMMAND_MEM                 0x2     /* Enable response in mem space */
26  #define PCI_COMMAND_MASTER              0x4     /* Enable bus mastering */  #define PCI_COMMAND_MASTER              0x4     /* Enable bus mastering */
27  #define PCI_LATENCY_TIMER               0x0d    /* 8 bits */  #define PCI_LATENCY_TIMER               0x0d    /* 8 bits */
28    
# Line 41  Line 42 
42  #define PCI_DEVICE_ID           0x02    /* 16 bits */  #define PCI_DEVICE_ID           0x02    /* 16 bits */
43  #define PCI_COMMAND             0x04    /* 16 bits */  #define PCI_COMMAND             0x04    /* 16 bits */
44    
45    #define PCI_REVISION            0x08    /* 8 bits  */
46  #define PCI_CLASS_CODE          0x0b    /* 8 bits */  #define PCI_CLASS_CODE          0x0b    /* 8 bits */
47  #define PCI_SUBCLASS_CODE       0x0a    /* 8 bits */  #define PCI_SUBCLASS_CODE       0x0a    /* 8 bits */
48  #define PCI_HEADER_TYPE         0x0e    /* 8 bits */  #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
# Line 101  __asm__ __volatile__("pushl %0 ; popfl": Line 103  __asm__ __volatile__("pushl %0 ; popfl":
103  #define PCI_DEVICE_ID_REALTEK_8139      0x8139  #define PCI_DEVICE_ID_REALTEK_8139      0x8139
104  #define PCI_VENDOR_ID_WINBOND2          0x1050  #define PCI_VENDOR_ID_WINBOND2          0x1050
105  #define PCI_DEVICE_ID_WINBOND2_89C940   0x0940  #define PCI_DEVICE_ID_WINBOND2_89C940   0x0940
106    #define PCI_DEVICE_ID_WINBOND2_89C840   0x0840
107  #define PCI_VENDOR_ID_COMPEX            0x11f6  #define PCI_VENDOR_ID_COMPEX            0x11f6
108  #define PCI_DEVICE_ID_COMPEX_RL2000     0x1401  #define PCI_DEVICE_ID_COMPEX_RL2000     0x1401
109    #define PCI_DEVICE_ID_COMPEX_RL100ATX   0x2011
110  #define PCI_VENDOR_ID_KTI               0x8e2e  #define PCI_VENDOR_ID_KTI               0x8e2e
111  #define PCI_DEVICE_ID_KTI_ET32P2        0x3000  #define PCI_DEVICE_ID_KTI_ET32P2        0x3000
112  #define PCI_VENDOR_ID_NETVIN            0x4a14  #define PCI_VENDOR_ID_NETVIN            0x4a14
113  #define PCI_DEVICE_ID_NETVIN_NV5000SC   0x5000  #define PCI_DEVICE_ID_NETVIN_NV5000SC   0x5000
114    #define PCI_VENDOR_ID_HOLTEK            0x12c3
115    #define PCI_DEVICE_ID_HOLTEK_HT80232    0x0058
116  #define PCI_VENDOR_ID_3COM              0x10b7  #define PCI_VENDOR_ID_3COM              0x10b7
117  #define PCI_DEVICE_ID_3COM_3C590        0x5900  #define PCI_DEVICE_ID_3COM_3C590        0x5900
118  #define PCI_DEVICE_ID_3COM_3C595        0x5950  #define PCI_DEVICE_ID_3COM_3C595        0x5950
# Line 120  __asm__ __volatile__("pushl %0 ; popfl": Line 126  __asm__ __volatile__("pushl %0 ; popfl":
126  #define PCI_DEVICE_ID_3COM_3C905C_TXM   0x9200  #define PCI_DEVICE_ID_3COM_3C905C_TXM   0x9200
127  #define PCI_VENDOR_ID_INTEL             0x8086  #define PCI_VENDOR_ID_INTEL             0x8086
128  #define PCI_DEVICE_ID_INTEL_82557       0x1229  #define PCI_DEVICE_ID_INTEL_82557       0x1229
129    #define PCI_DEVICE_ID_INTEL_82559ER     0x1209
130    #define PCI_DEVICE_ID_INTEL_ID1029      0x1029
131    #define PCI_DEVICE_ID_INTEL_ID1030      0x1030
132    #define PCI_DEVICE_ID_INTEL_82562       0x2449
133  #define PCI_VENDOR_ID_AMD               0x1022  #define PCI_VENDOR_ID_AMD               0x1022
134  #define PCI_DEVICE_ID_AMD_LANCE         0x2000  #define PCI_DEVICE_ID_AMD_LANCE         0x2000
135    #define PCI_VENDOR_ID_AMD_HOMEPNA       0x1022
136    #define PCI_DEVICE_ID_AMD_HOMEPNA       0x2001
137  #define PCI_VENDOR_ID_SMC_1211          0x1113  #define PCI_VENDOR_ID_SMC_1211          0x1113
138  #define PCI_DEVICE_ID_SMC_1211          0x1211  #define PCI_DEVICE_ID_SMC_1211          0x1211
139  #define PCI_VENDOR_ID_DEC               0x1011  #define PCI_VENDOR_ID_DEC               0x1011
# Line 139  __asm__ __volatile__("pushl %0 ; popfl": Line 151  __asm__ __volatile__("pushl %0 ; popfl":
151  #define PCI_DEVICE_ID_LC82C115          0xC115  #define PCI_DEVICE_ID_LC82C115          0xC115
152  #define PCI_VENDOR_ID_VIATEC            0x1106  #define PCI_VENDOR_ID_VIATEC            0x1106
153  #define PCI_DEVICE_ID_VIA_RHINE_I       0x3043  #define PCI_DEVICE_ID_VIA_RHINE_I       0x3043
154    #define PCI_DEVICE_ID_VIA_VT6102        0x3065
155  #define PCI_DEVICE_ID_VIA_86C100A       0x6100  #define PCI_DEVICE_ID_VIA_86C100A       0x6100
156  #define PCI_VENDOR_ID_DAVICOM           0x1282  #define PCI_VENDOR_ID_DAVICOM           0x1282
157    #define PCI_DEVICE_ID_DM9009            0x9009
158  #define PCI_DEVICE_ID_DM9102            0x9102  #define PCI_DEVICE_ID_DM9102            0x9102
159    #define PCI_VENDOR_ID_SIS               0x1039
160    #define PCI_DEVICE_ID_SIS900            0x0900  
161    #define PCI_DEVICE_ID_SIS7016           0x7016  
162    #define PCI_VENDOR_ID_DLINK             0x1186
163    #define PCI_DEVICE_ID_DFE530TXP         0x1300
164    #define PCI_VENDOR_ID_NS                0x100B
165    #define PCI_DEVICE_ID_DP83815           0x0020
166    #define PCI_VENDOR_ID_OLICOM            0x108d
167    #define PCI_DEVICE_ID_OLICOM_OC3136     0x0001
168    #define PCI_DEVICE_ID_OLICOM_OC2315     0x0011
169    #define PCI_DEVICE_ID_OLICOM_OC2325     0x0012
170    #define PCI_DEVICE_ID_OLICOM_OC2183     0x0013
171    #define PCI_DEVICE_ID_OLICOM_OC2326     0x0014
172    #define PCI_DEVICE_ID_OLICOM_OC6151     0x0021
173    
174  struct pci_device {  struct pci_device {
175          unsigned short  vendor, dev_id;          unsigned short  vendor, dev_id;
176          const char      *name;          const char      *name;
177          unsigned int    membase;          unsigned int    membase;
178          unsigned short  ioaddr;          unsigned short  ioaddr;
179          unsigned short  devfn;          unsigned char   devfn;
180            unsigned char   bus;
181  };  };
182    
183  extern void     eth_pci_init(struct pci_device *);  extern void     eth_pci_init(struct pci_device *);
184    
185  extern int pcibios_read_config_byte(unsigned char bus, unsigned char device_fn, unsigned char where, unsigned char *value);  extern int pcibios_read_config_byte(unsigned int bus, unsigned int device_fn, unsigned int where, unsigned char *value);
186  extern int pcibios_write_config_byte (unsigned char bus, unsigned char device_fn, unsigned char where, unsigned char value);  extern int pcibios_write_config_byte (unsigned int bus, unsigned int device_fn, unsigned int where, unsigned char value);
187  extern int pcibios_read_config_word(unsigned char bus, unsigned char device_fn, unsigned char where, unsigned short *value);  extern int pcibios_read_config_word(unsigned int bus, unsigned int device_fn, unsigned int where, unsigned short *value);
188  extern int pcibios_write_config_word (unsigned char bus, unsigned char device_fn, unsigned char where, unsigned short value);  extern int pcibios_write_config_word (unsigned int bus, unsigned int device_fn, unsigned int where, unsigned short value);
189  extern int pcibios_write_config_dword(unsigned char bus,  extern int pcibios_read_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, unsigned int *value);
190          unsigned char device_fn, unsigned char where, unsigned int value);  extern int pcibios_write_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, unsigned int value);
191    void adjust_pci_device(struct pci_device *p);
192  #endif  /* PCI_H */  #endif  /* PCI_H */

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