351 |
#define TMD3_LCAR 0x0800 /* Loss of CARrier */ |
#define TMD3_LCAR 0x0800 /* Loss of CARrier */ |
352 |
#define TMD3_RTRY 0x0400 /* ReTRY error */ |
#define TMD3_RTRY 0x0400 /* ReTRY error */ |
353 |
|
|
|
/* |
|
|
** EISA configuration Register (CNFG) bit definitions |
|
|
*/ |
|
|
|
|
|
#define TIMEO 0x0100 /* 0:2.5 mins, 1: 30 secs */ |
|
|
#define REMOTE 0x0080 /* Remote Boot Enable -> 1 */ |
|
|
#define IRQ11 0x0040 /* Enable -> 1 */ |
|
|
#define IRQ10 0x0020 /* Enable -> 1 */ |
|
|
#define IRQ9 0x0010 /* Enable -> 1 */ |
|
|
#define IRQ5 0x0008 /* Enable -> 1 */ |
|
|
#define BUFF 0x0004 /* 0: 64kB or 128kB, 1: 32kB */ |
|
|
#define PADR16 0x0002 /* RAM on 64kB boundary */ |
|
|
#define PADR17 0x0001 /* RAM on 128kB boundary */ |
|
|
|
|
|
/* |
|
|
** Miscellaneous |
|
|
*/ |
|
|
#define HASH_TABLE_LEN 64 /* Bits */ |
|
|
#define HASH_BITS 0x003f /* 6 LS bits */ |
|
|
|
|
|
#define MASK_INTERRUPTS 1 |
|
|
#define UNMASK_INTERRUPTS 0 |
|
|
|
|
|
#define EISA_EN 0x0001 /* Enable EISA bus buffers */ |
|
|
#define EISA_ID iobase+0x0080 /* ID long word for EISA card */ |
|
|
#define EISA_CTRL iobase+0x0084 /* Control word for EISA card */ |
|
|
|
|
|
/* |
|
|
** Recognised commands for the driver |
|
|
*/ |
|
|
#define DEPCA_GET_HWADDR 0x01 /* Get the hardware address */ |
|
|
#define DEPCA_SET_HWADDR 0x02 /* Get the hardware address */ |
|
|
#define DEPCA_SET_PROM 0x03 /* Set Promiscuous Mode */ |
|
|
#define DEPCA_CLR_PROM 0x04 /* Clear Promiscuous Mode */ |
|
|
#define DEPCA_SAY_BOO 0x05 /* Say "Boo!" to the kernel log file */ |
|
|
#define DEPCA_GET_MCA 0x06 /* Get a multicast address */ |
|
|
#define DEPCA_SET_MCA 0x07 /* Set a multicast address */ |
|
|
#define DEPCA_CLR_MCA 0x08 /* Clear a multicast address */ |
|
|
#define DEPCA_MCA_EN 0x09 /* Enable a multicast address group */ |
|
|
#define DEPCA_GET_STATS 0x0a /* Get the driver statistics */ |
|
|
#define DEPCA_CLR_STATS 0x0b /* Zero out the driver statistics */ |
|
|
#define DEPCA_GET_REG 0x0c /* Get the Register contents */ |
|
|
#define DEPCA_SET_REG 0x0d /* Set the Register contents */ |
|
|
#define DEPCA_DUMP 0x0f /* Dump the DEPCA Status */ |
|
|
|
|
|
#ifdef DEPCA_DEBUG |
|
|
static int depca_debug = DEPCA_DEBUG; |
|
|
#else |
|
|
static int depca_debug = 1; |
|
|
#endif |
|
|
|
|
|
#define DEPCA_NDA 0xffe0 /* No Device Address */ |
|
|
|
|
354 |
/* |
/* |
355 |
** Ethernet PROM defines |
** Ethernet PROM defines |
356 |
*/ |
*/ |
363 |
** |
** |
364 |
** total_memory = NUM_RX_DESC*(8+RX_BUFF_SZ) + NUM_TX_DESC*(8+TX_BUFF_SZ) |
** total_memory = NUM_RX_DESC*(8+RX_BUFF_SZ) + NUM_TX_DESC*(8+TX_BUFF_SZ) |
365 |
*/ |
*/ |
366 |
#define NUM_RX_DESC 8 /* Number of RX descriptors */ |
#define NUM_RX_DESC 2 /* Number of RX descriptors */ |
367 |
#define NUM_TX_DESC 8 /* Number of TX descriptors */ |
#define NUM_TX_DESC 2 /* Number of TX descriptors */ |
368 |
#define RX_BUFF_SZ 1536 /* Buffer size for each Rx buffer */ |
#define RX_BUFF_SZ 1536 /* Buffer size for each Rx buffer */ |
369 |
#define TX_BUFF_SZ 1536 /* Buffer size for each Tx buffer */ |
#define TX_BUFF_SZ 1536 /* Buffer size for each Tx buffer */ |
370 |
|
|
|
#define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */ |
|
|
#define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */ |
|
|
|
|
371 |
/* |
/* |
372 |
** ISA Bus defines |
** ISA Bus defines |
373 |
*/ |
*/ |
438 |
*/ |
*/ |
439 |
struct depca_init { |
struct depca_init { |
440 |
u16 mode; /* Mode register */ |
u16 mode; /* Mode register */ |
441 |
u8 phys_addr[ETHER_ADDR_SIZE]; /* Physical ethernet address */ |
u8 phys_addr[ETH_ALEN]; /* Physical ethernet address */ |
442 |
u8 mcast_table[8]; /* Multicast Hash Table. */ |
u8 mcast_table[8]; /* Multicast Hash Table. */ |
443 |
u32 rx_ring; /* Rx ring base pointer & ring length */ |
u32 rx_ring; /* Rx ring base pointer & ring length */ |
444 |
u32 tx_ring; /* Tx ring base pointer & ring length */ |
u32 tx_ring; /* Tx ring base pointer & ring length */ |
445 |
}; |
}; |
446 |
|
|
447 |
/* |
struct depca_private { |
448 |
** The transmit ring full condition is described by the tx_old and tx_new |
struct depca_rx_desc *rx_ring; |
449 |
** pointers by: |
struct depca_tx_desc *tx_ring; |
450 |
** tx_old = tx_new Empty ring |
struct depca_init init_block; /* Shadow init block */ |
451 |
** tx_old = tx_new+1 Full ring |
char *rx_memcpy[NUM_RX_DESC]; |
452 |
** tx_old+txRingMask = tx_new Full ring (wrapped condition) |
char *tx_memcpy[NUM_TX_DESC]; |
453 |
*/ |
u32 bus_offset; /* ISA bus address offset */ |
454 |
#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\ |
u32 sh_mem; /* address of shared mem */ |
455 |
lp->tx_old+lp->txRingMask-lp->tx_new:\ |
u32 dma_buffs; /* Rx & Tx buffer start */ |
456 |
lp->tx_old -lp->tx_new-1) |
int rx_cur, tx_cur; /* Next free ring entry */ |
457 |
|
int txRingMask, rxRingMask; |
458 |
|
s32 rx_rlen, tx_rlen; |
459 |
|
/* log2([rt]xRingMask+1) for the descriptors */ |
460 |
|
}; |
461 |
|
|
462 |
static Address mem_start = DEPCA_RAM_BASE; |
static Address mem_start = DEPCA_RAM_BASE; |
463 |
|
static Address mem_len, offset; |
464 |
static unsigned short ioaddr = 0; |
static unsigned short ioaddr = 0; |
465 |
|
static struct depca_private lp; |
466 |
|
|
467 |
/* |
/* |
468 |
** Miscellaneous defines... |
** Miscellaneous defines... |
471 |
outw(CSR0, DEPCA_ADDR);\ |
outw(CSR0, DEPCA_ADDR);\ |
472 |
outw(STOP, DEPCA_DATA) |
outw(STOP, DEPCA_DATA) |
473 |
|
|
474 |
|
/* Initialize the lance Rx and Tx descriptor rings. */ |
475 |
|
static void depca_init_ring(struct nic *nic) |
476 |
|
{ |
477 |
|
int i; |
478 |
|
u32 p; |
479 |
|
|
480 |
|
lp.rx_cur = lp.tx_cur = 0; |
481 |
|
/* Initialize the base addresses and length of each buffer in the ring */ |
482 |
|
for (i = 0; i <= lp.rxRingMask; i++) { |
483 |
|
writel((p = lp.dma_buffs + i * RX_BUFF_SZ) | R_OWN, &lp.rx_ring[i].base); |
484 |
|
writew(-RX_BUFF_SZ, &lp.rx_ring[i].buf_length); |
485 |
|
lp.rx_memcpy[i] = (char *) (p + lp.bus_offset); |
486 |
|
} |
487 |
|
for (i = 0; i <= lp.txRingMask; i++) { |
488 |
|
writel((p = lp.dma_buffs + (i + lp.txRingMask + 1) * TX_BUFF_SZ) & 0x00ffffff, &lp.tx_ring[i].base); |
489 |
|
lp.tx_memcpy[i] = (char *) (p + lp.bus_offset); |
490 |
|
} |
491 |
|
|
492 |
|
/* Set up the initialization block */ |
493 |
|
lp.init_block.rx_ring = ((u32) ((u32) lp.rx_ring) & LA_MASK) | lp.rx_rlen; |
494 |
|
lp.init_block.tx_ring = ((u32) ((u32) lp.tx_ring) & LA_MASK) | lp.tx_rlen; |
495 |
|
for (i = 0; i < ETH_ALEN; i++) |
496 |
|
lp.init_block.phys_addr[i] = nic->node_addr[i]; |
497 |
|
lp.init_block.mode = 0x0000; /* Enable the Tx and Rx */ |
498 |
|
memset(lp.init_block.mcast_table, 0, sizeof(lp.init_block.mcast_table)); |
499 |
|
} |
500 |
|
|
501 |
|
static void LoadCSRs(void) |
502 |
|
{ |
503 |
|
outw(CSR1, DEPCA_ADDR); /* initialisation block address LSW */ |
504 |
|
outw((u16) (lp.sh_mem & LA_MASK), DEPCA_DATA); |
505 |
|
outw(CSR2, DEPCA_ADDR); /* initialisation block address MSW */ |
506 |
|
outw((u16) ((lp.sh_mem & LA_MASK) >> 16), DEPCA_DATA); |
507 |
|
outw(CSR3, DEPCA_ADDR); /* ALE control */ |
508 |
|
outw(ACON, DEPCA_DATA); |
509 |
|
outw(CSR0, DEPCA_ADDR); /* Point back to CSR0 */ |
510 |
|
} |
511 |
|
|
512 |
|
static int InitRestartDepca(void) |
513 |
|
{ |
514 |
|
int i; |
515 |
|
|
516 |
|
/* Copy the shadow init_block to shared memory */ |
517 |
|
memcpy_toio((char *)lp.sh_mem, &lp.init_block, sizeof(struct depca_init)); |
518 |
|
outw(CSR0, DEPCA_ADDR); /* point back to CSR0 */ |
519 |
|
outw(INIT, DEPCA_DATA); /* initialise DEPCA */ |
520 |
|
|
521 |
|
for (i = 0; i < 100 && !(inw(DEPCA_DATA) & IDON); i++) |
522 |
|
; |
523 |
|
if (i < 100) { |
524 |
|
/* clear IDON by writing a 1, and start LANCE */ |
525 |
|
outw(IDON | STRT, DEPCA_DATA); |
526 |
|
} else { |
527 |
|
printf("DEPCA not initialised\n"); |
528 |
|
return (1); |
529 |
|
} |
530 |
|
return (0); |
531 |
|
} |
532 |
|
|
533 |
/************************************************************************** |
/************************************************************************** |
534 |
RESET - Reset adapter |
RESET - Reset adapter |
536 |
static void depca_reset(struct nic *nic) |
static void depca_reset(struct nic *nic) |
537 |
{ |
{ |
538 |
s16 nicsr; |
s16 nicsr; |
539 |
int status = 0; |
int i, j; |
540 |
|
|
541 |
STOP_DEPCA; |
STOP_DEPCA; |
542 |
nicsr = inb(DEPCA_NICSR); |
nicsr = inb(DEPCA_NICSR); |
543 |
|
nicsr = ((nicsr & ~SHE & ~RBE & ~IEN) | IM); |
544 |
|
outb(nicsr, DEPCA_NICSR); |
545 |
|
if (inw(DEPCA_DATA) != STOP) |
546 |
|
{ |
547 |
|
printf("depca: Cannot stop NIC\n"); |
548 |
|
return; |
549 |
|
} |
550 |
|
|
551 |
/* non-DEPCA need this */ |
/* Initialisation block */ |
552 |
if (adapter != DEPCA) |
lp.sh_mem = mem_start; |
553 |
outb(nicsr | SHE, DEPCA_NICSR); |
mem_start += sizeof(struct depca_init); |
554 |
|
/* Tx & Rx descriptors (aligned to a quadword boundary) */ |
555 |
|
mem_start = (mem_start + ALIGN) & ~ALIGN; |
556 |
|
lp.rx_ring = (struct depca_rx_desc *) mem_start; |
557 |
|
mem_start += (sizeof(struct depca_rx_desc) * NUM_RX_DESC); |
558 |
|
lp.tx_ring = (struct depca_tx_desc *) mem_start; |
559 |
|
mem_start += (sizeof(struct depca_tx_desc) * NUM_TX_DESC); |
560 |
|
|
561 |
|
lp.bus_offset = mem_start & 0x00ff0000; |
562 |
|
/* LANCE re-mapped start address */ |
563 |
|
lp.dma_buffs = mem_start & LA_MASK; |
564 |
|
|
565 |
|
/* Finish initialising the ring information. */ |
566 |
|
lp.rxRingMask = NUM_RX_DESC - 1; |
567 |
|
lp.txRingMask = NUM_TX_DESC - 1; |
568 |
|
|
569 |
|
/* Calculate Tx/Rx RLEN size for the descriptors. */ |
570 |
|
for (i = 0, j = lp.rxRingMask; j > 0; i++) { |
571 |
|
j >>= 1; |
572 |
|
} |
573 |
|
lp.rx_rlen = (s32) (i << 29); |
574 |
|
for (i = 0, j = lp.txRingMask; j > 0; i++) { |
575 |
|
j >>= 1; |
576 |
|
} |
577 |
|
lp.tx_rlen = (s32) (i << 29); |
578 |
|
|
579 |
|
/* Load the initialisation block */ |
580 |
|
depca_init_ring(nic); |
581 |
|
LoadCSRs(); |
582 |
|
InitRestartDepca(); |
583 |
} |
} |
584 |
|
|
585 |
/************************************************************************** |
/************************************************************************** |
587 |
***************************************************************************/ |
***************************************************************************/ |
588 |
static int depca_poll(struct nic *nic) |
static int depca_poll(struct nic *nic) |
589 |
{ |
{ |
590 |
/* return true if there's an ethernet packet ready to read */ |
int entry; |
591 |
/* nic->packet should contain data on return */ |
u32 status; |
592 |
/* nic->packetlen should contain length of data */ |
|
593 |
return 0; |
entry = lp.rx_cur; |
594 |
|
if ((status = readl(&lp.rx_ring[entry].base) & R_OWN)) |
595 |
|
return (0); |
596 |
|
memcpy(nic->packet, lp.rx_memcpy[entry], nic->packetlen = lp.rx_ring[entry].msg_length); |
597 |
|
lp.rx_ring[entry].base |= R_OWN; |
598 |
|
lp.rx_cur = (++lp.rx_cur) & lp.rxRingMask; |
599 |
|
return (1); |
600 |
} |
} |
601 |
|
|
602 |
/************************************************************************** |
/************************************************************************** |
609 |
unsigned int s, /* size */ |
unsigned int s, /* size */ |
610 |
const char *p) /* Packet */ |
const char *p) /* Packet */ |
611 |
{ |
{ |
612 |
|
int entry, len; |
613 |
|
char *mem; |
614 |
|
|
615 |
/* send the packet to destination */ |
/* send the packet to destination */ |
616 |
|
/* |
617 |
|
** Caution: the right order is important here... dont |
618 |
|
** setup the ownership rights until all the other |
619 |
|
** information is in place |
620 |
|
*/ |
621 |
|
mem = lp.tx_memcpy[entry = lp.tx_cur]; |
622 |
|
memcpy_toio(mem, d, ETH_ALEN); |
623 |
|
memcpy_toio(mem + ETH_ALEN, nic->node_addr, ETH_ALEN); |
624 |
|
mem[ETH_ALEN * 2] = t >> 8; |
625 |
|
mem[ETH_ALEN * 2 + 1] = t; |
626 |
|
memcpy_toio(mem + ETH_HLEN, p, s); |
627 |
|
s += ETH_HLEN; |
628 |
|
len = (s < ETH_ZLEN ? ETH_ZLEN : s); |
629 |
|
/* clean out flags */ |
630 |
|
writel(readl(&lp.tx_ring[entry].base) & ~T_FLAGS, &lp.tx_ring[entry].base); |
631 |
|
/* clears other error flags */ |
632 |
|
writew(0x0000, &lp.tx_ring[entry].misc); |
633 |
|
/* packet length in buffer */ |
634 |
|
writew(-len, &lp.tx_ring[entry].length); |
635 |
|
/* start and end of packet, ownership */ |
636 |
|
writel(readl(&lp.tx_ring[entry].base) | (T_STP|T_ENP|T_OWN), &lp.tx_ring[entry].base); |
637 |
|
/* update current pointers */ |
638 |
|
lp.tx_cur = (++lp.tx_cur) & lp.txRingMask; |
639 |
} |
} |
640 |
|
|
641 |
/************************************************************************** |
/************************************************************************** |
643 |
***************************************************************************/ |
***************************************************************************/ |
644 |
static void depca_disable(struct nic *nic) |
static void depca_disable(struct nic *nic) |
645 |
{ |
{ |
646 |
|
STOP_DEPCA; |
647 |
} |
} |
648 |
|
|
649 |
/* |
/* |
669 |
u8 sig[] = { 0xFF, 0x00, 0x55, 0xAA, 0xFF, 0x00, 0x55, 0xAA }; |
u8 sig[] = { 0xFF, 0x00, 0x55, 0xAA, 0xFF, 0x00, 0x55, 0xAA }; |
670 |
int i, j; |
int i, j; |
671 |
long sum, chksum; |
long sum, chksum; |
|
Address mem_len, offset; |
|
672 |
|
|
673 |
data = inb(DEPCA_PROM); /* clear counter on DEPCA */ |
data = inb(DEPCA_PROM); /* clear counter on DEPCA */ |
674 |
data = inb(DEPCA_PROM); /* read data */ |
data = inb(DEPCA_PROM); /* read data */ |
715 |
nicsr &= ~BS; |
nicsr &= ~BS; |
716 |
mem_len -= (32 << 10); |
mem_len -= (32 << 10); |
717 |
} |
} |
718 |
if (adapter != DEPCA) |
if (adapter != DEPCA) /* enable shadow RAM */ |
719 |
outb(nicsr |= SHE, DEPCA_NICSR); |
outb(nicsr |= SHE, DEPCA_NICSR); |
720 |
printf("%s base 0x%x, memory [0x%X-0x%X], addr ", adapter_name[adapter], |
printf("%s base %#hX, memory [%#hX-%#hX], addr %!", |
721 |
ioaddr, mem_start, mem_start + mem_len); |
adapter_name[adapter], ioaddr, mem_start, mem_start + mem_len, |
722 |
for (i = 0; i < ETHER_ADDR_SIZE; i++) { |
nic->node_addr); |
|
if (i != 0) |
|
|
putchar(':'); |
|
|
printf("%b", nic->node_addr[i]); |
|
|
} |
|
723 |
if (sum != chksum) |
if (sum != chksum) |
724 |
printf(" (bad checksum)"); |
printf(" (bad checksum)"); |
725 |
printf("\n"); |
putchar('\n'); |
726 |
return (1); |
return (1); |
727 |
} |
} |
728 |
|
|
734 |
static unsigned short base[] = DEPCA_IO_PORTS; |
static unsigned short base[] = DEPCA_IO_PORTS; |
735 |
int i; |
int i; |
736 |
|
|
|
printf("DEPCA driver not fully functional, only probe working...\n"); |
|
737 |
if (probe_addrs == 0 || probe_addrs[0] == 0) |
if (probe_addrs == 0 || probe_addrs[0] == 0) |
738 |
probe_addrs = base; /* Use defaults */ |
probe_addrs = base; /* Use defaults */ |
739 |
for (i = 0; (ioaddr = base[i]) != 0; ++i) { |
for (i = 0; (ioaddr = base[i]) != 0; ++i) { |
740 |
if (depca_probe1(nic)) |
if (depca_probe1(nic)) |
741 |
break; |
break; |
742 |
} |
} |
743 |
if (ioaddr != 0) { |
if (ioaddr == 0) |
744 |
depca_reset(nic); |
return (0); |
745 |
/* point to NIC specific routines */ |
depca_reset(nic); |
746 |
nic->reset = depca_reset; |
/* point to NIC specific routines */ |
747 |
nic->poll = depca_poll; |
nic->reset = depca_reset; |
748 |
nic->transmit = depca_transmit; |
nic->poll = depca_poll; |
749 |
nic->disable = depca_disable; |
nic->transmit = depca_transmit; |
750 |
return nic; |
nic->disable = depca_disable; |
751 |
} |
return (nic); |
|
return 0; |
|
752 |
} |
} |