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/* mips.h. Mips opcode list for GDB, the GNU debugger. |
/* mips.h. Mips opcode list for GDB, the GNU debugger. |
2 |
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
3 |
|
2003, 2004, 2005 |
4 |
Free Software Foundation, Inc. |
Free Software Foundation, Inc. |
5 |
Contributed by Ralph Campbell and OSF |
Contributed by Ralph Campbell and OSF |
6 |
Commented and modified by Ian Lance Taylor, Cygnus Support |
Commented and modified by Ian Lance Taylor, Cygnus Support |
138 |
#define OP_MASK_ALN 0x7 |
#define OP_MASK_ALN 0x7 |
139 |
#define OP_SH_VSEL 21 |
#define OP_SH_VSEL 21 |
140 |
#define OP_MASK_VSEL 0x1f |
#define OP_MASK_VSEL 0x1f |
141 |
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#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
142 |
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but 0x8-0xf don't select bytes. */ |
143 |
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#define OP_SH_VECBYTE 22 |
144 |
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#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ |
145 |
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#define OP_SH_VECALIGN 21 |
146 |
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#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
147 |
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#define OP_SH_INSMSB 11 |
148 |
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#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ |
149 |
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#define OP_SH_EXTMSBD 11 |
150 |
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151 |
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#define OP_OP_COP0 0x10 |
152 |
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#define OP_OP_COP1 0x11 |
153 |
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#define OP_OP_COP2 0x12 |
154 |
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#define OP_OP_COP3 0x13 |
155 |
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#define OP_OP_LWC1 0x31 |
156 |
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#define OP_OP_LWC2 0x32 |
157 |
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#define OP_OP_LWC3 0x33 /* a.k.a. pref */ |
158 |
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#define OP_OP_LDC1 0x35 |
159 |
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#define OP_OP_LDC2 0x36 |
160 |
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#define OP_OP_LDC3 0x37 /* a.k.a. ld */ |
161 |
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#define OP_OP_SWC1 0x39 |
162 |
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#define OP_OP_SWC2 0x3a |
163 |
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#define OP_OP_SWC3 0x3b |
164 |
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#define OP_OP_SDC1 0x3d |
165 |
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#define OP_OP_SDC2 0x3e |
166 |
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#define OP_OP_SDC3 0x3f /* a.k.a. sd */ |
167 |
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|
168 |
/* Values in the 'VSEL' field. */ |
/* Values in the 'VSEL' field. */ |
169 |
#define MDMX_FMTSEL_IMM_QH 0x1d |
#define MDMX_FMTSEL_IMM_QH 0x1d |
193 |
of bits describing the instruction, notably any relevant hazard |
of bits describing the instruction, notably any relevant hazard |
194 |
information. */ |
information. */ |
195 |
unsigned long pinfo; |
unsigned long pinfo; |
196 |
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/* A collection of additional bits describing the instruction. */ |
197 |
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unsigned long pinfo2; |
198 |
/* A collection of bits describing the instruction sets of which this |
/* A collection of bits describing the instruction sets of which this |
199 |
instruction or macro is a member. */ |
instruction or macro is a member. */ |
200 |
unsigned long membership; |
unsigned long membership; |
201 |
}; |
}; |
202 |
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|
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/* These are the characters which may appears in the args field of an |
/* These are the characters which may appear in the args field of an |
204 |
instruction. They appear in the order in which the fields appear |
instruction. They appear in the order in which the fields appear |
205 |
when the instruction is used. Commas and parentheses in the args |
when the instruction is used. Commas and parentheses in the args |
206 |
string are ignored when assembling, and written into the output |
string are ignored when assembling, and written into the output |
218 |
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE) |
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE) |
219 |
"j" 16 bit signed immediate (OP_*_DELTA) |
"j" 16 bit signed immediate (OP_*_DELTA) |
220 |
"k" 5 bit cache opcode in target register position (OP_*_CACHE) |
"k" 5 bit cache opcode in target register position (OP_*_CACHE) |
221 |
|
Also used for immediate operands in vr5400 vector insns. |
222 |
"o" 16 bit signed offset (OP_*_DELTA) |
"o" 16 bit signed offset (OP_*_DELTA) |
223 |
"p" 16 bit PC relative branch target address (OP_*_DELTA) |
"p" 16 bit PC relative branch target address (OP_*_DELTA) |
224 |
"q" 10 bit extra breakpoint code (OP_*_CODE2) |
"q" 10 bit extra breakpoint code (OP_*_CODE2) |
235 |
"J" 19 bit wait function code (OP_*_CODE19) |
"J" 19 bit wait function code (OP_*_CODE19) |
236 |
"x" accept and ignore register name |
"x" accept and ignore register name |
237 |
"z" must be zero register |
"z" must be zero register |
238 |
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"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) |
239 |
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"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). |
240 |
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Enforces: 0 <= pos < 32. |
241 |
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"+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). |
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Requires that "+A" or "+E" occur first to set position. |
243 |
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Enforces: 0 < (pos+size) <= 32. |
244 |
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"+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). |
245 |
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Requires that "+A" or "+E" occur first to set position. |
246 |
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Enforces: 0 < (pos+size) <= 32. |
247 |
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(Also used by "dext" w/ different limits, but limits for |
248 |
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that are checked by the M_DEXT macro.) |
249 |
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"+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). |
250 |
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Enforces: 32 <= pos < 64. |
251 |
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"+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). |
252 |
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Requires that "+A" or "+E" occur first to set position. |
253 |
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Enforces: 32 < (pos+size) <= 64. |
254 |
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"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). |
255 |
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Requires that "+A" or "+E" occur first to set position. |
256 |
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Enforces: 32 < (pos+size) <= 64. |
257 |
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"+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). |
258 |
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Requires that "+A" or "+E" occur first to set position. |
259 |
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Enforces: 32 < (pos+size) <= 64. |
260 |
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|
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Floating point instructions: |
Floating point instructions: |
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"D" 5 bit destination register (OP_*_FD) |
"D" 5 bit destination register (OP_*_FD) |
273 |
"G" 5 bit destination register (OP_*_RD) |
"G" 5 bit destination register (OP_*_RD) |
274 |
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) |
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) |
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"P" 5 bit performance-monitor register (OP_*_PERFREG) |
"P" 5 bit performance-monitor register (OP_*_PERFREG) |
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"e" 5 bit vector register byte specifier (OP_*_VECBYTE) |
277 |
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"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) |
278 |
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see also "k" above |
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"+D" Combined destination register ("G") and sel ("H") for CP0 ops, |
280 |
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for pretty-printing in disassembly only. |
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|
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Macro instructions: |
Macro instructions: |
283 |
"A" General 32 bit expression |
"A" General 32 bit expression |
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"I" 32 bit immediate |
"I" 32 bit immediate (value placed in imm_expr). |
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"+I" 32 bit immediate (value placed in imm2_expr). |
286 |
"F" 64 bit floating point constant in .rdata |
"F" 64 bit floating point constant in .rdata |
287 |
"L" 64 bit floating point constant in .lit8 |
"L" 64 bit floating point constant in .lit8 |
288 |
"f" 32 bit floating point constant |
"f" 32 bit floating point constant |
299 |
Other: |
Other: |
300 |
"()" parens surrounding optional value |
"()" parens surrounding optional value |
301 |
"," separates operands |
"," separates operands |
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"[]" brackets around index for vector-op scalar operand specifier (vr5400) |
303 |
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"+" Start of extension sequence. |
304 |
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|
305 |
Characters used so far, for quick reference when adding more: |
Characters used so far, for quick reference when adding more: |
306 |
"<>()," |
"%[]<>(),+" |
307 |
"ABCDEFGHIJLMNOPQRSTUVWXYZ" |
"ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
308 |
"abcdfhijklopqrstuvwxz" |
"abcdefhijklopqrstuvwxz" |
309 |
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|
310 |
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Extension character sequences used so far ("+" followed by the |
311 |
|
following), for quick reference when adding more: |
312 |
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"ABCDEFGHI" |
313 |
*/ |
*/ |
314 |
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|
315 |
/* These are the bits which may be set in the pinfo field of an |
/* These are the bits which may be set in the pinfo field of an |
379 |
#define INSN_MULT 0x40000000 |
#define INSN_MULT 0x40000000 |
380 |
/* Instruction synchronize shared memory. */ |
/* Instruction synchronize shared memory. */ |
381 |
#define INSN_SYNC 0x80000000 |
#define INSN_SYNC 0x80000000 |
382 |
/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */ |
|
383 |
#define INSN_READ_MDMX_ACC 0 |
/* These are the bits which may be set in the pinfo2 field of an |
384 |
/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */ |
instruction. */ |
385 |
#define INSN_WRITE_MDMX_ACC 0 |
|
386 |
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/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ |
387 |
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#define INSN2_ALIAS 0x00000001 |
388 |
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/* Instruction reads MDMX accumulator. */ |
389 |
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#define INSN2_READ_MDMX_ACC 0x00000002 |
390 |
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/* Instruction writes MDMX accumulator. */ |
391 |
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#define INSN2_WRITE_MDMX_ACC 0x00000004 |
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/* Instruction is actually a macro. It should be ignored by the |
/* Instruction is actually a macro. It should be ignored by the |
394 |
disassembler, and requires special treatment by the assembler. */ |
disassembler, and requires special treatment by the assembler. */ |
396 |
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|
397 |
/* Masks used to mark instructions to indicate which MIPS ISA level |
/* Masks used to mark instructions to indicate which MIPS ISA level |
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they were introduced in. ISAs, as defined below, are logical |
they were introduced in. ISAs, as defined below, are logical |
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ORs of these bits, indicatingthat they support the instructions |
ORs of these bits, indicating that they support the instructions |
400 |
defined at the given level. */ |
defined at the given level. */ |
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|
402 |
#define INSN_ISA_MASK 0x00000fff |
#define INSN_ISA_MASK 0x00000fff |
403 |
#define INSN_ISA1 0x00000010 |
#define INSN_ISA1 0x00000001 |
404 |
#define INSN_ISA2 0x00000020 |
#define INSN_ISA2 0x00000002 |
405 |
#define INSN_ISA3 0x00000040 |
#define INSN_ISA3 0x00000004 |
406 |
#define INSN_ISA4 0x00000080 |
#define INSN_ISA4 0x00000008 |
407 |
#define INSN_ISA5 0x00000100 |
#define INSN_ISA5 0x00000010 |
408 |
#define INSN_ISA32 0x00000200 |
#define INSN_ISA32 0x00000020 |
409 |
#define INSN_ISA64 0x00000400 |
#define INSN_ISA64 0x00000040 |
410 |
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#define INSN_ISA32R2 0x00000080 |
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#define INSN_ISA64R2 0x00000100 |
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|
413 |
/* Masks used for MIPS-defined ASEs. */ |
/* Masks used for MIPS-defined ASEs. */ |
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#define INSN_ASE_MASK 0x0000f000 |
#define INSN_ASE_MASK 0x0000f000 |
434 |
#define INSN_10000 0x00100000 |
#define INSN_10000 0x00100000 |
435 |
/* Broadcom SB-1 instruction. */ |
/* Broadcom SB-1 instruction. */ |
436 |
#define INSN_SB1 0x00200000 |
#define INSN_SB1 0x00200000 |
437 |
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/* NEC VR4111/VR4181 instruction. */ |
438 |
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#define INSN_4111 0x00400000 |
439 |
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/* NEC VR4120 instruction. */ |
440 |
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#define INSN_4120 0x00800000 |
441 |
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/* NEC VR5400 instruction. */ |
442 |
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#define INSN_5400 0x01000000 |
443 |
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/* NEC VR5500 instruction. */ |
444 |
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#define INSN_5500 0x02000000 |
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446 |
/* MIPS ISA defines, use instead of hardcoding ISA level. */ |
/* MIPS ISA defines, use instead of hardcoding ISA level. */ |
447 |
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|
451 |
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) |
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) |
452 |
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) |
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) |
453 |
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) |
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) |
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|
455 |
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) |
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) |
456 |
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) |
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) |
457 |
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458 |
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#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) |
459 |
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#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) |
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|
461 |
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|
462 |
/* CPU defines, use instead of hardcoding processor number. Keep this |
/* CPU defines, use instead of hardcoding processor number. Keep this |
463 |
in sync with bfd/archures.c in order for machine selection to work. */ |
in sync with bfd/archures.c in order for machine selection to work. */ |
464 |
#define CPU_UNKNOWN 0 /* Gas internal use. */ |
#define CPU_UNKNOWN 0 /* Gas internal use. */ |
|
#define CPU_R2000 2000 |
|
465 |
#define CPU_R3000 3000 |
#define CPU_R3000 3000 |
466 |
#define CPU_R3900 3900 |
#define CPU_R3900 3900 |
467 |
#define CPU_R4000 4000 |
#define CPU_R4000 4000 |
468 |
#define CPU_R4010 4010 |
#define CPU_R4010 4010 |
469 |
#define CPU_VR4100 4100 |
#define CPU_VR4100 4100 |
470 |
#define CPU_R4111 4111 |
#define CPU_R4111 4111 |
471 |
|
#define CPU_VR4120 4120 |
472 |
#define CPU_R4300 4300 |
#define CPU_R4300 4300 |
473 |
#define CPU_R4400 4400 |
#define CPU_R4400 4400 |
474 |
#define CPU_R4600 4600 |
#define CPU_R4600 4600 |
475 |
#define CPU_R4650 4650 |
#define CPU_R4650 4650 |
476 |
#define CPU_R5000 5000 |
#define CPU_R5000 5000 |
477 |
|
#define CPU_VR5400 5400 |
478 |
|
#define CPU_VR5500 5500 |
479 |
#define CPU_R6000 6000 |
#define CPU_R6000 6000 |
480 |
|
#define CPU_RM7000 7000 |
481 |
#define CPU_R8000 8000 |
#define CPU_R8000 8000 |
482 |
|
#define CPU_RM9000 9000 |
483 |
#define CPU_R10000 10000 |
#define CPU_R10000 10000 |
484 |
#define CPU_R12000 12000 |
#define CPU_R12000 12000 |
485 |
#define CPU_MIPS16 16 |
#define CPU_MIPS16 16 |
486 |
#define CPU_MIPS32 32 |
#define CPU_MIPS32 32 |
487 |
|
#define CPU_MIPS32R2 33 |
488 |
#define CPU_MIPS5 5 |
#define CPU_MIPS5 5 |
489 |
#define CPU_MIPS64 64 |
#define CPU_MIPS64 64 |
490 |
|
#define CPU_MIPS64R2 65 |
491 |
#define CPU_SB1 12310201 /* octal 'SB', 01. */ |
#define CPU_SB1 12310201 /* octal 'SB', 01. */ |
492 |
|
|
493 |
/* Test for membership in an ISA including chip specific ISAs. INSN |
/* Test for membership in an ISA including chip specific ISAs. INSN |
498 |
#define OPCODE_IS_MEMBER(insn, isa, cpu) \ |
#define OPCODE_IS_MEMBER(insn, isa, cpu) \ |
499 |
(((insn)->membership & isa) != 0 \ |
(((insn)->membership & isa) != 0 \ |
500 |
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ |
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ |
501 |
|
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ |
502 |
|
|| (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ |
503 |
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ |
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ |
504 |
|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ |
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ |
|
&& ((insn)->membership & INSN_4100) != 0) \ |
|
505 |
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ |
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ |
506 |
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \ |
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \ |
507 |
&& ((insn)->membership & INSN_10000) != 0) \ |
&& ((insn)->membership & INSN_10000) != 0) \ |
508 |
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ |
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ |
509 |
|
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ |
510 |
|
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ |
511 |
|
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ |
512 |
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|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ |
513 |
|| 0) /* Please keep this term for easier source merging. */ |
|| 0) /* Please keep this term for easier source merging. */ |
514 |
|
|
515 |
/* This is a list of macro expanded instructions. |
/* This is a list of macro expanded instructions. |
571 |
M_DDIV_3I, |
M_DDIV_3I, |
572 |
M_DDIVU_3, |
M_DDIVU_3, |
573 |
M_DDIVU_3I, |
M_DDIVU_3I, |
574 |
|
M_DEXT, |
575 |
|
M_DINS, |
576 |
M_DIV_3, |
M_DIV_3, |
577 |
M_DIV_3I, |
M_DIV_3I, |
578 |
M_DIVU_3, |
M_DIVU_3, |
579 |
M_DIVU_3I, |
M_DIVU_3I, |
580 |
M_DLA_AB, |
M_DLA_AB, |
581 |
|
M_DLCA_AB, |
582 |
M_DLI, |
M_DLI, |
583 |
M_DMUL, |
M_DMUL, |
584 |
M_DMUL_I, |
M_DMUL_I, |
604 |
M_LB_AB, |
M_LB_AB, |
605 |
M_LBU_A, |
M_LBU_A, |
606 |
M_LBU_AB, |
M_LBU_AB, |
607 |
|
M_LCA_AB, |
608 |
M_LD_A, |
M_LD_A, |
609 |
M_LD_OB, |
M_LD_OB, |
610 |
M_LD_AB, |
M_LD_AB, |