/[gcl]/gcl/binutils/include/opcode/m68k.h
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revision 1.1.1.1 by camm, Fri Aug 9 05:36:52 2002 UTC revision 1.2 by camm, Fri Sep 9 23:32:34 2005 UTC
# Line 1  Line 1 
1  /* Opcode table header for m680[01234]0/m6888[12]/m68851.  /* Opcode table header for m680[01234]0/m6888[12]/m68851.
2     Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001     Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
3     Free Software Foundation, Inc.     2003, 2004 Free Software Foundation, Inc.
4    
5  This file is part of GDB, GAS, and the GNU binutils.     This file is part of GDB, GAS, and the GNU binutils.
6    
7  GDB, GAS, and the GNU binutils are free software; you can redistribute     GDB, GAS, and the GNU binutils are free software; you can redistribute
8  them and/or modify them under the terms of the GNU General Public     them and/or modify them under the terms of the GNU General Public
9  License as published by the Free Software Foundation; either version     License as published by the Free Software Foundation; either version
10  1, or (at your option) any later version.     1, or (at your option) any later version.
11    
12  GDB, GAS, and the GNU binutils are distributed in the hope that they     GDB, GAS, and the GNU binutils are distributed in the hope that they
13  will be useful, but WITHOUT ANY WARRANTY; without even the implied     will be useful, but WITHOUT ANY WARRANTY; without even the implied
14  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See     warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
15  the GNU General Public License for more details.     the GNU General Public License for more details.
16    
17  You should have received a copy of the GNU General Public License     You should have received a copy of the GNU General Public License
18  along with this file; see the file COPYING.  If not, write to the Free     along with this file; see the file COPYING.  If not, write to the Free
19  Software Foundation, 59 Temple Place - Suite 330, Boston, MA     Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20  02111-1307, USA.  */     02111-1307, USA.  */
21    
22  /* These are used as bit flags for the arch field in the m68k_opcode  /* These are used as bit flags for the arch field in the m68k_opcode
23     structure.  */     structure.  */
24  #define _m68k_undef  0  #define _m68k_undef  0
25  #define m68000  0x001  #define m68000   0x001
26  #define m68008  m68000 /* synonym for -m68000.  otherwise unused. */  #define m68008   m68000 /* Synonym for -m68000.  otherwise unused.  */
27  #define m68010  0x002  #define m68010   0x002
28  #define m68020  0x004  #define m68020   0x004
29  #define m68030  0x008  #define m68030   0x008
30  #define m68ec030 m68030 /* similar enough to -m68030 to ignore differences;  #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
31                             gas will deal with the few differences.  */                             gas will deal with the few differences.  */
32  #define m68040  0x010  #define m68040   0x010
33  /* there is no 68050 */  /* There is no 68050.  */
34  #define m68060  0x020  #define m68060   0x020
35  #define m68881  0x040  #define m68881   0x040
36  #define m68882  m68881 /* synonym for -m68881.  otherwise unused. */  #define m68882   m68881 /* Synonym for -m68881.  otherwise unused.  */
37  #define m68851  0x080  #define m68851   0x080
38  #define cpu32   0x100   /* e.g., 68332 */  #define cpu32    0x100          /* e.g., 68332 */
39  #define mcf5200 0x200  
40  #define mcf5206e 0x400  #define mcfmac   0x200          /* ColdFire MAC. */
41  #define mcf5307 0x800  #define mcfemac  0x400          /* ColdFire EMAC. */
42  #define mcf5407 0x1000  #define cfloat   0x800          /* ColdFire FPU.  */
43    #define mcfhwdiv 0x1000         /* ColdFire hardware divide.  */
44   /* handy aliases */  
45  #define m68040up  (m68040 | m68060)  #define mcfisa_a 0x2000         /* ColdFire ISA_A.  */
46  #define m68030up  (m68030 | m68040up)  #define mcfisa_aa 0x4000        /* ColdFire ISA_A+.  */
47  #define m68020up  (m68020 | m68030up)  #define mcfisa_b 0x8000         /* ColdFire ISA_B.  */
48  #define m68010up  (m68010 | cpu32 | m68020up)  #define mcfusp   0x10000        /* ColdFire USP instructions.  */
49  #define m68000up  (m68000 | m68010up)  
50  #define mcf       (mcf5200 | mcf5206e | mcf5307 | mcf5407)  #define mcf5200  0x20000
51  #define mcf5307up (mcf5307 | mcf5407)  #define mcf5206e 0x40000
52    #define mcf521x  0x80000
53    #define mcf5249  0x100000
54    #define mcf528x  0x200000
55    #define mcf5307  0x400000
56    #define mcf5407  0x800000
57    #define mcf5470  0x1000000
58    #define mcf5480  0x2000000
59    
60     /* Handy aliases.  */
61    #define m68040up   (m68040 | m68060)
62    #define m68030up   (m68030 | m68040up)
63    #define m68020up   (m68020 | m68030up)
64    #define m68010up   (m68010 | cpu32 | m68020up)
65    #define m68000up   (m68000 | m68010up)
66    
67  #define mfloat  (m68881 | m68882 | m68040 | m68060)  #define mfloat  (m68881 | m68882 | m68040 | m68060)
68  #define mmmu    (m68851 | m68030 | m68040 | m68060)  #define mmmu    (m68851 | m68030 | m68040 | m68060)
# Line 59  struct m68k_opcode Line 73  struct m68k_opcode
73  {  {
74    /* The opcode name.  */    /* The opcode name.  */
75    const char *name;    const char *name;
76      /* The pseudo-size of the instruction(in bytes).  Used to determine
77         number of bytes necessary to disassemble the instruction.  */
78      unsigned int size;
79    /* The opcode itself.  */    /* The opcode itself.  */
80    unsigned long opcode;    unsigned long opcode;
81    /* The mask used by the disassembler.  */    /* The mask used by the disassembler.  */
# Line 93  struct m68k_opcode_alias Line 110  struct m68k_opcode_alias
110     operand; the second, the place it is stored.  */     operand; the second, the place it is stored.  */
111    
112  /* Kinds of operands:  /* Kinds of operands:
113     Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+-     Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
114    
115     D  data register only.  Stored as 3 bits.     D  data register only.  Stored as 3 bits.
116     A  address register only.  Stored as 3 bits.     A  address register only.  Stored as 3 bits.
# Line 127  struct m68k_opcode_alias Line 144  struct m68k_opcode_alias
144     C  the CCR.  No need to store it; this is just for filtering validity.     C  the CCR.  No need to store it; this is just for filtering validity.
145     S  the SR.  No need to store, just as with CCR.     S  the SR.  No need to store, just as with CCR.
146     U  the USP.  No need to store, just as with CCR.     U  the USP.  No need to store, just as with CCR.
147     E  the ACC.  No need to store, just as with CCR.     E  the MAC ACC.  No need to store, just as with CCR.
148     G  the MACSR.  No need to store, just as with CCR.     e  the EMAC ACC[0123].
149       G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
150       g  the EMAC ACCEXT{01,23}.
151     H  the MASK.  No need to store, just as with CCR.     H  the MASK.  No need to store, just as with CCR.
152       i  the MAC/EMAC scale factor.
153    
154     I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always     I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
155        extracted from the 'd' field of word one, which means that an extended        extracted from the 'd' field of word one, which means that an extended
# Line 141  struct m68k_opcode_alias Line 161  struct m68k_opcode_alias
161          Possible values:          Possible values:
162          0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]          0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]
163          0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]          0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]
164          0x002   CACR    Cache Control Register          [60, 40, 30, 20]          0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
165          0x003   TC      MMU Translation Control         [60, 40]          0x003   TC      MMU Translation Control         [60, 40]
166          0x004   ITT0    Instruction Transparent          0x004   ITT0    Instruction Transparent
167                                  Translation reg 0       [60, 40]                                  Translation reg 0       [60, 40]
# Line 153  struct m68k_opcode_alias Line 173  struct m68k_opcode_alias
173                                  Translation reg 1       [60, 40]                                  Translation reg 1       [60, 40]
174          0x008   BUSCR   Bus Control Register            [60]          0x008   BUSCR   Bus Control Register            [60]
175          0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]          0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]
176          0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10]          0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
177          0x802   CAAR    Cache Address Register          [        30, 20]          0x802   CAAR    Cache Address Register          [        30, 20]
178          0x803   MSP     Master Stack Pointer            [    40, 30, 20]          0x803   MSP     Master Stack Pointer            [    40, 30, 20]
179          0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]          0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]
# Line 165  struct m68k_opcode_alias Line 185  struct m68k_opcode_alias
185          0xC04   RAMBAR0 RAM Base Address Register 0     [520X]          0xC04   RAMBAR0 RAM Base Address Register 0     [520X]
186          0xC05   RAMBAR1 RAM Base Address Register 0     [520X]          0xC05   RAMBAR1 RAM Base Address Register 0     [520X]
187          0xC0F   MBAR0   RAM Base Address Register 0     [520X]          0xC0F   MBAR0   RAM Base Address Register 0     [520X]
188            0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
189            0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
190    
191      L  Register list of the type d0-d7/a0-a7 etc.      L  Register list of the type d0-d7/a0-a7 etc.
192         (New!  Improved!  Can also hold fp0-fp7, as well!)         (New!  Improved!  Can also hold fp0-fp7, as well!)
# Line 197  struct m68k_opcode_alias Line 219  struct m68k_opcode_alias
219     !  control                                   (modes 2,5,6,7.0-3)     !  control                                   (modes 2,5,6,7.0-3)
220                                                  (not 0,1,3,4,7.4)                                                  (not 0,1,3,4,7.4)
221     &  alterable control                         (modes 2,5,6,7.0,7.1)     &  alterable control                         (modes 2,5,6,7.0,7.1)
222                                                  (not 0,1,7.2-4)                                                  (not 0,1,3,4,7.2-4)
223     $  alterable data                            (modes 0,2-6,7.0,7.1)     $  alterable data                            (modes 0,2-6,7.0,7.1)
224                                                  (not 1,7.2-4)                                                  (not 1,7.2-4)
225     ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)     ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)
# Line 218  struct m68k_opcode_alias Line 240  struct m68k_opcode_alias
240     coldfire bset/bclr/btst/mulsl/mulul operands:     coldfire bset/bclr/btst/mulsl/mulul operands:
241     q                                            (modes 0,2-5)     q                                            (modes 0,2-5)
242     v                                            (modes 0,2-5,7.0,7.1)     v                                            (modes 0,2-5,7.0,7.1)
243  */     b                                            (modes 0,2-5,7.2)
244       w                                            (modes 2-5,7.2)
245       y                                            (modes 2,5)
246       z                                            (modes 2,5,7.2)
247       x  mov3q immediate operand.
248       4                                            (modes 2,3,4,5)
249      */
250    
251  /* For the 68851: */  /* For the 68851:  */
252  /*  /* I didn't use much imagination in choosing the
    I didn't use much imagination in choosing the  
253     following codes, so many of them aren't very     following codes, so many of them aren't very
254     mnemonic. -rab     mnemonic. -rab
255    
# Line 272  struct m68k_opcode_alias Line 299  struct m68k_opcode_alias
299  */  */
300    
301  /* Places to put an operand, for non-general operands:  /* Places to put an operand, for non-general operands:
302     Characters used: BbCcDdghijkLlMmNnostWw123456789     Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
303    
304     s  source, low bits of first word.     s  source, low bits of first word.
305     d  dest, shifted 9 in first word     d  dest, shifted 9 in first word
# Line 337  struct m68k_opcode_alias Line 364  struct m68k_opcode_alias
364     F  double precision float, low bit of 1st word, immediate uses 8 bytes     F  double precision float, low bit of 1st word, immediate uses 8 bytes
365     x  extended precision float, low bit of 1st word, immediate uses 12 bytes     x  extended precision float, low bit of 1st word, immediate uses 12 bytes
366     p  packed float, low bit of 1st word, immediate uses 12 bytes     p  packed float, low bit of 1st word, immediate uses 12 bytes
367       G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
368       H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
369       F  EMAC ACCx
370       f  EMAC ACCy
371       I  MAC/EMAC scale factor
372       /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
373       ]  first word, bit 10
374  */  */
375    
376  extern const struct m68k_opcode m68k_opcodes[];  extern const struct m68k_opcode m68k_opcodes[];

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