/[gcl]/gcl/binutils/include/opcode/i386.h
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revision 1.1.1.1 by camm, Fri Aug 9 05:36:51 2002 UTC revision 1.1.1.1.20.1 by camm, Fri Sep 30 02:10:25 2005 UTC
# Line 1  Line 1 
1  /* opcode/i386.h -- Intel 80386 opcode table  /* opcode/i386.h -- Intel 80386 opcode table
2     Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,     Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3     2000, 2001     2000, 2001, 2002, 2003, 2004, 2005
4     Free Software Foundation, Inc.     Free Software Foundation, Inc.
5    
6  This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.     This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
7    
8  This program is free software; you can redistribute it and/or modify     This program is free software; you can redistribute it and/or modify
9  it under the terms of the GNU General Public License as published by     it under the terms of the GNU General Public License as published by
10  the Free Software Foundation; either version 2 of the License, or     the Free Software Foundation; either version 2 of the License, or
11  (at your option) any later version.     (at your option) any later version.
12    
13  This program is distributed in the hope that it will be useful,     This program is distributed in the hope that it will be useful,
14  but WITHOUT ANY WARRANTY; without even the implied warranty of     but WITHOUT ANY WARRANTY; without even the implied warranty of
15  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  GNU General Public License for more details.     GNU General Public License for more details.
17    
18  You should have received a copy of the GNU General Public License     You should have received a copy of the GNU General Public License
19  along with this program; if not, write to the Free Software     along with this program; if not, write to the Free Software
20  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
21    
22  /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived  /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
23     ix86 Unix assemblers, generate floating point instructions with     ix86 Unix assemblers, generate floating point instructions with
# Line 48  Foundation, Inc., 59 Temple Place - Suit Line 48  Foundation, Inc., 59 Temple Place - Suit
48  #define OLDGCC_COMPAT SYSV386_COMPAT  #define OLDGCC_COMPAT SYSV386_COMPAT
49  #endif  #endif
50    
51  static const template i386_optab[] = {  static const template i386_optab[] =
52    {
53    
54  #define X None  #define X None
55  #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)  #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
# Line 64  static const template i386_optab[] = { Line 65  static const template i386_optab[] = {
65  #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)  #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
66  #define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)  #define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
67  #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)  #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
 #define sldx_Suf (No_bSuf|No_wSuf|No_qSuf)  
68  #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)  #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
69  #define bwlq_Suf (No_sSuf|No_xSuf)  #define bwlq_Suf (No_sSuf|No_xSuf)
70  #define FP (NoSuf|IgnoreSize)  #define FP (NoSuf)
71  #define l_FP (l_Suf|IgnoreSize)  #define l_FP (l_Suf)
72  #define x_FP (x_Suf|IgnoreSize)  #define q_FP (q_Suf|NoRex64)
73  #define sl_FP (sl_Suf|IgnoreSize)  #define x_FP (x_Suf|FloatMF)
74    #define sl_FP (sl_Suf|FloatMF)
75  #if SYSV386_COMPAT  #if SYSV386_COMPAT
76  /* Someone forgot that the FloatR bit reverses the operation when not  /* Someone forgot that the FloatR bit reverses the operation when not
77     equal to the FloatD bit.  ie. Changing only FloatD results in the     equal to the FloatD bit.  ie. Changing only FloatD results in the
# Line 84  static const template i386_optab[] = { Line 85  static const template i386_optab[] = {
85  #define MOV_AX_DISP32 0xa0  #define MOV_AX_DISP32 0xa0
86  /* In the 64bit mode the short form mov immediate is redefined to have  /* In the 64bit mode the short form mov immediate is redefined to have
87     64bit displacement value.  */     64bit displacement value.  */
88  { "mov",   2,   0xa0, X, CpuNo64,bwlq_Suf|D|W,                  { Disp16|Disp32, Acc, 0 } },  { "mov",   2,   0xa0, X, CpuNo64,bwl_Suf|D|W,                   { Disp16|Disp32, Acc, 0 } },
89  { "mov",   2,   0x88, X, 0,      bwlq_Suf|D|W|Modrm,            { Reg, Reg|AnyMem, 0} },  { "mov",   2,   0x88, X, 0,      bwlq_Suf|D|W|Modrm,            { Reg, Reg|AnyMem, 0} },
90  /* In the 64bit mode the short form mov immediate is redefined to have  /* In the 64bit mode the short form mov immediate is redefined to have
91     64bit displacement value.  */     64bit displacement value.  */
# Line 96  static const template i386_optab[] = { Line 97  static const template i386_optab[] = {
97     size prefix.  When moving to a 32 bit register, the upper 16 bits     size prefix.  When moving to a 32 bit register, the upper 16 bits
98     are set to an implementation defined value (on the Pentium Pro,     are set to an implementation defined value (on the Pentium Pro,
99     the implementation defined value is zero).  */     the implementation defined value is zero).  */
100  { "mov",   2,   0x8c, X, 0,      wl_Suf|Modrm,                  { SReg2, WordReg|WordMem, 0 } },  { "mov",   2,   0x8c, X, 0,      wl_Suf|Modrm,                  { SReg2, WordReg|InvMem, 0 } },
101  { "mov",   2,   0x8c, X, Cpu386, wl_Suf|Modrm,                  { SReg3, WordReg|WordMem, 0 } },  { "mov",   2,   0x8c, X, 0,      wl_Suf|Modrm|IgnoreSize,       { SReg2, WordMem, 0 } },
102    { "mov",   2,   0x8c, X, Cpu386, wl_Suf|Modrm,                  { SReg3, WordReg|InvMem, 0 } },
103    { "mov",   2,   0x8c, X, Cpu386, wl_Suf|Modrm|IgnoreSize,       { SReg3, WordMem, 0 } },
104  { "mov",   2,   0x8e, X, 0,      wl_Suf|Modrm|IgnoreSize,       { WordReg|WordMem, SReg2, 0 } },  { "mov",   2,   0x8e, X, 0,      wl_Suf|Modrm|IgnoreSize,       { WordReg|WordMem, SReg2, 0 } },
105  { "mov",   2,   0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize,       { WordReg|WordMem, SReg3, 0 } },  { "mov",   2,   0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize,       { WordReg|WordMem, SReg3, 0 } },
106  /* Move to/from control debug registers.  In the 16 or 32bit modes they are 32bit.  In the 64bit  /* Move to/from control debug registers.  In the 16 or 32bit modes they are 32bit.  In the 64bit
# Line 106  static const template i386_optab[] = { Line 109  static const template i386_optab[] = {
109  { "mov",   2, 0x0f20, X, Cpu64,  q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },  { "mov",   2, 0x0f20, X, Cpu64,  q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },
110  { "mov",   2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} },  { "mov",   2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} },
111  { "mov",   2, 0x0f21, X, Cpu64,  q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },  { "mov",   2, 0x0f21, X, Cpu64,  q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },
112  { "mov",   2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize,      { Test, Reg32|InvMem, 0} },  { "mov",   2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,      { Test, Reg32|InvMem, 0} },
113  { "movabs",2,   0xa0, X, Cpu64, bwlq_Suf|D|W,                   { Disp64, Acc, 0 } },  { "movabs",2,   0xa0, X, Cpu64, bwlq_Suf|D|W,                   { Disp64, Acc, 0 } },
114  { "movabs",2,   0xb0, X, Cpu64, q_Suf|W|ShortForm,              { Imm64, Reg64, 0 } },  { "movabs",2,   0xb0, X, Cpu64, q_Suf|W|ShortForm,              { Imm64, Reg64, 0 } },
115    
# Line 119  static const template i386_optab[] = { Line 122  static const template i386_optab[] = {
122  {"movsbq", 2, 0x0fbe, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg8|ByteMem, Reg64, 0} },  {"movsbq", 2, 0x0fbe, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg8|ByteMem, Reg64, 0} },
123  {"movswq", 2, 0x0fbf, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg16|ShortMem,Reg64, 0} },  {"movswq", 2, 0x0fbf, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg16|ShortMem,Reg64, 0} },
124  {"movslq", 2,   0x63, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg32|WordMem, Reg64, 0} },  {"movslq", 2,   0x63, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg32|WordMem, Reg64, 0} },
125  /* Intel Syntax next 5 insns */  /* Intel Syntax next 3 insns */
126  {"movsx",  2, 0x0fbe, X, Cpu386, b_Suf|Modrm,                   { Reg8|ByteMem, WordReg, 0} },  {"movsx",  2, 0x0fbe, X, Cpu386, b_Suf|Modrm,                   { Reg8|ByteMem, WordReg, 0} },
127  {"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm,                   { Reg16|ShortMem, Reg32, 0} },  {"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm,                   { Reg16|ShortMem, Reg32|Reg64, 0} },
 {"movsx",  2, 0x0fbe, X, Cpu64,  b_Suf|Modrm|Rex64,             { Reg8|ByteMem, Reg64, 0} },  
 {"movsx",  2, 0x0fbf, X, Cpu64,  w_Suf|Modrm|Rex64,             { Reg16|ShortMem, Reg64, 0} },  
128  {"movsx",  2,   0x63, X, Cpu64,  l_Suf|Modrm|Rex64,             { Reg32|WordMem, Reg64, 0} },  {"movsx",  2,   0x63, X, Cpu64,  l_Suf|Modrm|Rex64,             { Reg32|WordMem, Reg64, 0} },
129    
130  /* Move with zero extend.  */  /* Move with zero extend.  We can't remove "movzb" since existing
131       assembly codes may use it.  */
132  {"movzb",  2, 0x0fb6, X, Cpu386, wl_Suf|Modrm,                  { Reg8|ByteMem, WordReg, 0} },  {"movzb",  2, 0x0fb6, X, Cpu386, wl_Suf|Modrm,                  { Reg8|ByteMem, WordReg, 0} },
133    /* "movzbl" & "movzbw" should not be unified into "movzb" for
134       consistency with the sign extending moves above.  */
135    {"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm,                   { Reg8|ByteMem, Reg32, 0} },
136    {"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm,                   { Reg8|ByteMem, Reg16, 0} },
137  {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm,                   { Reg16|ShortMem, Reg32, 0} },  {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm,                   { Reg16|ShortMem, Reg32, 0} },
138  /* These instructions are not particulary usefull, since the zero extend  /* These instructions are not particulary useful, since the zero extend
139     32->64 is implicit, but we can encode them.  */     32->64 is implicit, but we can encode them.  */
140  {"movzbq", 2, 0x0fb6, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg8|ByteMem,   Reg64, 0} },  {"movzbq", 2, 0x0fb6, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg8|ByteMem,   Reg64, 0} },
141  {"movzwq", 2, 0x0fb7, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg16|ShortMem, Reg64, 0} },  {"movzwq", 2, 0x0fb7, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg16|ShortMem, Reg64, 0} },
142  /* Intel Syntax next 4 insns */  /* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful,
143       since the zero extend 32->64 is implicit, but we can encode them).  */
144  {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm,                   { Reg8|ByteMem, WordReg, 0} },  {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm,                   { Reg8|ByteMem, WordReg, 0} },
145  {"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm,                   { Reg16|ShortMem, Reg32, 0} },  {"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm,                   { Reg16|ShortMem, Reg32|Reg64, 0} },
 /* These instructions are not particulary usefull, since the zero extend  
    32->64 is implicit, but we can encode them.  */  
 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64,             { Reg8|ByteMem, Reg64, 0} },  
 {"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64,             { Reg16|ShortMem, Reg64, 0} },  
146    
147  /* Push instructions.  */  /* Push instructions.  */
148  {"push",   1,   0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },  {"push",   1,   0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
149  {"push",   1,   0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize,     { WordReg|WordMem, 0, 0 } },  {"push",   1,   0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize,     { WordReg|WordMem, 0, 0 } },
150  {"push",   1,   0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { Imm8S, 0, 0} },  {"push",   1,   0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { Imm8S, 0, 0} },
151  {"push",   1,   0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { Imm16|Imm32, 0, 0} },  {"push",   1,   0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { Imm16|Imm32, 0, 0} },
152  {"push",   1,   0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },  {"push",   1,   0x06, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
153  {"push",   1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },  {"push",   1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
154  /* In 64bit mode, the operand size is implicitly 64bit.  */  /* In 64bit mode, the operand size is implicitly 64bit.  */
155  {"push",   1,   0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } },  {"push",   1,   0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } },
156  {"push",   1,   0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } },  {"push",   1,   0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } },
157  {"push",   1,   0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },  {"push",   1,   0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
158  {"push",   1,   0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },  {"push",   1,   0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
159  {"push",   1,   0x06, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },  {"push",   1, 0x0fa0, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
 {"push",   1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },  
160    
161  {"pusha",  0,   0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { 0, 0, 0 } },  {"pusha",  0,   0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { 0, 0, 0 } },
162    
# Line 165  static const template i386_optab[] = { Line 167  static const template i386_optab[] = {
167  {"pop",    1,   0x07, X, CpuNo64,        wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },  {"pop",    1,   0x07, X, CpuNo64,        wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
168  {"pop",    1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },  {"pop",    1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
169  /* In 64bit mode, the operand size is implicitly 64bit.  */  /* In 64bit mode, the operand size is implicitly 64bit.  */
170  {"pop",    1,   0x58, X, Cpu64,  wq_Suf|ShortForm|DefaultSize|NoRex64,  { WordReg, 0, 0 } },  {"pop",    1,   0x58, X, Cpu64,  wq_Suf|ShortForm|DefaultSize|NoRex64,  { Reg16|Reg64, 0, 0 } },
171  {"pop",    1,   0x8f, 0, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64,      { WordReg|WordMem, 0, 0 } },  {"pop",    1,   0x8f, 0, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64,      { Reg16|Reg64|WordMem, 0, 0 } },
 {"pop",    1,   0x07, X, Cpu64,  wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },  
172  {"pop",    1, 0x0fa1, X, Cpu64,  wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },  {"pop",    1, 0x0fa1, X, Cpu64,  wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
173    
174  {"popa",   0,   0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,            { 0, 0, 0 } },  {"popa",   0,   0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,            { 0, 0, 0 } },
# Line 175  static const template i386_optab[] = { Line 176  static const template i386_optab[] = {
176  /* Exchange instructions.  /* Exchange instructions.
177     xchg commutes:  we allow both operand orders.     xchg commutes:  we allow both operand orders.
178    
179     In the 64bit code, xchg eax, eax is reused for new nop instruction.     In the 64bit code, xchg eax, eax is reused for new nop instruction.  */
180   */  #if 0 /* While the two entries that are disabled generate shorter code
181             for xchg eax, reg (on x86_64), the special case xchg eax, eax
182             does not get handled correctly - it degenerates into nop, but
183             that way the side effect of zero-extending eax to rax is lost.  */
184  {"xchg",   2,   0x90, X, 0,      wlq_Suf|ShortForm,     { WordReg, Acc, 0 } },  {"xchg",   2,   0x90, X, 0,      wlq_Suf|ShortForm,     { WordReg, Acc, 0 } },
185  {"xchg",   2,   0x90, X, 0,      wlq_Suf|ShortForm,     { Acc, WordReg, 0 } },  {"xchg",   2,   0x90, X, 0,      wlq_Suf|ShortForm,     { Acc, WordReg, 0 } },
186    #else
187    {"xchg",   2,   0x90, X, CpuNo64, wl_Suf|ShortForm,     { WordReg, Acc, 0 } },
188    {"xchg",   2,   0x90, X, CpuNo64, wl_Suf|ShortForm,     { Acc, WordReg, 0 } },
189    {"xchg",   2,   0x90, X, Cpu64, wq_Suf|ShortForm,       { Reg16|Reg64, Acc, 0 } },
190    {"xchg",   2,   0x90, X, Cpu64, wq_Suf|ShortForm,       { Acc, Reg16|Reg64, 0 } },
191    #endif
192  {"xchg",   2,   0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg, Reg|AnyMem, 0 } },  {"xchg",   2,   0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg, Reg|AnyMem, 0 } },
193  {"xchg",   2,   0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, Reg, 0 } },  {"xchg",   2,   0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, Reg, 0 } },
194    
195  /* In/out from ports.  */  /* In/out from ports.  */
196    /* XXX should reject %rax */
197  {"in",     2,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, Acc, 0 } },  {"in",     2,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, Acc, 0 } },
198  {"in",     2,   0xec, X, 0,      bwl_Suf|W,             { InOutPortReg, Acc, 0 } },  {"in",     2,   0xec, X, 0,      bwl_Suf|W,             { InOutPortReg, Acc, 0 } },
199  {"in",     1,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, 0, 0 } },  {"in",     1,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, 0, 0 } },
# Line 196  static const template i386_optab[] = { Line 207  static const template i386_optab[] = {
207  {"lea",    2, 0x8d,   X, 0,      wlq_Suf|Modrm,         { WordMem, WordReg, 0 } },  {"lea",    2, 0x8d,   X, 0,      wlq_Suf|Modrm,         { WordMem, WordReg, 0 } },
208    
209  /* Load segment registers from memory.  */  /* Load segment registers from memory.  */
210  {"lds",    2,   0xc5, X, CpuNo64, wlq_Suf|Modrm,        { WordMem, WordReg, 0} },  {"lds",    2,   0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} },
211  {"les",    2,   0xc4, X, CpuNo64, wlq_Suf|Modrm,        { WordMem, WordReg, 0} },  {"les",    2,   0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} },
212  {"lfs",    2, 0x0fb4, X, Cpu386, wlq_Suf|Modrm,         { WordMem, WordReg, 0} },  {"lfs",    2, 0x0fb4, X, Cpu386, wl_Suf|Modrm,          { WordMem, WordReg, 0} },
213  {"lgs",    2, 0x0fb5, X, Cpu386, wlq_Suf|Modrm,         { WordMem, WordReg, 0} },  {"lgs",    2, 0x0fb5, X, Cpu386, wl_Suf|Modrm,          { WordMem, WordReg, 0} },
214  {"lss",    2, 0x0fb2, X, Cpu386, wlq_Suf|Modrm,         { WordMem, WordReg, 0} },  {"lss",    2, 0x0fb2, X, Cpu386, wl_Suf|Modrm,          { WordMem, WordReg, 0} },
215    
216  /* Flags register instructions.  */  /* Flags register instructions.  */
217  {"clc",    0,   0xf8, X, 0,      NoSuf,                 { 0, 0, 0} },  {"clc",    0,   0xf8, X, 0,      NoSuf,                 { 0, 0, 0} },
# Line 208  static const template i386_optab[] = { Line 219  static const template i386_optab[] = {
219  {"cli",    0,   0xfa, X, 0,      NoSuf,                 { 0, 0, 0} },  {"cli",    0,   0xfa, X, 0,      NoSuf,                 { 0, 0, 0} },
220  {"clts",   0, 0x0f06, X, Cpu286, NoSuf,                 { 0, 0, 0} },  {"clts",   0, 0x0f06, X, Cpu286, NoSuf,                 { 0, 0, 0} },
221  {"cmc",    0,   0xf5, X, 0,      NoSuf,                 { 0, 0, 0} },  {"cmc",    0,   0xf5, X, 0,      NoSuf,                 { 0, 0, 0} },
222  {"lahf",   0,   0x9f, X, CpuNo64,NoSuf,                 { 0, 0, 0} },  {"lahf",   0,   0x9f, X, 0,      NoSuf,                 { 0, 0, 0} },
223  {"sahf",   0,   0x9e, X, CpuNo64,NoSuf,                 { 0, 0, 0} },  {"sahf",   0,   0x9e, X, 0,      NoSuf,                 { 0, 0, 0} },
224  {"pushf",  0,   0x9c, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },  {"pushf",  0,   0x9c, X, CpuNo64,wl_Suf|DefaultSize,    { 0, 0, 0} },
225  {"pushf",  0,   0x9c, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },  {"pushf",  0,   0x9c, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
226  {"popf",   0,   0x9d, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },  {"popf",   0,   0x9d, X, CpuNo64,wl_Suf|DefaultSize,    { 0, 0, 0} },
227  {"popf",   0,   0x9d, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },  {"popf",   0,   0x9d, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
228  {"stc",    0,   0xf9, X, 0,      NoSuf,                 { 0, 0, 0} },  {"stc",    0,   0xf9, X, 0,      NoSuf,                 { 0, 0, 0} },
229  {"std",    0,   0xfd, X, 0,      NoSuf,                 { 0, 0, 0} },  {"std",    0,   0xfd, X, 0,      NoSuf,                 { 0, 0, 0} },
# Line 276  static const template i386_optab[] = { Line 287  static const template i386_optab[] = {
287  {"neg",    1,   0xf6, 3, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },  {"neg",    1,   0xf6, 3, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
288  {"not",    1,   0xf6, 2, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },  {"not",    1,   0xf6, 2, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
289    
290  {"aaa",    0,   0x37, X, 0,      NoSuf,                 { 0, 0, 0} },  {"aaa",    0,   0x37, X, CpuNo64,        NoSuf,                 { 0, 0, 0} },
291  {"aas",    0,   0x3f, X, 0,      NoSuf,                 { 0, 0, 0} },  {"aas",    0,   0x3f, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
292  {"daa",    0,   0x27, X, 0,      NoSuf,                 { 0, 0, 0} },  {"daa",    0,   0x27, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
293  {"das",    0,   0x2f, X, 0,      NoSuf,                 { 0, 0, 0} },  {"das",    0,   0x2f, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
294  {"aad",    0, 0xd50a, X, 0,      NoSuf,                 { 0, 0, 0} },  {"aad",    0, 0xd50a, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
295  {"aad",    1,   0xd5, X, 0,      NoSuf,                 { Imm8S, 0, 0} },  {"aad",    1,   0xd5, X, CpuNo64,       NoSuf,                  { Imm8S, 0, 0} },
296  {"aam",    0, 0xd40a, X, 0,      NoSuf,                 { 0, 0, 0} },  {"aam",    0, 0xd40a, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
297  {"aam",    1,   0xd4, X, 0,      NoSuf,                 { Imm8S, 0, 0} },  {"aam",    1,   0xd4, X, CpuNo64,       NoSuf,                  { Imm8S, 0, 0} },
298    
299  /* Conversion insns.  */  /* Conversion insns.  */
300  /* Intel naming */  /* Intel naming */
# Line 370  static const template i386_optab[] = { Line 381  static const template i386_optab[] = {
381  {"shrd",   2, 0x0fad, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },  {"shrd",   2, 0x0fad, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },
382    
383  /* Control transfer instructions.  */  /* Control transfer instructions.  */
384  {"call",   1,   0xe8, X, 0,      wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },  {"call",   1,   0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
385    {"call",   1,   0xe8, X, Cpu64,  wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} },
386  {"call",   1,   0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize,     { WordReg|WordMem|JumpAbsolute, 0, 0} },  {"call",   1,   0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize,     { WordReg|WordMem|JumpAbsolute, 0, 0} },
387  {"call",   1,   0xff, 2, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} },  {"call",   1,   0xff, 2, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} },
388  /* Intel Syntax */  /* Intel Syntax */
389  {"call",   2,   0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },  {"call",   2,   0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
390  /* Intel Syntax */  /* Intel Syntax */
391  {"call",   1,   0xff, 3, 0,      x_Suf|Modrm|DefaultSize,       { WordMem, 0, 0} },  {"call",   1,   0xff, 3, 0,      x_Suf|Modrm|DefaultSize,       {WordMem|JumpAbsolute, 0, 0} },
392  {"lcall",  2,   0x9a, X, CpuNo64,        wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },  {"lcall",  2,   0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} },
393  {"lcall",  1,   0xff, 3, CpuNo64,        wl_Suf|Modrm|DefaultSize,      { WordMem|JumpAbsolute, 0, 0} },  {"lcall",  1,   0xff, 3, 0,      wl_Suf|Modrm|DefaultSize,      {WordMem|JumpAbsolute, 0, 0} },
 {"lcall",  1,   0xff, 3, Cpu64,  q_Suf|Modrm|DefaultSize|NoRex64,{ WordMem|JumpAbsolute, 0, 0} },  
394    
395  #define JUMP_PC_RELATIVE 0xeb  #define JUMP_PC_RELATIVE 0xeb
396  {"jmp",    1,   0xeb, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },  {"jmp",    1,   0xeb, X, 0,      NoSuf|Jump,            { Disp,0, 0} },
397  {"jmp",    1,   0xff, 4, CpuNo64, wl_Suf|Modrm,         { WordReg|WordMem|JumpAbsolute, 0, 0} },  {"jmp",    1,   0xff, 4, CpuNo64, wl_Suf|Modrm,         { WordReg|WordMem|JumpAbsolute, 0, 0} },
398  {"jmp",    1,   0xff, 4, Cpu64,  wq_Suf|Modrm|NoRex64,  { WordReg|WordMem|JumpAbsolute, 0, 0} },  {"jmp",    1,   0xff, 4, Cpu64,  wq_Suf|Modrm|NoRex64,  { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} },
399  /* Intel Syntax */  /* Intel Syntax.  */
400  {"jmp",    2,   0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },  {"jmp",    2,   0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
401  /* Intel Syntax */  /* Intel Syntax.  */
402  {"jmp",    1,   0xff, 5, 0,      x_Suf|Modrm,           { WordMem, 0, 0} },  {"jmp",    1,   0xff, 5, 0,      x_Suf|Modrm,           { WordMem|JumpAbsolute, 0, 0} },
403  {"ljmp",   2,   0xea, X, CpuNo64,        wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },  {"ljmp",   2,   0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
404  {"ljmp",   1,   0xff, 5, CpuNo64,        wl_Suf|Modrm,          { WordMem|JumpAbsolute, 0, 0} },  {"ljmp",   1,   0xff, 5, 0,      wl_Suf|Modrm,          { WordMem|JumpAbsolute, 0, 0} },
405  {"ljmp",   1,   0xff, 5, Cpu64,  q_Suf|Modrm|NoRex64,   { WordMem|JumpAbsolute, 0, 0} },  
406    {"ret",    0,   0xc3, X, CpuNo64,wl_Suf|DefaultSize,    { 0, 0, 0} },
407  {"ret",    0,   0xc3, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },  {"ret",    1,   0xc2, X, CpuNo64,wl_Suf|DefaultSize,    { Imm16, 0, 0} },
408  {"ret",    1,   0xc2, X, CpuNo64,wlq_Suf|DefaultSize,   { Imm16, 0, 0} },  {"ret",    0,   0xc3, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
409  {"ret",    0,   0xc3, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },  {"ret",    1,   0xc2, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },
 {"ret",    1,   0xc2, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },  
410  {"lret",   0,   0xcb, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },  {"lret",   0,   0xcb, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },
411  {"lret",   1,   0xca, X, 0,      wlq_Suf|DefaultSize,   { Imm16, 0, 0} },  {"lret",   1,   0xca, X, 0,      wlq_Suf|DefaultSize,   { Imm16, 0, 0} },
412  {"enter",  2,   0xc8, X, Cpu186, wlq_Suf|DefaultSize,   { Imm16, Imm8, 0} },  {"enter",  2,   0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { Imm16, Imm8, 0} },
413  {"leave",  0,   0xc9, X, Cpu186, wlq_Suf|DefaultSize,   { 0, 0, 0} },  {"enter",  2,   0xc8, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,    { Imm16, Imm8, 0} },
414    {"leave",  0,   0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { 0, 0, 0} },
415    {"leave",  0,   0xc9, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,    { 0, 0, 0} },
416    
417  /* Conditional jumps.  */  /* Conditional jumps.  */
418  {"jo",     1,   0x70, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },  {"jo",     1,   0x70, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
# Line 536  static const template i386_optab[] = { Line 548  static const template i386_optab[] = {
548  /* Interrupts & op. sys insns.  */  /* Interrupts & op. sys insns.  */
549  /* See gas/config/tc-i386.c for conversion of 'int $3' into the special  /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
550     int 3 insn.  */     int 3 insn.  */
551  #define INT_OPCODE 0xcd  #define INT_OPCODE  0xcd
552  #define INT3_OPCODE 0xcc  #define INT3_OPCODE 0xcc
553  {"int",    1,   0xcd, X, 0,      NoSuf,                 { Imm8, 0, 0} },  {"int",    1,   0xcd, X, 0,      NoSuf,                 { Imm8, 0, 0} },
554  {"int3",   0,   0xcc, X, 0,      NoSuf,                 { 0, 0, 0} },  {"int3",   0,   0xcc, X, 0,      NoSuf,                 { 0, 0, 0} },
555  {"into",   0,   0xce, X, 0,      NoSuf,                 { 0, 0, 0} },  {"into",   0,   0xce, X, CpuNo64,        NoSuf,                 { 0, 0, 0} },
556  {"iret",   0,   0xcf, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },  {"iret",   0,   0xcf, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },
557  /* i386sl, i486sl, later 486, and Pentium.  */  /* i386sl, i486sl, later 486, and Pentium.  */
558  {"rsm",    0, 0x0faa, X, Cpu386, NoSuf,                 { 0, 0, 0} },  {"rsm",    0, 0x0faa, X, Cpu386, NoSuf,                 { 0, 0, 0} },
559    
560  {"bound",  2,   0x62, X, Cpu186, wlq_Suf|Modrm,         { WordReg, WordMem, 0} },  {"bound",  2,   0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm,          { WordReg, WordMem, 0} },
561    
562  {"hlt",    0,   0xf4, X, 0,      NoSuf,                 { 0, 0, 0} },  {"hlt",    0,   0xf4, X, 0,      NoSuf,                 { 0, 0, 0} },
563  /* nop is actually 'xchgl %eax, %eax'.  */  /* nop is actually 'xchgl %eax, %eax'.  */
564  {"nop",    0,   0x90, X, 0,      NoSuf,                 { 0, 0, 0} },  {"nop",    0,   0x90, X, 0,      NoSuf,                 { 0, 0, 0} },
565    
566  /* Protection control.  */  /* Protection control.  */
567  {"arpl",   2,   0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },  {"arpl",   2,   0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
568  {"lar",    2, 0x0f02, X, Cpu286, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },  {"lar",    2, 0x0f02, X, Cpu286, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },
569  {"lgdt",   1, 0x0f01, 2, Cpu286, wlq_Suf|Modrm,         { WordMem, 0, 0} },  {"lgdt",   1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm,          { WordMem, 0, 0} },
570  {"lidt",   1, 0x0f01, 3, Cpu286, wlq_Suf|Modrm,         { WordMem, 0, 0} },  {"lgdt",   1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64,            { LLongMem, 0, 0} },
571    {"lidt",   1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm,          { WordMem, 0, 0} },
572    {"lidt",   1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64,            { LLongMem, 0, 0} },
573  {"lldt",   1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },  {"lldt",   1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
574  {"lmsw",   1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },  {"lmsw",   1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
575  {"lsl",    2, 0x0f03, X, Cpu286, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },  {"lsl",    2, 0x0f03, X, Cpu286, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },
576  {"ltr",    1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },  {"ltr",    1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
577    
578  {"sgdt",   1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm,         { WordMem, 0, 0} },  {"sgdt",   1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm,          { WordMem, 0, 0} },
579  {"sidt",   1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm,         { WordMem, 0, 0} },  {"sgdt",   1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64,            { LLongMem, 0, 0} },
580    {"sidt",   1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm,          { WordMem, 0, 0} },
581    {"sidt",   1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64,            { LLongMem, 0, 0} },
582  {"sldt",   1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },  {"sldt",   1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },
583  {"sldt",   1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },  {"sldt",   1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
584  {"smsw",   1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },  {"smsw",   1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },
# Line 577  static const template i386_optab[] = { Line 593  static const template i386_optab[] = {
593    
594  /* load */  /* load */
595  {"fld",    1, 0xd9c0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },  {"fld",    1, 0xd9c0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
596  {"fld",    1,   0xd9, 0, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fld",    1,   0xd9, 0, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
597  {"fld",    1, 0xd9c0, X, 0,      l_FP|ShortForm|Ugh,    { FloatReg, 0, 0} },  {"fld",    1, 0xd9c0, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
598  /* Intel Syntax */  /* Intel Syntax */
599  {"fld",    1,   0xdb, 5, 0,      x_FP|Modrm,            { LLongMem, 0, 0} },  {"fld",    1,   0xdb, 5, 0,      x_FP|Modrm,            { LLongMem, 0, 0} },
600  {"fild",   1,   0xdf, 0, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"fild",   1,   0xdf, 0, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
601  /* Intel Syntax */  {"fild",   1,   0xdf, 5, 0,      q_FP|Modrm,            { LLongMem, 0, 0} },
 {"fildd",  1,   0xdf, 5, 0,      FP|Modrm,              { LLongMem, 0, 0} },  
 {"fildq",  1,   0xdf, 5, 0,      FP|Modrm,              { LLongMem, 0, 0} },  
602  {"fildll", 1,   0xdf, 5, 0,      FP|Modrm,              { LLongMem, 0, 0} },  {"fildll", 1,   0xdf, 5, 0,      FP|Modrm,              { LLongMem, 0, 0} },
603  {"fldt",   1,   0xdb, 5, 0,      FP|Modrm,              { LLongMem, 0, 0} },  {"fldt",   1,   0xdb, 5, 0,      FP|Modrm,              { LLongMem, 0, 0} },
604  {"fbld",   1,   0xdf, 4, 0,      FP|Modrm,              { LLongMem, 0, 0} },  {"fbld",   1,   0xdf, 4, 0,      x_Suf|Modrm,           { LLongMem, 0, 0} },
605    
606  /* store (no pop) */  /* store (no pop) */
607  {"fst",    1, 0xddd0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },  {"fst",    1, 0xddd0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
608  {"fst",    1,   0xd9, 2, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fst",    1,   0xd9, 2, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
609  {"fst",    1, 0xddd0, X, 0,      l_FP|ShortForm|Ugh,    { FloatReg, 0, 0} },  {"fst",    1, 0xddd0, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
610  {"fist",   1,   0xdf, 2, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"fist",   1,   0xdf, 2, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
611    
612  /* store (with pop) */  /* store (with pop) */
613  {"fstp",   1, 0xddd8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },  {"fstp",   1, 0xddd8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
614  {"fstp",   1,   0xd9, 3, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fstp",   1,   0xd9, 3, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
615  {"fstp",   1, 0xddd8, X, 0,      l_FP|ShortForm|Ugh,    { FloatReg, 0, 0} },  {"fstp",   1, 0xddd8, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
616  /* Intel Syntax */  /* Intel Syntax */
617  {"fstp",   1,   0xdb, 7, 0,      x_FP|Modrm,            { LLongMem, 0, 0} },  {"fstp",   1,   0xdb, 7, 0,      x_FP|Modrm,            { LLongMem, 0, 0} },
618  {"fistp",  1,   0xdf, 3, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"fistp",  1,   0xdf, 3, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
619  /* Intel Syntax */  {"fistp",  1,   0xdf, 7, 0,      q_FP|Modrm,            { LLongMem, 0, 0} },
 {"fistpd", 1,   0xdf, 7, 0,      FP|Modrm,              { LLongMem, 0, 0} },  
 {"fistpq", 1,   0xdf, 7, 0,      FP|Modrm,              { LLongMem, 0, 0} },  
620  {"fistpll",1,   0xdf, 7, 0,      FP|Modrm,              { LLongMem, 0, 0} },  {"fistpll",1,   0xdf, 7, 0,      FP|Modrm,              { LLongMem, 0, 0} },
621  {"fstpt",  1,   0xdb, 7, 0,      FP|Modrm,              { LLongMem, 0, 0} },  {"fstpt",  1,   0xdb, 7, 0,      FP|Modrm,              { LLongMem, 0, 0} },
622  {"fbstp",  1,   0xdf, 6, 0,      FP|Modrm,              { LLongMem, 0, 0} },  {"fbstp",  1,   0xdf, 6, 0,      x_Suf|Modrm,           { LLongMem, 0, 0} },
623    
624  /* exchange %st<n> with %st0 */  /* exchange %st<n> with %st0 */
625  {"fxch",   1, 0xd9c8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },  {"fxch",   1, 0xd9c8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
# Line 618  static const template i386_optab[] = { Line 630  static const template i386_optab[] = {
630  {"fcom",   1, 0xd8d0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },  {"fcom",   1, 0xd8d0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
631  /* alias for fcom %st(1) */  /* alias for fcom %st(1) */
632  {"fcom",   0, 0xd8d1, X, 0,      FP,                    { 0, 0, 0} },  {"fcom",   0, 0xd8d1, X, 0,      FP,                    { 0, 0, 0} },
633  {"fcom",   1,   0xd8, 2, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fcom",   1,   0xd8, 2, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
634  {"fcom",   1, 0xd8d0, X, 0,      l_FP|ShortForm|Ugh,    { FloatReg, 0, 0} },  {"fcom",   1, 0xd8d0, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
635  {"ficom",  1,   0xde, 2, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"ficom",  1,   0xde, 2, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
636    
637  /* comparison (with pop) */  /* comparison (with pop) */
638  {"fcomp",  1, 0xd8d8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },  {"fcomp",  1, 0xd8d8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
639  /* alias for fcomp %st(1) */  /* alias for fcomp %st(1) */
640  {"fcomp",  0, 0xd8d9, X, 0,      FP,                    { 0, 0, 0} },  {"fcomp",  0, 0xd8d9, X, 0,      FP,                    { 0, 0, 0} },
641  {"fcomp",  1,   0xd8, 3, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fcomp",  1,   0xd8, 3, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
642  {"fcomp",  1, 0xd8d8, X, 0,      l_FP|ShortForm|Ugh,    { FloatReg, 0, 0} },  {"fcomp",  1, 0xd8d8, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
643  {"ficomp", 1,   0xde, 3, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"ficomp", 1,   0xde, 3, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
644  {"fcompp", 0, 0xded9, X, 0,      FP,                    { 0, 0, 0} },  {"fcompp", 0, 0xded9, X, 0,      FP,                    { 0, 0, 0} },
645    
646  /* unordered comparison (with pop) */  /* unordered comparison (with pop) */
# Line 652  static const template i386_optab[] = { Line 664  static const template i386_optab[] = {
664  {"fldln2", 0, 0xd9ed, X, 0,      FP,                    { 0, 0, 0} },  {"fldln2", 0, 0xd9ed, X, 0,      FP,                    { 0, 0, 0} },
665  {"fldz",   0, 0xd9ee, X, 0,      FP,                    { 0, 0, 0} },  {"fldz",   0, 0xd9ee, X, 0,      FP,                    { 0, 0, 0} },
666    
667  /* arithmetic */  /* Arithmetic.  */
668    
669  /* add */  /* add */
670  {"fadd",   2, 0xd8c0, X, 0,      FP|ShortForm|FloatD,   { FloatReg, FloatAcc, 0} },  {"fadd",   2, 0xd8c0, X, 0,      FP|ShortForm|FloatD,   { FloatReg, FloatAcc, 0} },
# Line 662  static const template i386_optab[] = { Line 674  static const template i386_optab[] = {
674  /* alias for faddp */  /* alias for faddp */
675  {"fadd",   0, 0xdec1, X, 0,      FP|Ugh,                { 0, 0, 0} },  {"fadd",   0, 0xdec1, X, 0,      FP|Ugh,                { 0, 0, 0} },
676  #endif  #endif
677  {"fadd",   1,   0xd8, 0, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fadd",   1,   0xd8, 0, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
678  {"fiadd",  1,   0xde, 0, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"fiadd",  1,   0xde, 0, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
679    
680  {"faddp",  2, 0xdec0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },  {"faddp",  2, 0xdec0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
681  {"faddp",  1, 0xdec0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },  {"faddp",  1, 0xdec0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
# Line 678  static const template i386_optab[] = { Line 690  static const template i386_optab[] = {
690  /* alias for fsubp */  /* alias for fsubp */
691  {"fsub",   0, 0xdee1, X, 0,      FP|Ugh,                { 0, 0, 0} },  {"fsub",   0, 0xdee1, X, 0,      FP|Ugh,                { 0, 0, 0} },
692  #endif  #endif
693  {"fsub",   1,   0xd8, 4, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fsub",   1,   0xd8, 4, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
694  {"fisub",  1,   0xde, 4, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"fisub",  1,   0xde, 4, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
695    
696  #if SYSV386_COMPAT  #if SYSV386_COMPAT
697  {"fsubp",  2, 0xdee0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },  {"fsubp",  2, 0xdee0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
# Line 701  static const template i386_optab[] = { Line 713  static const template i386_optab[] = {
713  /* alias for fsubrp */  /* alias for fsubrp */
714  {"fsubr",  0, 0xdee9, X, 0,      FP|Ugh,                { 0, 0, 0} },  {"fsubr",  0, 0xdee9, X, 0,      FP|Ugh,                { 0, 0, 0} },
715  #endif  #endif
716  {"fsubr",  1,   0xd8, 5, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fsubr",  1,   0xd8, 5, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
717  {"fisubr", 1,   0xde, 5, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"fisubr", 1,   0xde, 5, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
718    
719  #if SYSV386_COMPAT  #if SYSV386_COMPAT
720  {"fsubrp", 2, 0xdee8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },  {"fsubrp", 2, 0xdee8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
# Line 724  static const template i386_optab[] = { Line 736  static const template i386_optab[] = {
736  /* alias for fmulp */  /* alias for fmulp */
737  {"fmul",   0, 0xdec9, X, 0,      FP|Ugh,                { 0, 0, 0} },  {"fmul",   0, 0xdec9, X, 0,      FP|Ugh,                { 0, 0, 0} },
738  #endif  #endif
739  {"fmul",   1,   0xd8, 1, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fmul",   1,   0xd8, 1, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
740  {"fimul",  1,   0xde, 1, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"fimul",  1,   0xde, 1, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
741    
742  {"fmulp",  2, 0xdec8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },  {"fmulp",  2, 0xdec8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
743  {"fmulp",  1, 0xdec8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },  {"fmulp",  1, 0xdec8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
# Line 739  static const template i386_optab[] = { Line 751  static const template i386_optab[] = {
751  /* alias for fdivp */  /* alias for fdivp */
752  {"fdiv",   0, 0xdef1, X, 0,      FP|Ugh,                { 0, 0, 0} },  {"fdiv",   0, 0xdef1, X, 0,      FP|Ugh,                { 0, 0, 0} },
753  #endif  #endif
754  {"fdiv",   1,   0xd8, 6, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fdiv",   1,   0xd8, 6, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
755  {"fidiv",  1,   0xde, 6, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"fidiv",  1,   0xde, 6, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
756    
757  #if SYSV386_COMPAT  #if SYSV386_COMPAT
758  {"fdivp",  2, 0xdef0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },  {"fdivp",  2, 0xdef0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
# Line 762  static const template i386_optab[] = { Line 774  static const template i386_optab[] = {
774  /* alias for fdivrp */  /* alias for fdivrp */
775  {"fdivr",  0, 0xdef9, X, 0,      FP|Ugh,                { 0, 0, 0} },  {"fdivr",  0, 0xdef9, X, 0,      FP|Ugh,                { 0, 0, 0} },
776  #endif  #endif
777  {"fdivr",  1,   0xd8, 7, 0,      sl_FP|FloatMF|Modrm,   { LongMem|LLongMem, 0, 0} },  {"fdivr",  1,   0xd8, 7, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
778  {"fidivr", 1,   0xde, 7, 0,      sl_FP|FloatMF|Modrm,   { ShortMem|LongMem, 0, 0} },  {"fidivr", 1,   0xde, 7, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
779    
780  #if SYSV386_COMPAT  #if SYSV386_COMPAT
781  {"fdivrp", 2, 0xdef8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },  {"fdivrp", 2, 0xdef8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
# Line 800  static const template i386_optab[] = { Line 812  static const template i386_optab[] = {
812  /* processor control */  /* processor control */
813  {"fninit", 0, 0xdbe3, X, 0,      FP,                    { 0, 0, 0} },  {"fninit", 0, 0xdbe3, X, 0,      FP,                    { 0, 0, 0} },
814  {"finit",  0, 0xdbe3, X, 0,      FP|FWait,              { 0, 0, 0} },  {"finit",  0, 0xdbe3, X, 0,      FP|FWait,              { 0, 0, 0} },
815  {"fldcw",  1,   0xd9, 5, 0,      FP|Modrm,              { ShortMem, 0, 0} },  {"fldcw",  1,   0xd9, 5, 0,      w_Suf|FloatMF|Modrm,   { ShortMem, 0, 0} },
816  {"fnstcw", 1,   0xd9, 7, 0,      FP|Modrm,              { ShortMem, 0, 0} },  {"fnstcw", 1,   0xd9, 7, 0,      w_Suf|FloatMF|Modrm,   { ShortMem, 0, 0} },
817  {"fstcw",  1,   0xd9, 7, 0,      FP|FWait|Modrm,        { ShortMem, 0, 0} },  {"fstcw",  1,   0xd9, 7, 0,      w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
818  {"fnstsw", 1, 0xdfe0, X, 0,      FP,                    { Acc, 0, 0} },  /* XXX should reject %al, %eax, and %rax */
819  {"fnstsw", 1,   0xdd, 7, 0,      FP|Modrm,              { ShortMem, 0, 0} },  {"fnstsw", 1, 0xdfe0, X, 0,      FP|IgnoreSize,         { Acc, 0, 0} },
820    {"fnstsw", 1,   0xdd, 7, 0,      w_Suf|FloatMF|Modrm,   { ShortMem, 0, 0} },
821  {"fnstsw", 0, 0xdfe0, X, 0,      FP,                    { 0, 0, 0} },  {"fnstsw", 0, 0xdfe0, X, 0,      FP,                    { 0, 0, 0} },
822  {"fstsw",  1, 0xdfe0, X, 0,      FP|FWait,              { Acc, 0, 0} },  /* XXX should reject %al, %eax, and %rax */
823  {"fstsw",  1,   0xdd, 7, 0,      FP|FWait|Modrm,        { ShortMem, 0, 0} },  {"fstsw",  1, 0xdfe0, X, 0,      FP|FWait|IgnoreSize,   { Acc, 0, 0} },
824    {"fstsw",  1,   0xdd, 7, 0,      w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
825  {"fstsw",  0, 0xdfe0, X, 0,      FP|FWait,              { 0, 0, 0} },  {"fstsw",  0, 0xdfe0, X, 0,      FP|FWait,              { 0, 0, 0} },
826  {"fnclex", 0, 0xdbe2, X, 0,      FP,                    { 0, 0, 0} },  {"fnclex", 0, 0xdbe2, X, 0,      FP,                    { 0, 0, 0} },
827  {"fclex",  0, 0xdbe2, X, 0,      FP|FWait,              { 0, 0, 0} },  {"fclex",  0, 0xdbe2, X, 0,      FP|FWait,              { 0, 0, 0} },
828  /* Short forms of fldenv, fstenv use data size prefix.  */  /* Short forms of fldenv, fstenv use data size prefix.  */
829  {"fnstenv",1,   0xd9, 6, 0,      sl_Suf|Modrm,          { LLongMem, 0, 0} },  {"fnstenv",1,   0xd9, 6, 0,      sl_Suf|Modrm|DefaultSize,              { LLongMem, 0, 0} },
830  {"fstenv", 1,   0xd9, 6, 0,      sl_Suf|FWait|Modrm,    { LLongMem, 0, 0} },  {"fstenv", 1,   0xd9, 6, 0,      sl_Suf|FWait|Modrm|DefaultSize,        { LLongMem, 0, 0} },
831  {"fldenv", 1,   0xd9, 4, 0,      sl_Suf|Modrm,          { LLongMem, 0, 0} },  {"fldenv", 1,   0xd9, 4, 0,      sl_Suf|Modrm|DefaultSize,              { LLongMem, 0, 0} },
832  {"fnsave", 1,   0xdd, 6, 0,      sl_Suf|Modrm,          { LLongMem, 0, 0} },  {"fnsave", 1,   0xdd, 6, 0,      sl_Suf|Modrm|DefaultSize,              { LLongMem, 0, 0} },
833  {"fsave",  1,   0xdd, 6, 0,      sl_Suf|FWait|Modrm,    { LLongMem, 0, 0} },  {"fsave",  1,   0xdd, 6, 0,      sl_Suf|FWait|Modrm|DefaultSize,        { LLongMem, 0, 0} },
834  {"frstor", 1,   0xdd, 4, 0,      sl_Suf|Modrm,          { LLongMem, 0, 0} },  {"frstor", 1,   0xdd, 4, 0,      sl_Suf|Modrm|DefaultSize,              { LLongMem, 0, 0} },
835    
836  {"ffree",  1, 0xddc0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },  {"ffree",  1, 0xddc0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
837  /* P6:free st(i), pop st */  /* P6:free st(i), pop st */
# Line 829  static const template i386_optab[] = { Line 843  static const template i386_optab[] = {
843  /* Opcode prefixes; we allow them as separate insns too.  */  /* Opcode prefixes; we allow them as separate insns too.  */
844    
845  #define ADDR_PREFIX_OPCODE 0x67  #define ADDR_PREFIX_OPCODE 0x67
846  {"addr16", 0,   0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize,      { 0, 0, 0} },  {"addr16", 0,   0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize,      { 0, 0, 0} },
847  {"addr32", 0,   0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize,      { 0, 0, 0} },  {"addr32", 0,   0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
848  {"aword",  0,   0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize,      { 0, 0, 0} },  {"aword",  0,   0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize,       { 0, 0, 0} },
849  {"adword", 0,   0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize,      { 0, 0, 0} },  {"adword", 0,   0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
850  #define DATA_PREFIX_OPCODE 0x66  #define DATA_PREFIX_OPCODE 0x66
851  {"data16", 0,   0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize,      { 0, 0, 0} },  {"data16", 0,   0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize,       { 0, 0, 0} },
852  {"data32", 0,   0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize,      { 0, 0, 0} },  {"data32", 0,   0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
853  {"word",   0,   0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize,      { 0, 0, 0} },  {"word",   0,   0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize,       { 0, 0, 0} },
854  {"dword",  0,   0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize,      { 0, 0, 0} },  {"dword",  0,   0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
855  #define LOCK_PREFIX_OPCODE 0xf0  #define LOCK_PREFIX_OPCODE 0xf0
856  {"lock",   0,   0xf0, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },  {"lock",   0,   0xf0, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
857  {"wait",   0,   0x9b, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },  {"wait",   0,   0x9b, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
858  #define CS_PREFIX_OPCODE 0x2e  #define CS_PREFIX_OPCODE 0x2e
859  {"cs",     0,   0x2e, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },  {"cs",     0,   0x2e, X, 0,     NoSuf|IsPrefix, { 0, 0, 0} },
860  #define DS_PREFIX_OPCODE 0x3e  #define DS_PREFIX_OPCODE 0x3e
861  {"ds",     0,   0x3e, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },  {"ds",     0,   0x3e, X, 0,     NoSuf|IsPrefix, { 0, 0, 0} },
862  #define ES_PREFIX_OPCODE 0x26  #define ES_PREFIX_OPCODE 0x26
863  {"es",     0,   0x26, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },  {"es",     0,   0x26, X, CpuNo64,       NoSuf|IsPrefix, { 0, 0, 0} },
864  #define FS_PREFIX_OPCODE 0x64  #define FS_PREFIX_OPCODE 0x64
865  {"fs",     0,   0x64, X, Cpu386, NoSuf|IsPrefix,        { 0, 0, 0} },  {"fs",     0,   0x64, X, Cpu386, NoSuf|IsPrefix,        { 0, 0, 0} },
866  #define GS_PREFIX_OPCODE 0x65  #define GS_PREFIX_OPCODE 0x65
867  {"gs",     0,   0x65, X, Cpu386, NoSuf|IsPrefix,        { 0, 0, 0} },  {"gs",     0,   0x65, X, Cpu386, NoSuf|IsPrefix,        { 0, 0, 0} },
868  #define SS_PREFIX_OPCODE 0x36  #define SS_PREFIX_OPCODE 0x36
869  {"ss",     0,   0x36, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },  {"ss",     0,   0x36, X, CpuNo64,       NoSuf|IsPrefix, { 0, 0, 0} },
870  #define REPNE_PREFIX_OPCODE 0xf2  #define REPNE_PREFIX_OPCODE 0xf2
871  #define REPE_PREFIX_OPCODE  0xf3  #define REPE_PREFIX_OPCODE  0xf3
872  {"rep",    0,   0xf3, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },  {"rep",    0,   0xf3, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
# Line 884  static const template i386_optab[] = { Line 898  static const template i386_optab[] = {
898  {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm,     { Reg, Reg|AnyMem, 0 } },  {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm,     { Reg, Reg|AnyMem, 0 } },
899  {"invd",    0, 0x0f08, X, Cpu486, NoSuf,                { 0, 0, 0} },  {"invd",    0, 0x0f08, X, Cpu486, NoSuf,                { 0, 0, 0} },
900  {"wbinvd",  0, 0x0f09, X, Cpu486, NoSuf,                { 0, 0, 0} },  {"wbinvd",  0, 0x0f09, X, Cpu486, NoSuf,                { 0, 0, 0} },
901  {"invlpg",  1, 0x0f01, 7, Cpu486, NoSuf|Modrm,          { AnyMem, 0, 0} },  {"invlpg",  1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} },
902    
903  /* 586 and late 486 extensions.  */  /* 586 and late 486 extensions.  */
904  {"cpuid",   0, 0x0fa2, X, Cpu486, NoSuf,                { 0, 0, 0} },  {"cpuid",   0, 0x0fa2, X, Cpu486, NoSuf,                { 0, 0, 0} },
# Line 893  static const template i386_optab[] = { Line 907  static const template i386_optab[] = {
907  {"wrmsr",   0, 0x0f30, X, Cpu586, NoSuf,                { 0, 0, 0} },  {"wrmsr",   0, 0x0f30, X, Cpu586, NoSuf,                { 0, 0, 0} },
908  {"rdtsc",   0, 0x0f31, X, Cpu586, NoSuf,                { 0, 0, 0} },  {"rdtsc",   0, 0x0f31, X, Cpu586, NoSuf,                { 0, 0, 0} },
909  {"rdmsr",   0, 0x0f32, X, Cpu586, NoSuf,                { 0, 0, 0} },  {"rdmsr",   0, 0x0f32, X, Cpu586, NoSuf,                { 0, 0, 0} },
910  {"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm,          { LLongMem, 0, 0} },  {"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm,          { LLongMem, 0, 0} },
911    
912  /* Pentium II/Pentium Pro extensions.  */  /* Pentium II/Pentium Pro extensions.  */
913  {"sysenter",0, 0x0f34, X, Cpu686|CpuNo64, NoSuf,        { 0, 0, 0} },  {"sysenter",0, 0x0f34, X, Cpu686, NoSuf,                { 0, 0, 0} },
914  {"sysexit", 0, 0x0f35, X, Cpu686|CpuNo64, NoSuf,        { 0, 0, 0} },  {"sysexit", 0, 0x0f35, X, Cpu686, NoSuf,                { 0, 0, 0} },
915  {"fxsave",  1, 0x0fae, 0, Cpu686, FP|Modrm,             { LLongMem, 0, 0} },  {"fxsave",  1, 0x0fae, 0, Cpu686, q_Suf|Modrm,          { LLongMem, 0, 0} },
916  {"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm,             { LLongMem, 0, 0} },  {"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm,          { LLongMem, 0, 0} },
917  {"rdpmc",   0, 0x0f33, X, Cpu686, NoSuf,                { 0, 0, 0} },  {"rdpmc",   0, 0x0f33, X, Cpu686, NoSuf,                { 0, 0, 0} },
918  /* official undefined instr. */  /* official undefined instr. */
919  {"ud2",     0, 0x0f0b, X, Cpu686, NoSuf,                { 0, 0, 0} },  {"ud2",     0, 0x0f0b, X, Cpu686, NoSuf,                { 0, 0, 0} },
# Line 967  static const template i386_optab[] = { Line 981  static const template i386_optab[] = {
981    
982  /* Pentium4 extensions.  */  /* Pentium4 extensions.  */
983    
984  {"movnti",   2, 0x0fc3,    X, CpuP4, FP|Modrm,          { WordReg, WordMem, 0 } },  {"movnti",   2, 0x0fc3,    X, CpuP4, wlq_Suf|Modrm,             { WordReg, WordMem, 0 } },
985  {"clflush",  1, 0x0fae,    7, CpuP4, FP|Modrm,          { ByteMem, 0, 0 } },  {"clflush",  1, 0x0fae,    7, CpuP4, NoSuf|Modrm|IgnoreSize,    { ByteMem, 0, 0 } },
986  {"lfence",   0, 0x0fae, 0xe8, CpuP4, FP|ImmExt,         { 0, 0, 0 } },  {"lfence",   0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt,              { 0, 0, 0 } },
987  {"mfence",   0, 0x0fae, 0xf0, CpuP4, FP|ImmExt,         { 0, 0, 0 } },  {"mfence",   0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt,              { 0, 0, 0 } },
988  {"pause",    0, 0xf390,    X, CpuP4, FP,                { 0, 0, 0 } },  {"pause",    0, 0xf390,    X, CpuP4, NoSuf,             { 0, 0, 0 } },
989    
990  /* MMX/SSE2 instructions.  */  /* MMX/SSE2 instructions.  */
991    
992  {"emms",     0, 0x0f77, X, CpuMMX, FP,                  { 0, 0, 0 } },  {"emms",     0, 0x0f77, X, CpuMMX, NoSuf,                       { 0, 0, 0 } },
993  {"movd",     2, 0x0f6e, X, CpuMMX, FP|Modrm,            { Reg32|LongMem, RegMMX, 0 } },  {"movd",     2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } },
994  {"movd",     2, 0x0f7e, X, CpuMMX, FP|Modrm,            { RegMMX, Reg32|LongMem, 0 } },  {"movd",     2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } },
995  {"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,            { Reg32|LLongMem, RegXMM, 0 } },  {"movd",     2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LLongMem, RegXMM, 0 } },
996  {"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,            { RegXMM, Reg32|LLongMem, 0 } },  {"movd",     2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LLongMem, 0 } },
 /* Real MMX instructions.  */  
 {"movd",     2, 0x0f6e, X, CpuMMX, FP|Modrm,            { Reg64|LLongMem, RegMMX, 0 } },  
 {"movd",     2, 0x0f7e, X, CpuMMX, FP|Modrm,            { RegMMX, Reg64|LLongMem, 0 } },  
 {"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,            { Reg64|LLongMem, RegXMM, 0 } },  
 {"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,            { RegXMM, Reg64|LLongMem, 0 } },  
997  /* In the 64bit mode the short form mov immediate is redefined to have  /* In the 64bit mode the short form mov immediate is redefined to have
998     64bit displacement value.  */     64bit displacement value.  */
999  {"movq",     2, 0x0f6f, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"movq",     2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1000  {"movq",     2, 0x0f7f, X, CpuMMX, FP|Modrm,            { RegMMX, RegMMX|LongMem, 0 } },  {"movq",     2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
1001  {"movq",     2, 0xf30f7e,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"movq",     2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1002  {"movq",     2, 0x660fd6,X,CpuSSE2,FP|Modrm,            { RegXMM, RegXMM|LLongMem, 0 } },  {"movq",     2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1003  {"movq",   2,   0x88, X, Cpu64,  NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },  {"movq",   2,   0x88, X, Cpu64,  NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
1004  {"movq",   2,   0xc6, 0, Cpu64,  NoSuf|W|Modrm|Size64,  { Imm32S, Reg64|WordMem, 0 } },  {"movq",   2,   0xc6, 0, Cpu64,  NoSuf|W|Modrm|Size64,  { Imm32S, Reg64|WordMem, 0 } },
1005  {"movq",   2,   0xb0, X, Cpu64,  NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },  {"movq",   2,   0xb0, X, Cpu64,  NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
# Line 998  static const template i386_optab[] = { Line 1007  static const template i386_optab[] = {
1007     mode they are 64bit.*/     mode they are 64bit.*/
1008  {"movq",   2, 0x0f20, X, Cpu64,  NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} },  {"movq",   2, 0x0f20, X, Cpu64,  NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} },
1009  {"movq",   2, 0x0f21, X, Cpu64,  NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} },  {"movq",   2, 0x0f21, X, Cpu64,  NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} },
1010  {"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  /* Real MMX instructions.  */
1011  {"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1012  {"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1013  {"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1014  {"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1015  {"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1016  {"paddb",    2, 0x0ffc, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1017  {"paddb",    2, 0x660ffc,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"paddb",    2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1018  {"paddw",    2, 0x0ffd, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"paddb",    2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1019  {"paddw",    2, 0x660ffd,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"paddw",    2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1020  {"paddd",    2, 0x0ffe, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"paddw",    2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1021  {"paddd",    2, 0x660ffe,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"paddd",    2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1022  {"paddq",    2, 0x0fd4, X, CpuMMX, FP|Modrm,            { RegMMX|LLongMem, RegMMX, 0 } },  {"paddd",    2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1023  {"paddq",    2, 0x660fd4,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"paddq",    2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegMMX|LLongMem, RegMMX, 0 } },
1024  {"paddsb",   2, 0x0fec, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"paddq",    2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1025  {"paddsb",   2, 0x660fec,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"paddsb",   2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1026  {"paddsw",   2, 0x0fed, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"paddsb",   2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1027  {"paddsw",   2, 0x660fed,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"paddsw",   2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1028  {"paddusb",  2, 0x0fdc, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"paddsw",   2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1029  {"paddusb",  2, 0x660fdc,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"paddusb",  2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1030  {"paddusw",  2, 0x0fdd, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"paddusb",  2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1031  {"paddusw",  2, 0x660fdd,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"paddusw",  2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1032  {"pand",     2, 0x0fdb, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"paddusw",  2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1033  {"pand",     2, 0x660fdb,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pand",     2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1034  {"pandn",    2, 0x0fdf, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pand",     2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1035  {"pandn",    2, 0x660fdf,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pandn",    2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1036  {"pcmpeqb",  2, 0x0f74, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pandn",    2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1037  {"pcmpeqb",  2, 0x660f74,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pcmpeqb",  2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1038  {"pcmpeqw",  2, 0x0f75, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pcmpeqb",  2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1039  {"pcmpeqw",  2, 0x660f75,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pcmpeqw",  2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1040  {"pcmpeqd",  2, 0x0f76, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pcmpeqw",  2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1041  {"pcmpeqd",  2, 0x660f76,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pcmpeqd",  2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1042  {"pcmpgtb",  2, 0x0f64, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pcmpeqd",  2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1043  {"pcmpgtb",  2, 0x660f64,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pcmpgtb",  2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1044  {"pcmpgtw",  2, 0x0f65, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pcmpgtb",  2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1045  {"pcmpgtw",  2, 0x660f65,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pcmpgtw",  2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1046  {"pcmpgtd",  2, 0x0f66, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pcmpgtw",  2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1047  {"pcmpgtd",  2, 0x660f66,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pcmpgtd",  2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1048  {"pmaddwd",  2, 0x0ff5, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pcmpgtd",  2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1049  {"pmaddwd",  2, 0x660ff5,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pmaddwd",  2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1050  {"pmulhw",   2, 0x0fe5, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pmaddwd",  2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1051  {"pmulhw",   2, 0x660fe5,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pmulhw",   2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1052  {"pmullw",   2, 0x0fd5, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pmulhw",   2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1053  {"pmullw",   2, 0x660fd5,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pmullw",   2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1054  {"por",      2, 0x0feb, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pmullw",   2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1055  {"por",      2, 0x660feb,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"por",      2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1056  {"psllw",    2, 0x0ff1, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"por",      2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1057  {"psllw",    2, 0x660ff1,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psllw",    2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1058  {"psllw",    2, 0x0f71, 6, CpuMMX, FP|Modrm,            { Imm8, RegMMX, 0 } },  {"psllw",    2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1059  {"psllw",    2, 0x660f71,6,CpuSSE2,FP|Modrm,            { Imm8, RegXMM, 0 } },  {"psllw",    2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1060  {"pslld",    2, 0x0ff2, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psllw",    2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1061  {"pslld",    2, 0x660ff2,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pslld",    2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1062  {"pslld",    2, 0x0f72, 6, CpuMMX, FP|Modrm,            { Imm8, RegMMX, 0 } },  {"pslld",    2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1063  {"pslld",    2, 0x660f72,6,CpuSSE2,FP|Modrm,            { Imm8, RegXMM, 0 } },  {"pslld",    2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1064  {"psllq",    2, 0x0ff3, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"pslld",    2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1065  {"psllq",    2, 0x660ff3,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psllq",    2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1066  {"psllq",    2, 0x0f73, 6, CpuMMX, FP|Modrm,            { Imm8, RegMMX, 0 } },  {"psllq",    2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1067  {"psllq",    2, 0x660f73,6,CpuSSE2,FP|Modrm,            { Imm8, RegXMM, 0 } },  {"psllq",    2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1068  {"psraw",    2, 0x0fe1, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psllq",    2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1069  {"psraw",    2, 0x660fe1,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psraw",    2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1070  {"psraw",    2, 0x0f71, 4, CpuMMX, FP|Modrm,            { Imm8, RegMMX, 0 } },  {"psraw",    2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1071  {"psraw",    2, 0x660f71,4,CpuSSE2,FP|Modrm,            { Imm8, RegXMM, 0 } },  {"psraw",    2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1072  {"psrad",    2, 0x0fe2, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psraw",    2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1073  {"psrad",    2, 0x660fe2,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psrad",    2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1074  {"psrad",    2, 0x0f72, 4, CpuMMX, FP|Modrm,            { Imm8, RegMMX, 0 } },  {"psrad",    2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1075  {"psrad",    2, 0x660f72,4,CpuSSE2,FP|Modrm,            { Imm8, RegXMM, 0 } },  {"psrad",    2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1076  {"psrlw",    2, 0x0fd1, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psrad",    2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1077  {"psrlw",    2, 0x660fd1,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psrlw",    2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1078  {"psrlw",    2, 0x0f71, 2, CpuMMX, FP|Modrm,            { Imm8, RegMMX, 0 } },  {"psrlw",    2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1079  {"psrlw",    2, 0x660f71,2,CpuSSE2,FP|Modrm,            { Imm8, RegXMM, 0 } },  {"psrlw",    2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1080  {"psrld",    2, 0x0fd2, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psrlw",    2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1081  {"psrld",    2, 0x660fd2,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psrld",    2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1082  {"psrld",    2, 0x0f72, 2, CpuMMX, FP|Modrm,            { Imm8, RegMMX, 0 } },  {"psrld",    2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1083  {"psrld",    2, 0x660f72,2,CpuSSE2,FP|Modrm,            { Imm8, RegXMM, 0 } },  {"psrld",    2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1084  {"psrlq",    2, 0x0fd3, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psrld",    2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1085  {"psrlq",    2, 0x660fd3,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psrlq",    2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1086  {"psrlq",    2, 0x0f73, 2, CpuMMX, FP|Modrm,            { Imm8, RegMMX, 0 } },  {"psrlq",    2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1087  {"psrlq",    2, 0x660f73,2,CpuSSE2,FP|Modrm,            { Imm8, RegXMM, 0 } },  {"psrlq",    2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1088  {"psubb",    2, 0x0ff8, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psrlq",    2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1089  {"psubb",    2, 0x660ff8,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psubb",    2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1090  {"psubw",    2, 0x0ff9, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psubb",    2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1091  {"psubw",    2, 0x660ff9,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psubw",    2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1092  {"psubd",    2, 0x0ffa, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psubw",    2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1093  {"psubd",    2, 0x660ffa,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psubd",    2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1094  {"psubq",    2, 0x0ffb, X, CpuMMX, FP|Modrm,            { RegMMX|LLongMem, RegMMX, 0 } },  {"psubd",    2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1095  {"psubq",    2, 0x660ffb,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psubq",    2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegMMX|LLongMem, RegMMX, 0 } },
1096  {"psubsb",   2, 0x0fe8, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psubq",    2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1097  {"psubsb",   2, 0x660fe8,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psubsb",   2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1098  {"psubsw",   2, 0x0fe9, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psubsb",   2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1099  {"psubsw",   2, 0x660fe9,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psubsw",   2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1100  {"psubusb",  2, 0x0fd8, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psubsw",   2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1101  {"psubusb",  2, 0x660fd8,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psubusb",  2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1102  {"psubusw",  2, 0x0fd9, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psubusb",  2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1103  {"psubusw",  2, 0x660fd9,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"psubusw",  2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1104  {"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"psubusw",  2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1105  {"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1106  {"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1107  {"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1108  {"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1109  {"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1110  {"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1111  {"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1112  {"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1113  {"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1114  {"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1115  {"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1116  {"pxor",     2, 0x0fef, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },  {"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1117  {"pxor",     2, 0x660fef,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },  {"pxor",     2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1118    {"pxor",     2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1119    
1120  /* PIII Katmai New Instructions / SIMD instructions.  */  /* PIII Katmai New Instructions / SIMD instructions.  */
1121    
1122  {"addps",     2, 0x0f58,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"addps",     2, 0x0f58,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1123  {"addss",     2, 0xf30f58,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"addss",     2, 0xf30f58,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1124  {"andnps",    2, 0x0f55,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"andnps",    2, 0x0f55,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1125  {"andps",     2, 0x0f54,    X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"andps",     2, 0x0f54,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1126  {"cmpeqps",   2, 0x0fc2,    0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },  {"cmpeqps",   2, 0x0fc2,    0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1127  {"cmpeqss",   2, 0xf30fc2,  0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },  {"cmpeqss",   2, 0xf30fc2,  0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1128  {"cmpleps",   2, 0x0fc2,    2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },  {"cmpleps",   2, 0x0fc2,    2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1129  {"cmpless",   2, 0xf30fc2,  2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },  {"cmpless",   2, 0xf30fc2,  2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1130  {"cmpltps",   2, 0x0fc2,    1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },  {"cmpltps",   2, 0x0fc2,    1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1131  {"cmpltss",   2, 0xf30fc2,  1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },  {"cmpltss",   2, 0xf30fc2,  1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1132  {"cmpneqps",  2, 0x0fc2,    4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },  {"cmpneqps",  2, 0x0fc2,    4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1133  {"cmpneqss",  2, 0xf30fc2,  4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },  {"cmpneqss",  2, 0xf30fc2,  4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1134  {"cmpnleps",  2, 0x0fc2,    6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },  {"cmpnleps",  2, 0x0fc2,    6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1135  {"cmpnless",  2, 0xf30fc2,  6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },  {"cmpnless",  2, 0xf30fc2,  6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1136  {"cmpnltps",  2, 0x0fc2,    5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },  {"cmpnltps",  2, 0x0fc2,    5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1137  {"cmpnltss",  2, 0xf30fc2,  5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },  {"cmpnltss",  2, 0xf30fc2,  5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1138  {"cmpordps",  2, 0x0fc2,    7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },  {"cmpordps",  2, 0x0fc2,    7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1139  {"cmpordss",  2, 0xf30fc2,  7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },  {"cmpordss",  2, 0xf30fc2,  7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1140  {"cmpunordps",2, 0x0fc2,    3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },  {"cmpunordps",2, 0x0fc2,    3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1141  {"cmpunordss",2, 0xf30fc2,  3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },  {"cmpunordss",2, 0xf30fc2,  3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1142  {"cmpps",     3, 0x0fc2,    X, CpuSSE, FP|Modrm,        { Imm8, RegXMM|LLongMem, RegXMM } },  {"cmpps",     3, 0x0fc2,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { Imm8, RegXMM|LLongMem, RegXMM } },
1143  {"cmpss",     3, 0xf30fc2,  X, CpuSSE, FP|Modrm,        { Imm8, RegXMM|WordMem, RegXMM } },  {"cmpss",     3, 0xf30fc2,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { Imm8, RegXMM|WordMem, RegXMM } },
1144  {"comiss",    2, 0x0f2f,    X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"comiss",    2, 0x0f2f,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1145  {"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegXMM, 0 } },  {"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegXMM, 0 } },
1146  {"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegMMX, 0 } },  {"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegMMX, 0 } },
1147  {"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },  {"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
1148  {"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },  {"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
1149  {"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegMMX, 0 } },  {"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegMMX, 0 } },
1150  {"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } },  {"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } },
1151  {"divps",     2, 0x0f5e,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"divps",     2, 0x0f5e,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1152  {"divss",     2, 0xf30f5e,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"divss",     2, 0xf30f5e,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1153  {"ldmxcsr",   1, 0x0fae,    2, CpuSSE, FP|Modrm,        { WordMem, 0, 0 } },  {"ldmxcsr",   1, 0x0fae,    2, CpuSSE, NoSuf|IgnoreSize|Modrm,  { WordMem, 0, 0 } },
1154  {"maskmovq",  2, 0x0ff7,    X, CpuSSE, FP|Modrm,        { RegMMX|InvMem, RegMMX, 0 } },  {"maskmovq",  2, 0x0ff7,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|InvMem, RegMMX, 0 } },
1155  {"maxps",     2, 0x0f5f,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"maxps",     2, 0x0f5f,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1156  {"maxss",     2, 0xf30f5f,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"maxss",     2, 0xf30f5f,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1157  {"minps",     2, 0x0f5d,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"minps",     2, 0x0f5d,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1158  {"minss",     2, 0xf30f5d,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"minss",     2, 0xf30f5d,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1159  {"movaps",    2, 0x0f28,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"movaps",    2, 0x0f28,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1160  {"movaps",    2, 0x0f29,    X, CpuSSE, FP|Modrm,        { RegXMM, RegXMM|LLongMem, 0 } },  {"movaps",    2, 0x0f29,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, RegXMM|LLongMem, 0 } },
1161  {"movhlps",   2, 0x0f12,    X, CpuSSE, FP|Modrm,        { RegXMM|InvMem, RegXMM, 0 } },  {"movhlps",   2, 0x0f12,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|InvMem, RegXMM, 0 } },
1162  {"movhps",    2, 0x0f16,    X, CpuSSE, FP|Modrm,        { LLongMem, RegXMM, 0 } },  {"movhps",    2, 0x0f16,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { LLongMem, RegXMM, 0 } },
1163  {"movhps",    2, 0x0f17,    X, CpuSSE, FP|Modrm,        { RegXMM, LLongMem, 0 } },  {"movhps",    2, 0x0f17,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, LLongMem, 0 } },
1164  {"movlhps",   2, 0x0f16,    X, CpuSSE, FP|Modrm,        { RegXMM|InvMem, RegXMM, 0 } },  {"movlhps",   2, 0x0f16,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|InvMem, RegXMM, 0 } },
1165  {"movlps",    2, 0x0f12,    X, CpuSSE, FP|Modrm,        { LLongMem, RegXMM, 0 } },  {"movlps",    2, 0x0f12,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { LLongMem, RegXMM, 0 } },
1166  {"movlps",    2, 0x0f13,    X, CpuSSE, FP|Modrm,        { RegXMM, LLongMem, 0 } },  {"movlps",    2, 0x0f13,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, LLongMem, 0 } },
1167  {"movmskps",  2, 0x0f50,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },  {"movmskps",  2, 0x0f50,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
1168  {"movntps",   2, 0x0f2b,    X, CpuSSE, FP|Modrm,        { RegXMM, LLongMem, 0 } },  {"movntps",   2, 0x0f2b,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, LLongMem, 0 } },
1169  {"movntq",    2, 0x0fe7,    X, CpuSSE, FP|Modrm,        { RegMMX, LLongMem, 0 } },  {"movntq",    2, 0x0fe7,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX, LLongMem, 0 } },
1170  {"movntdq",   2, 0x660fe7,  X, CpuSSE2,FP|Modrm,        { RegXMM, LLongMem, 0 } },  {"movntdq",   2, 0x660fe7,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM, LLongMem, 0 } },
1171  {"movss",     2, 0xf30f10,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"movss",     2, 0xf30f10,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1172  {"movss",     2, 0xf30f11,  X, CpuSSE, FP|Modrm,        { RegXMM, RegXMM|WordMem, 0 } },  {"movss",     2, 0xf30f11,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, RegXMM|WordMem, 0 } },
1173  {"movups",    2, 0x0f10,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"movups",    2, 0x0f10,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1174  {"movups",    2, 0x0f11,    X, CpuSSE, FP|Modrm,        { RegXMM, RegXMM|LLongMem, 0 } },  {"movups",    2, 0x0f11,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, RegXMM|LLongMem, 0 } },
1175  {"mulps",     2, 0x0f59,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"mulps",     2, 0x0f59,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1176  {"mulss",     2, 0xf30f59,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"mulss",     2, 0xf30f59,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1177  {"orps",      2, 0x0f56,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"orps",      2, 0x0f56,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1178  {"pavgb",     2, 0x0fe0,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },  {"pavgb",     2, 0x0fe0,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1179  {"pavgb",     2, 0x660fe0,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"pavgb",     2, 0x660fe0,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1180  {"pavgw",     2, 0x0fe3,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },  {"pavgw",     2, 0x0fe3,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1181  {"pavgw",     2, 0x660fe3,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"pavgw",     2, 0x660fe3,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1182  {"pextrw",    3, 0x0fc5,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },  {"pextrw",    3, 0x0fc5,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
1183  {"pextrw",    3, 0x660fc5,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } },  {"pextrw",    3, 0x660fc5,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } },
1184  {"pinsrw",    3, 0x0fc4,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },  {"pinsrw",    3, 0x0fc4,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
1185  {"pinsrw",    3, 0x660fc4,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },  {"pinsrw",    3, 0x660fc4,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
1186  {"pmaxsw",    2, 0x0fee,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },  {"pmaxsw",    2, 0x0fee,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1187  {"pmaxsw",    2, 0x660fee,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"pmaxsw",    2, 0x660fee,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1188  {"pmaxub",    2, 0x0fde,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },  {"pmaxub",    2, 0x0fde,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1189  {"pmaxub",    2, 0x660fde,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"pmaxub",    2, 0x660fde,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1190  {"pminsw",    2, 0x0fea,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },  {"pminsw",    2, 0x0fea,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1191  {"pminsw",    2, 0x660fea,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"pminsw",    2, 0x660fea,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1192  {"pminub",    2, 0x0fda,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },  {"pminub",    2, 0x0fda,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1193  {"pminub",    2, 0x660fda,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"pminub",    2, 0x660fda,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1194  {"pmovmskb",  2, 0x0fd7,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },  {"pmovmskb",  2, 0x0fd7,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },
1195  {"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },  {"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
1196  {"pmulhuw",   2, 0x0fe4,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },  {"pmulhuw",   2, 0x0fe4,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1197  {"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1198  {"prefetchnta", 1, 0x0f18,  0, CpuSSE, FP|Modrm,        { LLongMem, 0, 0 } },  {"prefetchnta", 1, 0x0f18,  0, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { LLongMem, 0, 0 } },
1199  {"prefetcht0",  1, 0x0f18,  1, CpuSSE, FP|Modrm,        { LLongMem, 0, 0 } },  {"prefetcht0",  1, 0x0f18,  1, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { LLongMem, 0, 0 } },
1200  {"prefetcht1",  1, 0x0f18,  2, CpuSSE, FP|Modrm,        { LLongMem, 0, 0 } },  {"prefetcht1",  1, 0x0f18,  2, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { LLongMem, 0, 0 } },
1201  {"prefetcht2",  1, 0x0f18,  3, CpuSSE, FP|Modrm,        { LLongMem, 0, 0 } },  {"prefetcht2",  1, 0x0f18,  3, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { LLongMem, 0, 0 } },
1202  {"psadbw",    2, 0x0ff6,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },  {"psadbw",    2, 0x0ff6,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1203  {"psadbw",    2, 0x660ff6,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"psadbw",    2, 0x660ff6,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1204  {"pshufw",    3, 0x0f70,    X, CpuSSE, FP|Modrm,        { Imm8, RegMMX|LLongMem, RegMMX } },  {"pshufw",    3, 0x0f70,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { Imm8, RegMMX|LLongMem, RegMMX } },
1205  {"rcpps",     2, 0x0f53,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"rcpps",     2, 0x0f53,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1206  {"rcpss",     2, 0xf30f53,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"rcpss",     2, 0xf30f53,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1207  {"rsqrtps",   2, 0x0f52,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"rsqrtps",   2, 0x0f52,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1208  {"rsqrtss",   2, 0xf30f52,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"rsqrtss",   2, 0xf30f52,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1209  {"sfence",    0, 0x0fae, 0xf8, CpuSSE, FP|ImmExt,       { 0, 0, 0 } },  {"sfence",    0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } },
1210  {"shufps",    3, 0x0fc6,    X, CpuSSE, FP|Modrm,        { Imm8, RegXMM|LLongMem, RegXMM } },  {"shufps",    3, 0x0fc6,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { Imm8, RegXMM|LLongMem, RegXMM } },
1211  {"sqrtps",    2, 0x0f51,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"sqrtps",    2, 0x0f51,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1212  {"sqrtss",    2, 0xf30f51,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"sqrtss",    2, 0xf30f51,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1213  {"stmxcsr",   1, 0x0fae,    3, CpuSSE, FP|Modrm,        { WordMem, 0, 0 } },  {"stmxcsr",   1, 0x0fae,    3, CpuSSE, NoSuf|IgnoreSize|Modrm,  { WordMem, 0, 0 } },
1214  {"subps",     2, 0x0f5c,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"subps",     2, 0x0f5c,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1215  {"subss",     2, 0xf30f5c,  X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"subss",     2, 0xf30f5c,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1216  {"ucomiss",   2, 0x0f2e,    X, CpuSSE, FP|Modrm,        { RegXMM|WordMem, RegXMM, 0 } },  {"ucomiss",   2, 0x0f2e,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1217  {"unpckhps",  2, 0x0f15,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"unpckhps",  2, 0x0f15,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1218  {"unpcklps",  2, 0x0f14,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"unpcklps",  2, 0x0f14,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1219  {"xorps",     2, 0x0f57,    X, CpuSSE, FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },  {"xorps",     2, 0x0f57,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1220    
1221  /* SSE-2 instructions.  */  /* SSE-2 instructions.  */
1222    
1223  {"addpd",     2, 0x660f58,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"addpd",     2, 0x660f58,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1224  {"addsd",     2, 0xf20f58,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"addsd",     2, 0xf20f58,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1225  {"andnpd",    2, 0x660f55,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"andnpd",    2, 0x660f55,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1226  {"andpd",     2, 0x660f54,  X, CpuSSE2, FP|Modrm,       { RegXMM|WordMem, RegXMM, 0 } },  {"andpd",     2, 0x660f54,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1227  {"cmpeqpd",   2, 0x660fc2,  0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },  {"cmpeqpd",   2, 0x660fc2,  0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1228  {"cmpeqsd",   2, 0xf20fc2,  0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },  {"cmpeqsd",   2, 0xf20fc2,  0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1229  {"cmplepd",   2, 0x660fc2,  2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },  {"cmplepd",   2, 0x660fc2,  2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1230  {"cmplesd",   2, 0xf20fc2,  2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },  {"cmplesd",   2, 0xf20fc2,  2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1231  {"cmpltpd",   2, 0x660fc2,  1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },  {"cmpltpd",   2, 0x660fc2,  1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1232  {"cmpltsd",   2, 0xf20fc2,  1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },  {"cmpltsd",   2, 0xf20fc2,  1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1233  {"cmpneqpd",  2, 0x660fc2,  4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },  {"cmpneqpd",  2, 0x660fc2,  4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1234  {"cmpneqsd",  2, 0xf20fc2,  4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },  {"cmpneqsd",  2, 0xf20fc2,  4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1235  {"cmpnlepd",  2, 0x660fc2,  6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },  {"cmpnlepd",  2, 0x660fc2,  6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1236  {"cmpnlesd",  2, 0xf20fc2,  6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },  {"cmpnlesd",  2, 0xf20fc2,  6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1237  {"cmpnltpd",  2, 0x660fc2,  5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },  {"cmpnltpd",  2, 0x660fc2,  5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1238  {"cmpnltsd",  2, 0xf20fc2,  5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },  {"cmpnltsd",  2, 0xf20fc2,  5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1239  {"cmpordpd",  2, 0x660fc2,  7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },  {"cmpordpd",  2, 0x660fc2,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1240  {"cmpordsd",  2, 0xf20fc2,  7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },  {"cmpordsd",  2, 0xf20fc2,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1241  {"cmpunordpd",2, 0x660fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },  {"cmpunordpd",2, 0x660fc2,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1242  {"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },  {"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1243  {"cmppd",     3, 0x660fc2,  X, CpuSSE2, FP|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },  {"cmppd",     3, 0x660fc2,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1244  /* Intel mode string compare.  */  /* Intel mode string compare.  */
1245  {"cmpsd",     0, 0xa7,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },  {"cmpsd",     0, 0xa7,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
1246  {"cmpsd",     2, 0xa7,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },  {"cmpsd",     2, 0xa7,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
1247  {"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, FP|Modrm,       { Imm8, RegXMM|LongMem, RegXMM } },  {"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
1248  {"comisd",    2, 0x660f2f,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"comisd",    2, 0x660f2f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1249  {"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, FP|Modrm,       { RegMMX|LLongMem, RegXMM, 0 } },  {"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
1250  {"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },  {"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
1251  {"divpd",     2, 0x660f5e,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"divpd",     2, 0x660f5e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1252  {"divsd",     2, 0xf20f5e,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"divsd",     2, 0xf20f5e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1253  {"maxpd",     2, 0x660f5f,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"maxpd",     2, 0x660f5f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1254  {"maxsd",     2, 0xf20f5f,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"maxsd",     2, 0xf20f5f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1255  {"minpd",     2, 0x660f5d,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"minpd",     2, 0x660f5d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1256  {"minsd",     2, 0xf20f5d,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"minsd",     2, 0xf20f5d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1257  {"movapd",    2, 0x660f28,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"movapd",    2, 0x660f28,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1258  {"movapd",    2, 0x660f29,  X, CpuSSE2, FP|Modrm,       { RegXMM, RegXMM|LLongMem, 0 } },  {"movapd",    2, 0x660f29,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1259  {"movhpd",    2, 0x660f16,  X, CpuSSE2, FP|Modrm,       { LLongMem, RegXMM, 0 } },  {"movhpd",    2, 0x660f16,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1260  {"movhpd",    2, 0x660f17,  X, CpuSSE2, FP|Modrm,       { RegXMM, LLongMem, 0 } },  {"movhpd",    2, 0x660f17,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
1261  {"movlpd",    2, 0x660f12,  X, CpuSSE2, FP|Modrm,       { LLongMem, RegXMM, 0 } },  {"movlpd",    2, 0x660f12,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1262  {"movlpd",    2, 0x660f13,  X, CpuSSE2, FP|Modrm,       { RegXMM, LLongMem, 0 } },  {"movlpd",    2, 0x660f13,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
1263  {"movmskpd",  2, 0x660f50,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },  {"movmskpd",  2, 0x660f50,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
1264  {"movntpd",   2, 0x660f2b,  X, CpuSSE2, FP|Modrm,       { RegXMM, LLongMem, 0 } },  {"movntpd",   2, 0x660f2b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,         { RegXMM, LLongMem, 0 } },
1265  /* Intel mode string move.  */  /* Intel mode string move.  */
1266  {"movsd",     0, 0xa5,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },  {"movsd",     0, 0xa5,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
1267  {"movsd",     2, 0xa5,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },  {"movsd",     2, 0xa5,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
1268  {"movsd",     2, 0xf20f10,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"movsd",     2, 0xf20f10,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1269  {"movsd",     2, 0xf20f11,  X, CpuSSE2, FP|Modrm,       { RegXMM, RegXMM|LongMem, 0 } },  {"movsd",     2, 0xf20f11,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LongMem, 0 } },
1270  {"movupd",    2, 0x660f10,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"movupd",    2, 0x660f10,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1271  {"movupd",    2, 0x660f11,  X, CpuSSE2, FP|Modrm,       { RegXMM, RegXMM|LLongMem, 0 } },  {"movupd",    2, 0x660f11,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1272  {"mulpd",     2, 0x660f59,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"mulpd",     2, 0x660f59,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1273  {"mulsd",     2, 0xf20f59,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"mulsd",     2, 0xf20f59,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1274  {"orpd",      2, 0x660f56,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"orpd",      2, 0x660f56,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1275  {"shufpd",    3, 0x660fc6,  X, CpuSSE2, FP|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },  {"shufpd",    3, 0x660fc6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1276  {"sqrtpd",    2, 0x660f51,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"sqrtpd",    2, 0x660f51,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1277  {"sqrtsd",    2, 0xf20f51,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"sqrtsd",    2, 0xf20f51,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1278  {"subpd",     2, 0x660f5c,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"subpd",     2, 0x660f5c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1279  {"subsd",     2, 0xf20f5c,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"subsd",     2, 0xf20f5c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1280  {"ucomisd",   2, 0x660f2e,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"ucomisd",   2, 0x660f2e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1281  {"unpckhpd",  2, 0x660f15,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"unpckhpd",  2, 0x660f15,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1282  {"unpcklpd",  2, 0x660f14,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"unpcklpd",  2, 0x660f14,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1283  {"xorpd",     2, 0x660f57,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"xorpd",     2, 0x660f57,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1284  {"cvtdq2pd",  2, 0xf30fe6,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvtdq2pd",  2, 0xf30fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1285  {"cvtpd2dq",  2, 0xf20fe6,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvtpd2dq",  2, 0xf20fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1286  {"cvtdq2ps",  2, 0x0f5b,    X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvtdq2ps",  2, 0x0f5b,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1287  {"cvtpd2pi",  2, 0x660f2d,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegMMX, 0 } },  {"cvtpd2pi",  2, 0x660f2d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
1288  {"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1289  {"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1290  {"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1291  {"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },  {"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },
1292  {"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1293  {"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1294  {"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegMMX, 0 } },  {"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
1295  {"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },  {"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
1296  {"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1297  {"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1298  {"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, FP|Modrm,       { RegXMM|InvMem, RegXMM, 0 } },  {"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
1299  {"movdqa",    2, 0x660f6f,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"movdqa",    2, 0x660f6f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1300  {"movdqa",    2, 0x660f7f,  X, CpuSSE2, FP|Modrm,       { RegXMM, RegXMM|LLongMem, 0 } },  {"movdqa",    2, 0x660f7f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1301  {"movdqu",    2, 0xf30f6f,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"movdqu",    2, 0xf30f6f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1302  {"movdqu",    2, 0xf30f7f,  X, CpuSSE2, FP|Modrm,       { RegXMM, RegXMM|LLongMem, 0 } },  {"movdqu",    2, 0xf30f7f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1303  {"movdq2q",    2, 0xf20fd6,  X, CpuSSE2, FP|Modrm,      { RegXMM|InvMem, RegMMX, 0 } },  {"movdq2q",    2, 0xf20fd6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,        { RegXMM|InvMem, RegMMX, 0 } },
1304  {"movq2dq",   2, 0xf30fd6,  X, CpuSSE2, FP|Modrm,       { RegMMX|InvMem, RegXMM, 0 } },  {"movq2dq",   2, 0xf30fd6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegXMM, 0 } },
1305  {"pmuludq",   2, 0x0ff4,    X, CpuSSE2, FP|Modrm,       { RegMMX|LongMem, RegMMX, 0 } },  {"pmuludq",   2, 0x0ff4,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1306  {"pmuludq",   2, 0x660ff4,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },  {"pmuludq",   2, 0x660ff4,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1307  {"pshufd",    3, 0x660f70,  X, CpuSSE2, FP|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },  {"pshufd",    3, 0x660f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1308  {"pshufhw",   3, 0xf30f70,  X, CpuSSE2, FP|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },  {"pshufhw",   3, 0xf30f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1309  {"pshuflw",   3, 0xf20f70,  X, CpuSSE2, FP|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },  {"pshuflw",   3, 0xf20f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1310  {"pslldq",    2, 0x660f73,  7, CpuSSE2, FP|Modrm,       { Imm8, RegXMM, 0 } },  {"pslldq",    2, 0x660f73,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1311  {"psrldq",    2, 0x660f73,  3, CpuSSE2, FP|Modrm,       { Imm8, RegXMM, 0 } },  {"psrldq",    2, 0x660f73,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1312  {"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1313  {"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, FP|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },  {"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1314    
1315    /* Prescott New Instructions.  */
1316    
1317    {"addsubpd",  2, 0x660fd0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1318    {"addsubps",  2, 0xf20fd0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1319    {"cmpxchg16b",1, 0x0fc7,    1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
1320    {"fisttp",    1, 0xdf,      1, CpuPNI, sl_FP|Modrm,     { ShortMem|LongMem, 0, 0} },
1321    {"fisttp",    1, 0xdd,      1, CpuPNI, q_FP|Modrm,      { LLongMem, 0, 0} },
1322    {"fisttpll",  1, 0xdd,      1, CpuPNI, FP|Modrm,        { LLongMem, 0, 0} },
1323    {"haddpd",    2, 0x660f7c,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1324    {"haddps",    2, 0xf20f7c,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1325    {"hsubpd",    2, 0x660f7d,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1326    {"hsubps",    2, 0xf20f7d,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1327    {"lddqu",     2, 0xf20ff0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { LLongMem, RegXMM, 0 } },
1328    {"monitor",   0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt,    { 0, 0, 0} },
1329    /* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */
1330    {"monitor",   3, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt,    { Reg32, Reg32, Reg32} },
1331    {"movddup",   2, 0xf20f12,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1332    {"movshdup",  2, 0xf30f16,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1333    {"movsldup",  2, 0xf30f12,  X, CpuPNI, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1334    {"mwait",     0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt,    { 0, 0, 0} },
1335    /* Need to ensure only "mwait %eax,%ecx" is accepted.  */
1336    {"mwait",     2, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt,    { Reg32, Reg32, 0} },
1337    
1338  /* AMD 3DNow! instructions.  */  /* AMD 3DNow! instructions.  */
1339    
1340  {"prefetch", 1, 0x0f0d,    0, Cpu3dnow, FP|Modrm,               { ByteMem, 0, 0 } },  {"prefetch", 1, 0x0f0d,    0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
1341  {"prefetchw",1, 0x0f0d,    1, Cpu3dnow, FP|Modrm,               { ByteMem, 0, 0 } },  {"prefetchw",1, 0x0f0d,    1, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
1342  {"femms",    0, 0x0f0e,    X, Cpu3dnow, FP,                     { 0, 0, 0 } },  {"femms",    0, 0x0f0e,    X, Cpu3dnow, NoSuf,                  { 0, 0, 0 } },
1343  {"pavgusb",  2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pavgusb",  2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1344  {"pf2id",    2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pf2id",    2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1345  {"pf2iw",    2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },  {"pf2iw",    2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1346  {"pfacc",    2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfacc",    2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1347  {"pfadd",    2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfadd",    2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1348  {"pfcmpeq",  2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfcmpeq",  2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1349  {"pfcmpge",  2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfcmpge",  2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1350  {"pfcmpgt",  2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfcmpgt",  2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1351  {"pfmax",    2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfmax",    2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1352  {"pfmin",    2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfmin",    2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1353  {"pfmul",    2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfmul",    2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1354  {"pfnacc",   2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },  {"pfnacc",   2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1355  {"pfpnacc",  2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },  {"pfpnacc",  2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1356  {"pfrcp",    2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfrcp",    2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1357  {"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1358  {"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1359  {"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1360  {"pfrsqrt",  2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfrsqrt",  2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1361  {"pfsub",    2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfsub",    2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1362  {"pfsubr",   2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pfsubr",   2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1363  {"pi2fd",    2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pi2fd",    2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1364  {"pi2fw",    2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },  {"pi2fw",    2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1365  {"pmulhrw",  2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt,        { RegMMX|LongMem, RegMMX, 0 } },  {"pmulhrw",  2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1366  {"pswapd",   2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },  {"pswapd",   2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1367    
1368  /* AMD extensions. */  /* AMD extensions. */
1369  {"syscall",  0, 0x0f05,    X, CpuK6,    NoSuf,                  { 0, 0, 0} },  {"syscall",  0, 0x0f05,    X, CpuK6,    NoSuf,                  { 0, 0, 0} },
1370  {"sysret",   0, 0x0f07,    X, CpuK6,    lq_Suf|DefaultSize,     { 0, 0, 0} },  {"sysret",   0, 0x0f07,    X, CpuK6,    lq_Suf|DefaultSize,     { 0, 0, 0} },
1371  {"swapgs",   0, 0x0f01, 0xf8, Cpu64,    NoSuf|ImmExt,           { 0, 0, 0} },  {"swapgs",   0, 0x0f01, 0xf8, Cpu64,    NoSuf|ImmExt,           { 0, 0, 0} },
1372    {"rdtscp",   0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt,     { 0, 0, 0} },
1373    
1374    /* VIA PadLock extensions.  */
1375    {"xstorerng", 0, 0x000fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
1376    {"xcryptecb", 0, 0xf30fa7c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
1377    {"xcryptcbc", 0, 0xf30fa7d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
1378    {"xcryptcfb", 0, 0xf30fa7e0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
1379    {"xcryptofb", 0, 0xf30fa7e8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
1380    {"montmul",   0, 0xf30fa6c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
1381    {"xsha1",     0, 0xf30fa6c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
1382    {"xsha256",   0, 0xf30fa6d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
1383    /* Alias for xstorerng.  */
1384    {"xstore",    0, 0x000fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
1385    
1386  /* sentinel */  /* sentinel */
1387  {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }  {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
# Line 1356  static const template i386_optab[] = { Line 1402  static const template i386_optab[] = {
1402  #undef bwlq_Suf  #undef bwlq_Suf
1403  #undef FP  #undef FP
1404  #undef l_FP  #undef l_FP
1405    #undef q_FP
1406  #undef x_FP  #undef x_FP
1407  #undef sl_FP  #undef sl_FP
1408    
1409  #define MAX_MNEM_SIZE 16        /* for parsing insn mnemonics from input */  #define MAX_MNEM_SIZE 16        /* For parsing insn mnemonics from input.  */
   
1410    
1411  /* 386 register table.  */  /* 386 register table.  */
1412    
1413  static const reg_entry i386_regtab[] = {  static const reg_entry i386_regtab[] =
1414    /* make %st first as we test for it */  {
1415      /* Make %st first as we test for it.  */
1416    {"st", FloatReg|FloatAcc, 0, 0},    {"st", FloatReg|FloatAcc, 0, 0},
1417    /* 8 bit regs */    /* 8 bit regs */
1418  #define REGNAM_AL 1             /* Entry in i386_regtab.  */  #define REGNAM_AL 1             /* Entry in i386_regtab.  */
# Line 1413  static const reg_entry i386_regtab[] = { Line 1460  static const reg_entry i386_regtab[] = {
1460    {"r15w", Reg16, RegRex, 7},    {"r15w", Reg16, RegRex, 7},
1461    /* 32 bit regs */    /* 32 bit regs */
1462  #define REGNAM_EAX 41  #define REGNAM_EAX 41
1463    {"eax", Reg32|BaseIndex|Acc, 0, 0},  /* Must be in ax + 16 slot */    {"eax", Reg32|BaseIndex|Acc, 0, 0},  /* Must be in ax + 16 slot.  */
1464    {"ecx", Reg32|BaseIndex, 0, 1},    {"ecx", Reg32|BaseIndex, 0, 1},
1465    {"edx", Reg32|BaseIndex, 0, 2},    {"edx", Reg32|BaseIndex, 0, 2},
1466    {"ebx", Reg32|BaseIndex, 0, 3},    {"ebx", Reg32|BaseIndex, 0, 3},
# Line 1445  static const reg_entry i386_regtab[] = { Line 1492  static const reg_entry i386_regtab[] = {
1492    {"r13", Reg64|BaseIndex, RegRex, 5},    {"r13", Reg64|BaseIndex, RegRex, 5},
1493    {"r14", Reg64|BaseIndex, RegRex, 6},    {"r14", Reg64|BaseIndex, RegRex, 6},
1494    {"r15", Reg64|BaseIndex, RegRex, 7},    {"r15", Reg64|BaseIndex, RegRex, 7},
1495    /* segment registers */    /* Segment registers.  */
1496    {"es", SReg2, 0, 0},    {"es", SReg2, 0, 0},
1497    {"cs", SReg2, 0, 1},    {"cs", SReg2, 0, 1},
1498    {"ss", SReg2, 0, 2},    {"ss", SReg2, 0, 2},
1499    {"ds", SReg2, 0, 3},    {"ds", SReg2, 0, 3},
1500    {"fs", SReg3, 0, 4},    {"fs", SReg3, 0, 4},
1501    {"gs", SReg3, 0, 5},    {"gs", SReg3, 0, 5},
1502    /* control registers */    /* Control registers.  */
1503    {"cr0", Control, 0, 0},    {"cr0", Control, 0, 0},
1504    {"cr1", Control, 0, 1},    {"cr1", Control, 0, 1},
1505    {"cr2", Control, 0, 2},    {"cr2", Control, 0, 2},
# Line 1469  static const reg_entry i386_regtab[] = { Line 1516  static const reg_entry i386_regtab[] = {
1516    {"cr13", Control, RegRex, 5},    {"cr13", Control, RegRex, 5},
1517    {"cr14", Control, RegRex, 6},    {"cr14", Control, RegRex, 6},
1518    {"cr15", Control, RegRex, 7},    {"cr15", Control, RegRex, 7},
1519    /* debug registers */    /* Debug registers.  */
1520    {"db0", Debug, 0, 0},    {"db0", Debug, 0, 0},
1521    {"db1", Debug, 0, 1},    {"db1", Debug, 0, 1},
1522    {"db2", Debug, 0, 2},    {"db2", Debug, 0, 2},
# Line 1502  static const reg_entry i386_regtab[] = { Line 1549  static const reg_entry i386_regtab[] = {
1549    {"dr13", Debug, RegRex, 5},    {"dr13", Debug, RegRex, 5},
1550    {"dr14", Debug, RegRex, 6},    {"dr14", Debug, RegRex, 6},
1551    {"dr15", Debug, RegRex, 7},    {"dr15", Debug, RegRex, 7},
1552    /* test registers */    /* Test registers.  */
1553    {"tr0", Test, 0, 0},    {"tr0", Test, 0, 0},
1554    {"tr1", Test, 0, 1},    {"tr1", Test, 0, 1},
1555    {"tr2", Test, 0, 2},    {"tr2", Test, 0, 2},
# Line 1511  static const reg_entry i386_regtab[] = { Line 1558  static const reg_entry i386_regtab[] = {
1558    {"tr5", Test, 0, 5},    {"tr5", Test, 0, 5},
1559    {"tr6", Test, 0, 6},    {"tr6", Test, 0, 6},
1560    {"tr7", Test, 0, 7},    {"tr7", Test, 0, 7},
1561    /* mmx and simd registers */    /* MMX and simd registers.  */
1562    {"mm0", RegMMX, 0, 0},    {"mm0", RegMMX, 0, 0},
1563    {"mm1", RegMMX, 0, 1},    {"mm1", RegMMX, 0, 1},
1564    {"mm2", RegMMX, 0, 2},    {"mm2", RegMMX, 0, 2},
# Line 1536  static const reg_entry i386_regtab[] = { Line 1583  static const reg_entry i386_regtab[] = {
1583    {"xmm13", RegXMM, RegRex, 5},    {"xmm13", RegXMM, RegRex, 5},
1584    {"xmm14", RegXMM, RegRex, 6},    {"xmm14", RegXMM, RegRex, 6},
1585    {"xmm15", RegXMM, RegRex, 7},    {"xmm15", RegXMM, RegRex, 7},
1586    /* no type will make this register rejected for all purposes except    /* No type will make this register rejected for all purposes except
1587       for addressing.  This saves creating one extra type for RIP.  */       for addressing.  This saves creating one extra type for RIP.  */
1588    {"rip", BaseIndex, 0, 0}    {"rip", BaseIndex, 0, 0}
1589  };  };
1590    
1591  static const reg_entry i386_float_regtab[] = {  static const reg_entry i386_float_regtab[] =
1592    {
1593    {"st(0)", FloatReg|FloatAcc, 0, 0},    {"st(0)", FloatReg|FloatAcc, 0, 0},
1594    {"st(1)", FloatReg, 0, 1},    {"st(1)", FloatReg, 0, 1},
1595    {"st(2)", FloatReg, 0, 2},    {"st(2)", FloatReg, 0, 2},
# Line 1552  static const reg_entry i386_float_regtab Line 1600  static const reg_entry i386_float_regtab
1600    {"st(7)", FloatReg, 0, 7}    {"st(7)", FloatReg, 0, 7}
1601  };  };
1602    
1603  #define MAX_REG_NAME_SIZE 8     /* for parsing register names from input */  #define MAX_REG_NAME_SIZE 8     /* For parsing register names from input.  */
1604    
1605  /* segment stuff */  /* Segment stuff.  */
1606  static const seg_entry cs = { "cs", 0x2e };  static const seg_entry cs = { "cs", 0x2e };
1607  static const seg_entry ds = { "ds", 0x3e };  static const seg_entry ds = { "ds", 0x3e };
1608  static const seg_entry ss = { "ss", 0x36 };  static const seg_entry ss = { "ss", 0x36 };
# Line 1562  static const seg_entry es = { "es", 0x26 Line 1610  static const seg_entry es = { "es", 0x26
1610  static const seg_entry fs = { "fs", 0x64 };  static const seg_entry fs = { "fs", 0x64 };
1611  static const seg_entry gs = { "gs", 0x65 };  static const seg_entry gs = { "gs", 0x65 };
1612    
 /* end of opcode/i386.h */  

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