1 |
/* Opcode table for the H8/300 |
/* Opcode table for the H8/300 |
2 |
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002 |
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002, |
3 |
|
2003, 2004 |
4 |
Free Software Foundation, Inc. |
Free Software Foundation, Inc. |
5 |
Written by Steve Chamberlain <sac@cygnus.com>. |
Written by Steve Chamberlain <sac@cygnus.com>. |
6 |
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27 |
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28 |
typedef int op_type; |
typedef int op_type; |
29 |
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30 |
#define Hex0 0 |
enum h8_flags |
31 |
#define Hex1 1 |
{ |
32 |
#define Hex2 2 |
L_2 = 0x10, |
33 |
#define Hex3 3 |
L_3 = 0x20, |
34 |
#define Hex4 4 |
/* 3 bit constant, zero not accepted. */ |
35 |
#define Hex5 5 |
L_3NZ = 0x30, |
36 |
#define Hex6 6 |
L_4 = 0x40, |
37 |
#define Hex7 7 |
L_5 = 0x50, |
38 |
#define Hex8 8 |
L_8 = 0x60, |
39 |
#define Hex9 9 |
L_8U = 0x70, |
40 |
#define HexA 10 |
L_16 = 0x80, |
41 |
#define HexB 11 |
L_16U = 0x90, |
42 |
#define HexC 12 |
L_24 = 0xA0, |
43 |
#define HexD 13 |
L_32 = 0xB0, |
44 |
#define HexE 14 |
L_P = 0xC0, |
45 |
#define HexF 15 |
|
46 |
|
/* Mask to isolate the L_x size bits. */ |
47 |
#define L_8 0x01 |
SIZE = 0xF0, |
48 |
#define L_16 0x02 |
|
49 |
#define L_32 0x04 |
REG = 0x0100, |
50 |
#define L_P 0x08 |
ABS = 0x0200, |
51 |
#define L_24 0x10 |
MEMIND = 0x0300, |
52 |
#define MEMRELAX 0x20 /* move insn which may relax */ |
IMM = 0x0400, |
53 |
#define SRC 0x40 |
DISP = 0x0500, |
54 |
#define DST 0x80 |
IND = 0x0600, |
55 |
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POSTINC = 0x0700, |
56 |
#define REG 0x100 |
POSTDEC = 0x0800, |
57 |
#define EXR 0x200 |
PREINC = 0x0900, |
58 |
#define MACREG 0x800 |
PREDEC = 0x0A00, |
59 |
#define SRC_IN_DST 0x400 |
PCREL = 0x0B00, |
60 |
#define IMM 0x1000 |
KBIT = 0x0C00, |
61 |
#define DISP 0x2000 |
DBIT = 0x0D00, |
62 |
#define IND 0x4000 |
CONST_2 = 0x0E00, |
63 |
#define INC 0x8000 |
CONST_4 = 0x0F00, |
64 |
#define DEC 0x10000 |
CONST_8 = 0x1000, |
65 |
#define L_3 0x20000 |
CONST_16 = 0x1100, |
66 |
#define KBIT 0x40000 |
INDEXB = 0x1200, |
67 |
#define DBIT 0x80000 |
INDEXW = 0x1300, |
68 |
#define DISPREG 0x100000 |
INDEXL = 0x1400, |
69 |
#define IGNORE 0x200000 |
PCIDXB = 0x1500, |
70 |
#define E 0x400000 /* FIXME: end of nibble sequence? */ |
PCIDXW = 0x1600, |
71 |
#define L_2 0x800000 |
PCIDXL = 0x1700, |
72 |
#define B30 0x1000000 /* bit 3 must be low */ |
VECIND = 0x1800, |
73 |
#define B31 0x2000000 /* bit 3 must be high */ |
LOWREG = 0x1900, |
74 |
#define CCR 0x4000000 |
DATA = 0x2000, |
75 |
#define ABS 0x8000000 |
|
76 |
#define ABSJMP 0x10000000 |
/* Synonyms. */ |
77 |
#define ABS8MEM 0x20000000 |
INC = POSTINC, |
78 |
#define PCREL 0x40000000 |
DEC = PREDEC, |
79 |
#define MEMIND 0x80000000 |
/* Control Registers. */ |
80 |
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CCR = 0x4000, |
81 |
#define IMM3 IMM|L_3 |
EXR = 0x4100, |
82 |
#define IMM2 IMM|L_2 |
MACH = 0x4200, |
83 |
|
MACL = 0x4300, |
84 |
#define SIZE (L_2|L_3|L_8|L_16|L_32|L_P|L_24) |
RESERV1 = 0x4400, |
85 |
#define MODE (REG|IMM|DISP|IND|INC|DEC|CCR|ABS|MEMIND|EXR) |
RESERV2 = 0x4500, |
86 |
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VBR = 0x4600, |
87 |
#define RD8 (DST|L_8|REG) |
SBR = 0x4700, |
88 |
#define RD16 (DST|L_16|REG) |
MACREG = 0x4800, |
89 |
#define RD32 (DST|L_32|REG) |
CCR_EXR = 0x4900, |
90 |
#define RS8 (SRC|L_8|REG) |
VBR_SBR = 0x4A00, |
91 |
#define RS16 (SRC|L_16|REG) |
CC_EX_VB_SB = 0x4B00, |
92 |
#define RS32 (SRC|L_32|REG) |
RESERV3 = 0x4C00, |
93 |
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RESERV4 = 0x4D00, |
94 |
#define RSP (SRC|L_P|REG) |
RESERV5 = 0x4E00, |
95 |
#define RDP (DST|L_P|REG) |
RESERV6 = 0x4F00, |
96 |
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|
97 |
#define IMM8 (IMM|SRC|L_8) |
/* Mask to isolate the addressing mode bits (REG .. PREDEC). */ |
98 |
#define IMM16 (IMM|SRC|L_16) |
MODE = 0x7F00, |
99 |
#define IMM32 (IMM|SRC|L_32) |
|
100 |
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CTRL = 0x4000, |
101 |
#define ABS8SRC (SRC|ABS|L_8|ABS8MEM) |
|
102 |
#define ABS8DST (DST|ABS|L_8|ABS8MEM) |
NO_SYMBOLS = 0x8000, |
103 |
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SRC = 0x10000, |
104 |
#define DISP8 (PCREL|L_8) |
DST = 0x20000, |
105 |
#define DISP16 (PCREL|L_16) |
OP3 = 0x40000, |
106 |
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MEMRELAX = 0x80000, /* Move insn which may relax. */ |
107 |
#define DISP8SRC (DISP|L_8|SRC) |
|
108 |
#define DISP16SRC (DISP|L_16|SRC) |
DISPREG = 0x100000, |
109 |
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IGNORE = 0x200000, |
110 |
#define DISP8DST (DISP|L_8|DST) |
ABSJMP = 0x400000, |
111 |
#define DISP16DST (DISP|L_16|DST) |
|
112 |
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B00 = 0x800000, /* Bit 0 must be low. */ |
113 |
#define ABS16SRC (SRC|ABS|L_16) |
B01 = 0x1000000, /* Bit 0 must be high. */ |
114 |
#define ABS16DST (DST|ABS|L_16) |
B10 = 0x2000000, /* Bit 1 must be low. */ |
115 |
#define ABS24SRC (SRC|ABS|L_24) |
B11 = 0x4000000, /* Bit 1 must be high. */ |
116 |
#define ABS24DST (DST|ABS|L_24) |
B20 = 0x8000000, /* Bit 2 must be low. */ |
117 |
#define ABS32SRC (SRC|ABS|L_32) |
B21 = 0x10000000, /* Bit 2 must be high. */ |
118 |
#define ABS32DST (DST|ABS|L_32) |
B30 = 0x20000000, /* Bit 3 must be low. */ |
119 |
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B31 = 0x40000000, /* Bit 3 must be high. */ |
120 |
#define RDDEC (DST|DEC) |
E = 0x80000000, /* End of nibble sequence. */ |
121 |
#define RSINC (SRC|INC) |
|
122 |
#define RDINC (DST|INC) |
/* Immediates smaller than 8 bits are always unsigned. */ |
123 |
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IMM3 = IMM | L_3, |
124 |
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IMM4 = IMM | L_4, |
125 |
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IMM5 = IMM | L_5, |
126 |
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IMM3NZ = IMM | L_3NZ, |
127 |
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IMM2 = IMM | L_2, |
128 |
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129 |
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IMM8 = IMM | SRC | L_8, |
130 |
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IMM8U = IMM | SRC | L_8U, |
131 |
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IMM16 = IMM | SRC | L_16, |
132 |
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IMM16U = IMM | SRC | L_16U, |
133 |
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IMM32 = IMM | SRC | L_32, |
134 |
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135 |
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IMM3NZ_NS = IMM3NZ | NO_SYMBOLS, |
136 |
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IMM4_NS = IMM4 | NO_SYMBOLS, |
137 |
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IMM8U_NS = IMM8U | NO_SYMBOLS, |
138 |
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IMM16U_NS = IMM16U | NO_SYMBOLS, |
139 |
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140 |
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RD8 = DST | L_8 | REG, |
141 |
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RD16 = DST | L_16 | REG, |
142 |
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RD32 = DST | L_32 | REG, |
143 |
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R3_8 = OP3 | L_8 | REG, |
144 |
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R3_16 = OP3 | L_16 | REG, |
145 |
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R3_32 = OP3 | L_32 | REG, |
146 |
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RS8 = SRC | L_8 | REG, |
147 |
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RS16 = SRC | L_16 | REG, |
148 |
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RS32 = SRC | L_32 | REG, |
149 |
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150 |
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RSP = SRC | L_P | REG, |
151 |
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RDP = DST | L_P | REG, |
152 |
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153 |
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PCREL8 = PCREL | L_8, |
154 |
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PCREL16 = PCREL | L_16, |
155 |
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156 |
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OP3PCREL8 = OP3 | PCREL | L_8, |
157 |
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OP3PCREL16 = OP3 | PCREL | L_16, |
158 |
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159 |
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INDEXB16 = INDEXB | L_16, |
160 |
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INDEXW16 = INDEXW | L_16, |
161 |
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INDEXL16 = INDEXL | L_16, |
162 |
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INDEXB16D = INDEXB | L_16 | DST, |
163 |
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INDEXW16D = INDEXW | L_16 | DST, |
164 |
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INDEXL16D = INDEXL | L_16 | DST, |
165 |
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166 |
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INDEXB32 = INDEXB | L_32, |
167 |
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INDEXW32 = INDEXW | L_32, |
168 |
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INDEXL32 = INDEXL | L_32, |
169 |
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INDEXB32D = INDEXB | L_32 | DST, |
170 |
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INDEXW32D = INDEXW | L_32 | DST, |
171 |
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INDEXL32D = INDEXL | L_32 | DST, |
172 |
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173 |
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DISP2SRC = DISP | L_2 | SRC, |
174 |
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DISP16SRC = DISP | L_16 | SRC, |
175 |
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DISP32SRC = DISP | L_32 | SRC, |
176 |
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177 |
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DISP2DST = DISP | L_2 | DST, |
178 |
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DISP16DST = DISP | L_16 | DST, |
179 |
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DISP32DST = DISP | L_32 | DST, |
180 |
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181 |
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DSTDISPREG = DST | DISPREG, |
182 |
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SRCDISPREG = SRC | DISPREG, |
183 |
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184 |
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ABS8SRC = SRC | ABS | L_8, |
185 |
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ABS16SRC = SRC | ABS | L_16U, |
186 |
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ABS24SRC = SRC | ABS | L_24, |
187 |
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ABS32SRC = SRC | ABS | L_32, |
188 |
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189 |
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ABS8DST = DST | ABS | L_8, |
190 |
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ABS16DST = DST | ABS | L_16U, |
191 |
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ABS24DST = DST | ABS | L_24, |
192 |
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ABS32DST = DST | ABS | L_32, |
193 |
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194 |
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ABS8OP3 = OP3 | ABS | L_8, |
195 |
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ABS16OP3 = OP3 | ABS | L_16U, |
196 |
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ABS24OP3 = OP3 | ABS | L_24, |
197 |
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ABS32OP3 = OP3 | ABS | L_32, |
198 |
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|
199 |
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RDDEC = DST | DEC, |
200 |
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RSINC = SRC | INC, |
201 |
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RDINC = DST | INC, |
202 |
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203 |
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RSPOSTINC = SRC | POSTINC, |
204 |
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RDPOSTINC = DST | POSTINC, |
205 |
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RSPREINC = SRC | PREINC, |
206 |
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RDPREINC = DST | PREINC, |
207 |
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RSPOSTDEC = SRC | POSTDEC, |
208 |
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RDPOSTDEC = DST | POSTDEC, |
209 |
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RSPREDEC = SRC | PREDEC, |
210 |
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RDPREDEC = DST | PREDEC, |
211 |
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212 |
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RSIND = SRC | IND, |
213 |
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RDIND = DST | IND, |
214 |
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R3_IND = OP3 | IND, |
215 |
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|
216 |
#define RDIND (DST|IND) |
#define MS32 (SRC | L_32 | MACREG) |
217 |
#define RSIND (SRC|IND) |
#define MD32 (DST | L_32 | MACREG) |
218 |
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|
219 |
#if 1 |
#if 1 |
220 |
#define OR8 RS8 /* ??? OR as in One Register? */ |
OR8 = RS8, /* ??? OR as in One Register. */ |
221 |
#define OR16 RS16 |
OR16 = RS16, |
222 |
#define OR32 RS32 |
OR32 = RS32, |
223 |
#else |
#else |
224 |
#define OR8 RD8 |
OR8 = RD8, |
225 |
#define OR16 RD16 |
OR16 = RD16, |
226 |
#define OR32 RD32 |
OR32 = RD32 |
227 |
#endif |
#endif |
228 |
|
}; |
229 |
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|
230 |
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enum ctrlreg |
231 |
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{ |
232 |
|
C_CCR = 0, |
233 |
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C_EXR = 1, |
234 |
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C_MACH = 2, |
235 |
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C_MACL = 3, |
236 |
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C_VBR = 6, |
237 |
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C_SBR = 7 |
238 |
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}; |
239 |
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240 |
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enum {MAX_CODE_NIBBLES = 33}; |
241 |
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|
242 |
struct code |
struct code |
243 |
{ |
{ |
244 |
op_type nib[30]; |
op_type nib[MAX_CODE_NIBBLES]; |
245 |
}; |
}; |
246 |
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|
247 |
struct arg |
struct arg |
249 |
op_type nib[3]; |
op_type nib[3]; |
250 |
}; |
}; |
251 |
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|
252 |
|
/* Availability of instructions on processor models. */ |
253 |
|
enum h8_model |
254 |
|
{ |
255 |
|
AV_H8, |
256 |
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AV_H8H, |
257 |
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AV_H8S, |
258 |
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AV_H8SX |
259 |
|
}; |
260 |
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|
261 |
struct h8_opcode |
struct h8_opcode |
262 |
{ |
{ |
263 |
int how; |
int how; |
264 |
int inbase; |
enum h8_model available; |
265 |
int time; |
int time; |
266 |
char *name; |
char *name; |
267 |
struct arg args; |
struct arg args; |
268 |
struct code data; |
struct code data; |
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int length; |
|
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int noperands; |
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int idx; |
|
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int size; |
|
269 |
}; |
}; |
270 |
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271 |
#ifdef DEFINE_TABLE |
#ifdef DEFINE_TABLE |
272 |
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|
273 |
#define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\ |
#define DATA2 DATA, DATA |
274 |
{ code, 1, 2, name, {{imm,RD8,E}}, {{op00, op01, imm, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\ |
#define DATA3 DATA, DATA, DATA |
275 |
{ code, 1, 6, name, {{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}, 0, 0, 0, 0},\ |
#define DATA5 DATA, DATA, DATA, DATA, DATA |
276 |
{ code, 1, 6, name, {{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}\ |
#define DATA7 DATA, DATA, DATA, DATA, DATA, DATA, DATA |
277 |
,{ code, 0, 6, name, {{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0},\ |
|
278 |
{ code, 0, 6, name, {{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0} |
#define IMM8LIST IMM8, DATA |
279 |
|
#define IMM16LIST IMM16, DATA3 |
280 |
|
#define IMM16ULIST IMM16U, DATA3 |
281 |
|
#define IMM24LIST IMM24, DATA5 |
282 |
|
#define IMM32LIST IMM32, DATA7 |
283 |
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|
284 |
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#define DISP16LIST DISP | L_16, DATA3 |
285 |
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#define DISP24LIST DISP | L_24, DATA5 |
286 |
|
#define DISP32LIST DISP | L_32, DATA7 |
287 |
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|
288 |
|
#define ABS8LIST ABS | L_8, DATA |
289 |
|
#define ABS16LIST ABS | L_16U, DATA3 |
290 |
|
#define ABS24LIST ABS | L_24, DATA5 |
291 |
|
#define ABS32LIST ABS | L_32, DATA7 |
292 |
|
|
293 |
|
#define DSTABS8LIST DST | ABS | L_8, DATA |
294 |
|
#define DSTABS16LIST DST | ABS | L_16U, DATA3 |
295 |
|
#define DSTABS24LIST DST | ABS | L_24, DATA5 |
296 |
|
#define DSTABS32LIST DST | ABS | L_32, DATA7 |
297 |
|
|
298 |
|
#define OP3ABS8LIST OP3 | ABS | L_8, DATA |
299 |
|
#define OP3ABS16LIST OP3 | ABS | L_16, DATA3 |
300 |
|
#define OP3ABS24LIST OP3 | ABS | L_24, DATA5 |
301 |
|
#define OP3ABS32LIST OP3 | ABS | L_32, DATA7 |
302 |
|
|
303 |
|
#define DSTDISP16LIST DST | DISP | L_16, DATA3 |
304 |
|
#define DSTDISP24LIST DST | DISP | L_24, DATA5 |
305 |
|
#define DSTDISP32LIST DST | DISP | L_32, DATA7 |
306 |
|
|
307 |
|
#define A16LIST L_16, DATA3 |
308 |
|
#define A24LIST L_24, DATA5 |
309 |
|
#define A32LIST L_32, DATA7 |
310 |
|
|
311 |
|
/* Extended Operand Prefixes: */ |
312 |
|
|
313 |
|
#define PREFIX_010 0x0, 0x1, 0x0 |
314 |
|
#define PREFIX_015 0x0, 0x1, 0x5 |
315 |
|
#define PREFIX_017 0x0, 0x1, 0x7 |
316 |
|
|
317 |
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#define PREFIX_0100 0x0, 0x1, 0x0, 0x0 |
318 |
|
#define PREFIX_010_D2 0x0, 0x1, 0x0, B30 | B21 | DISP2SRC |
319 |
|
#define PREFIX_0101 0x0, 0x1, 0x0, 0x1 |
320 |
|
#define PREFIX_0102 0x0, 0x1, 0x0, 0x2 |
321 |
|
#define PREFIX_0103 0x0, 0x1, 0x0, 0x3 |
322 |
|
#define PREFIX_0104 0x0, 0x1, 0x0, 0x4 |
323 |
|
#define PREFIX_0105 0x0, 0x1, 0x0, 0x5 |
324 |
|
#define PREFIX_0106 0x0, 0x1, 0x0, 0x6 |
325 |
|
#define PREFIX_0107 0x0, 0x1, 0x0, 0x7 |
326 |
|
#define PREFIX_0108 0x0, 0x1, 0x0, 0x8 |
327 |
|
#define PREFIX_0109 0x0, 0x1, 0x0, 0x9 |
328 |
|
#define PREFIX_010A 0x0, 0x1, 0x0, 0xa |
329 |
|
#define PREFIX_010D 0x0, 0x1, 0x0, 0xd |
330 |
|
#define PREFIX_010E 0x0, 0x1, 0x0, 0xe |
331 |
|
|
332 |
|
#define PREFIX_0150 0x0, 0x1, 0x5, 0x0 |
333 |
|
#define PREFIX_015_D2 0x0, 0x1, 0x5, B30 | B21 | DISP2SRC |
334 |
|
#define PREFIX_0151 0x0, 0x1, 0x5, 0x1 |
335 |
|
#define PREFIX_0152 0x0, 0x1, 0x5, 0x2 |
336 |
|
#define PREFIX_0153 0x0, 0x1, 0x5, 0x3 |
337 |
|
#define PREFIX_0154 0x0, 0x1, 0x5, 0x4 |
338 |
|
#define PREFIX_0155 0x0, 0x1, 0x5, 0x5 |
339 |
|
#define PREFIX_0156 0x0, 0x1, 0x5, 0x6 |
340 |
|
#define PREFIX_0157 0x0, 0x1, 0x5, 0x7 |
341 |
|
#define PREFIX_0158 0x0, 0x1, 0x5, 0x8 |
342 |
|
#define PREFIX_0159 0x0, 0x1, 0x5, 0x9 |
343 |
|
#define PREFIX_015A 0x0, 0x1, 0x5, 0xa |
344 |
|
#define PREFIX_015D 0x0, 0x1, 0x5, 0xd |
345 |
|
#define PREFIX_015E 0x0, 0x1, 0x5, 0xe |
346 |
|
#define PREFIX_015F 0x0, 0x1, 0x5, 0xf |
347 |
|
|
348 |
|
#define PREFIX_0170 0x0, 0x1, 0x7, 0x0 |
349 |
|
#define PREFIX_017_D2S 0x0, 0x1, 0x7, B30 | B21 | DISP2SRC |
350 |
|
#define PREFIX_017_D2D 0x0, 0x1, 0x7, B30 | B21 | DISP2DST |
351 |
|
#define PREFIX_0171 0x0, 0x1, 0x7, 0x1 |
352 |
|
#define PREFIX_0172 0x0, 0x1, 0x7, 0x2 |
353 |
|
#define PREFIX_0173 0x0, 0x1, 0x7, 0x3 |
354 |
|
#define PREFIX_0174 0x0, 0x1, 0x7, 0x4 |
355 |
|
#define PREFIX_0175 0x0, 0x1, 0x7, 0x5 |
356 |
|
#define PREFIX_0176 0x0, 0x1, 0x7, 0x6 |
357 |
|
#define PREFIX_0177 0x0, 0x1, 0x7, 0x7 |
358 |
|
#define PREFIX_0178 0x0, 0x1, 0x7, 0x8 |
359 |
|
#define PREFIX_0179 0x0, 0x1, 0x7, 0x9 |
360 |
|
#define PREFIX_017A 0x0, 0x1, 0x7, 0xa |
361 |
|
#define PREFIX_017D 0x0, 0x1, 0x7, 0xd |
362 |
|
#define PREFIX_017E 0x0, 0x1, 0x7, 0xe |
363 |
|
#define PREFIX_017F 0x0, 0x1, 0x7, 0xf |
364 |
|
|
365 |
|
#define PREFIX_6A15 0x6, 0xa, 0x1, 0x5 |
366 |
|
#define PREFIX_6A35 0x6, 0xa, 0x3, 0x5 |
367 |
|
#define PREFIX_6B15 0x6, 0xb, 0x1, 0x5 |
368 |
|
#define PREFIX_6B35 0x6, 0xb, 0x3, 0x5 |
369 |
|
|
370 |
|
#define PREFIX_78R4 0x7, 0x8, B31 | DISPREG, 0x4 |
371 |
|
#define PREFIX_78R5 0x7, 0x8, B31 | DISPREG, 0x5 |
372 |
|
#define PREFIX_78R6 0x7, 0x8, B31 | DISPREG, 0x6 |
373 |
|
#define PREFIX_78R7 0x7, 0x8, B31 | DISPREG, 0x7 |
374 |
|
|
375 |
|
#define PREFIX_78R4W 0x7, 0x8, B30 | DISPREG, 0x4 |
376 |
|
#define PREFIX_78R5W 0x7, 0x8, B30 | DISPREG, 0x5 |
377 |
|
#define PREFIX_78R6W 0x7, 0x8, B30 | DISPREG, 0x6 |
378 |
|
#define PREFIX_78R7W 0x7, 0x8, B30 | DISPREG, 0x7 |
379 |
|
|
380 |
|
#define PREFIX_78R4WD 0x7, 0x8, B30 | DSTDISPREG, 0x4 |
381 |
|
#define PREFIX_78R5WD 0x7, 0x8, B30 | DSTDISPREG, 0x5 |
382 |
|
#define PREFIX_78R6WD 0x7, 0x8, B30 | DSTDISPREG, 0x6 |
383 |
|
#define PREFIX_78R7WD 0x7, 0x8, B30 | DSTDISPREG, 0x7 |
384 |
|
|
385 |
|
#define PREFIX_7974 0x7, 0x9, 0x7, 0x4 |
386 |
|
#define PREFIX_7A74 0x7, 0xa, 0x7, 0x4 |
387 |
|
#define PREFIX_7A7C 0x7, 0xa, 0x7, 0xc |
388 |
|
|
389 |
|
|
390 |
|
/* Source standard fragment: */ |
391 |
|
#define FROM_IND 0, RSIND |
392 |
|
#define FROM_POSTINC 8, RSPOSTINC |
393 |
|
#define FROM_POSTDEC 10, RSPOSTDEC |
394 |
|
#define FROM_PREINC 9, RSPREINC |
395 |
|
#define FROM_PREDEC 11, RSPREDEC |
396 |
|
#define FROM_DISP2 B30 | B20 | DISP2SRC, DISPREG |
397 |
|
#define FROM_DISP16 12, B30 | DISPREG |
398 |
|
#define FROM_DISP32 12, B31 | DISPREG |
399 |
|
#define FROM_DISP16B 13, B30 | DISPREG |
400 |
|
#define FROM_DISP16W 14, B30 | DISPREG |
401 |
|
#define FROM_DISP16L 15, B30 | DISPREG |
402 |
|
#define FROM_DISP32B 13, B31 | DISPREG |
403 |
|
#define FROM_DISP32W 14, B31 | DISPREG |
404 |
|
#define FROM_DISP32L 15, B31 | DISPREG |
405 |
|
#define FROM_ABS16 4, B30 | IGNORE |
406 |
|
#define FROM_ABS32 4, B31 | IGNORE |
407 |
|
|
408 |
|
/* Destination standard fragment: */ |
409 |
|
#define TO_IND 0, RDIND |
410 |
|
#define TO_IND_MOV 0, RDIND | B30 |
411 |
|
#define TO_POSTINC 8, RDPOSTINC |
412 |
|
#define TO_POSTINC_MOV 8, RDPOSTINC | B30 |
413 |
|
#define TO_POSTDEC 10, RDPOSTDEC |
414 |
|
#define TO_POSTDEC_MOV 10, RDPOSTDEC | B30 |
415 |
|
#define TO_PREINC 9, RDPREINC |
416 |
|
#define TO_PREINC_MOV 9, RDPREINC | B30 |
417 |
|
#define TO_PREDEC 11, RDPREDEC |
418 |
|
#define TO_PREDEC_MOV 11, RDPREDEC | B30 |
419 |
|
#define TO_DISP2 B30 | B20 | DISP2DST, DSTDISPREG |
420 |
|
#define TO_DISP2_MOV B30 | B20 | DISP2DST, DSTDISPREG | B30 |
421 |
|
#define TO_DISP16 12, B30 | DSTDISPREG |
422 |
|
#define TO_DISP32 12, B31 | DSTDISPREG |
423 |
|
#define TO_DISP16B 13, B30 | DSTDISPREG |
424 |
|
#define TO_DISP16W 14, B30 | DSTDISPREG |
425 |
|
#define TO_DISP16L 15, B30 | DSTDISPREG |
426 |
|
#define TO_DISP32B 13, B31 | DSTDISPREG |
427 |
|
#define TO_DISP32W 14, B31 | DSTDISPREG |
428 |
|
#define TO_DISP32L 15, B31 | DSTDISPREG |
429 |
|
#define TO_ABS16 4, B30 | IGNORE |
430 |
|
#define TO_ABS32 4, B31 | IGNORE |
431 |
|
|
432 |
|
/* Source fragment for three-word instruction: */ |
433 |
|
#define TFROM_IND 6, 9, B30 | RSIND, 12 |
434 |
|
#define TFROM_DISP2 6, 9, B30 | DISPREG, 12 |
435 |
|
#define TFROM_ABS16 6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST |
436 |
|
#define TFROM_ABS32 6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST |
437 |
|
#define TFROM_POSTINC 6, 13, B30 | RSPOSTINC, 12 |
438 |
|
#define TFROM_PREINC 6, 13, B30 | RSPREINC, 12 |
439 |
|
#define TFROM_POSTDEC 6, 13, B30 | RSPOSTDEC, 12 |
440 |
|
#define TFROM_PREDEC 6, 13, B30 | RSPREDEC, 12 |
441 |
|
#define TFROM_DISP16 6, 15, B30 | DISPREG, 12, DISP16LIST |
442 |
|
#define TFROM_DISP32 6, 11, 2, 12, DISP32LIST |
443 |
|
#define TFROM_DISP16B 6, 15, B30 | DISPREG, 12, DISP16LIST |
444 |
|
#define TFROM_DISP16W 6, 15, B30 | DISPREG, 12, DISP16LIST |
445 |
|
#define TFROM_DISP16L 6, 15, B30 | DISPREG, 12, DISP16LIST |
446 |
|
#define TFROM_DISP32B 6, 11, 2, 12, DISP32LIST |
447 |
|
#define TFROM_DISP32W 6, 11, 2, 12, DISP32LIST |
448 |
|
#define TFROM_DISP32L 6, 11, 2, 12, DISP32LIST |
449 |
|
#define TFROM_ABS16W 6, 11, 1, 12, ABS16LIST |
450 |
|
#define TFROM_ABS32W 6, 11, 3, 12, ABS32LIST |
451 |
|
|
452 |
|
/* Source fragment for three-word instruction: */ |
453 |
|
#define TFROM_IND_B 6, 8, B30 | RSIND, 12 |
454 |
|
#define TFROM_ABS16_B 6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST |
455 |
|
#define TFROM_ABS32_B 6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST |
456 |
|
|
457 |
|
#define TFROM_DISP2_B 6, 8, B30 | DISPREG, 12 |
458 |
|
#define TFROM_POSTINC_B 6, 12, B30 | RSPOSTINC, 12 |
459 |
|
#define TFROM_PREINC_B 6, 12, B30 | RSPREINC, 12 |
460 |
|
#define TFROM_POSTDEC_B 6, 12, B30 | RSPOSTDEC, 12 |
461 |
|
#define TFROM_PREDEC_B 6, 12, B30 | RSPREDEC, 12 |
462 |
|
#define TFROM_DISP16_B 6, 14, B30 | DISPREG, 12, DISP16LIST |
463 |
|
#define TFROM_DISP32_B 6, 10, 2, 12, DISP32LIST |
464 |
|
#define TFROM_DISP16B_B 6, 14, B30 | DISPREG, 12, DISP16LIST |
465 |
|
#define TFROM_DISP16W_B 6, 14, B30 | DISPREG, 12, DISP16LIST |
466 |
|
#define TFROM_DISP16L_B 6, 14, B30 | DISPREG, 12, DISP16LIST |
467 |
|
#define TFROM_DISP32B_B 6, 10, 2, 12, DISP32LIST |
468 |
|
#define TFROM_DISP32W_B 6, 10, 2, 12, DISP32LIST |
469 |
|
#define TFROM_DISP32L_B 6, 10, 2, 12, DISP32LIST |
470 |
|
|
471 |
|
#define TFROM_ABS16W_B 6, 10, 1, 12, ABS16LIST |
472 |
|
#define TFROM_ABS32W_B 6, 10, 3, 12, ABS32LIST |
473 |
|
|
474 |
|
/* Extended Operand Class Expanders: */ |
475 |
|
|
476 |
|
#define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \ |
477 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, E}}}, \ |
478 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \ |
479 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \ |
480 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, E}}}, \ |
481 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, E}}}, \ |
482 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, E}}}, \ |
483 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, DSTDISP16LIST, E}}}, \ |
484 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, DSTDISP32LIST, E}}}, \ |
485 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \ |
486 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \ |
487 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \ |
488 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \ |
489 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \ |
490 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \ |
491 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, DSTABS16LIST, E}}}, \ |
492 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, DSTABS32LIST, E}}} |
493 |
|
|
494 |
|
#define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \ |
495 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, SRC_SUFFIX, E}}}, \ |
496 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \ |
497 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \ |
498 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, SRC_SUFFIX, E}}}, \ |
499 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, SRC_SUFFIX, E}}}, \ |
500 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, SRC_SUFFIX, E}}}, \ |
501 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ |
502 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ |
503 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ |
504 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ |
505 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ |
506 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ |
507 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ |
508 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ |
509 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, SRC_SUFFIX, DSTABS16LIST, E}}}, \ |
510 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, SRC_SUFFIX, DSTABS32LIST, E}}} |
511 |
|
|
512 |
|
#define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \ |
513 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, 0, RDIND, IMM8LIST, E}}}, \ |
514 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 8, RDPOSTINC, IMM8LIST, E}}}, \ |
515 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \ |
516 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 9, RDPREINC, IMM8LIST, E}}}, \ |
517 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, 11, RDPREDEC, IMM8LIST, E}}}, \ |
518 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \ |
519 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ |
520 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ |
521 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ |
522 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ |
523 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ |
524 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ |
525 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ |
526 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ |
527 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, 4, B30 | IGNORE, IMM8LIST, DSTABS16LIST, E}}}, \ |
528 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, 4, B31 | IGNORE, IMM8LIST, DSTABS32LIST, E}}} |
529 |
|
|
530 |
|
#define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \ |
531 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, LIST, 0, RDIND, DATA2, E}}}, \ |
532 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, LIST, 8, RDPOSTINC, DATA2, E}}}, \ |
533 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \ |
534 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, LIST, 9, RDPREINC, DATA2, E}}}, \ |
535 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, LIST, 11, RDPREDEC, DATA2, E}}}, \ |
536 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \ |
537 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ |
538 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ |
539 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ |
540 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ |
541 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ |
542 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ |
543 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ |
544 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ |
545 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, LIST, 4, B30 | IGNORE, DATA2, DSTABS16LIST, E}}}, \ |
546 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, LIST, 4, B31 | IGNORE, DATA2, DSTABS32LIST, E}}} |
547 |
|
|
548 |
|
#define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ |
549 |
|
{CODE, AV_H8, 4, NAME, {{SRC, RDIND, E}}, {{ 6, OP1, B31 | RDIND, SRC, E}}}, \ |
550 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3, 6, OP3, B31 | RDPOSTINC, SRC, E}}}, \ |
551 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1, 6, OP3, B31 | RDPOSTDEC, SRC, E}}}, \ |
552 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 2, 6, OP3, B31 | RDPREINC, SRC, E}}}, \ |
553 |
|
{CODE, AV_H8, 6, NAME, {{SRC, RDPREDEC, E}}, {{ 6, OP3, B31 | RDPREDEC, SRC, E}}}, \ |
554 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC, E}}}, \ |
555 |
|
{CODE, AV_H8, 6, NAME, {{SRC, DISP16DST, E}}, {{ 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ |
556 |
|
{CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ |
557 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ |
558 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ |
559 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ |
560 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ |
561 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ |
562 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ |
563 |
|
{CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ |
564 |
|
{CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} |
565 |
|
|
566 |
|
#define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ |
567 |
|
{CODE, AV_H8, 4, NAME, {{RSIND, DST, E}}, {{ 6, OP1, B30 | RSIND, DST, E}}}, \ |
568 |
|
{CODE, AV_H8, 6, NAME, {{RSPOSTINC, DST, E}}, {{ 6, OP3, B30 | RSPOSTINC, DST, E}}}, \ |
569 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2, 6, OP3, B30 | RSPOSTDEC, DST, E}}}, \ |
570 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, 1, 6, OP3, B30 | RSPREINC, DST, E}}}, \ |
571 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, 3, 6, OP3, B30 | RSPREDEC, DST, E}}}, \ |
572 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG, DST, E}}}, \ |
573 |
|
{CODE, AV_H8, 6, NAME, {{DISP16SRC, DST, E}}, {{ 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ |
574 |
|
{CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, DISP32LIST, E}}}, \ |
575 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, 1, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ |
576 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, 2, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ |
577 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, 3, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ |
578 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}}, \ |
579 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{7, 8, B30 | DISPREG, 2, 6, OP2, 2, DST, DISP32LIST, E}}}, \ |
580 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{7, 8, B30 | DISPREG, 3, 6, OP2, 2, DST, DISP32LIST, E}}}, \ |
581 |
|
{CODE, AV_H8, 4, NAME, {{ABS16SRC, DST, E}}, {{ 6, OP2, 0, DST, RELAX16 | ABS16LIST, E}}}, \ |
582 |
|
{CODE, AV_H8, 6, NAME, {{ABS32SRC, DST, E}}, {{ 6, OP2, 2, DST, MEMRELAX | ABS32LIST, E}}} |
583 |
|
|
584 |
|
/* Expansion macros for two-word (plus data) instructions. */ |
585 |
|
|
586 |
|
/* Expansion from one source to "standard" destinations. */ |
587 |
|
#define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \ |
588 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \ |
589 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \ |
590 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, NIB1, NIB2, E}}}, \ |
591 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, NIB1, NIB2, E}}}, \ |
592 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, NIB1, NIB2, E}}}, \ |
593 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ |
594 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ |
595 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ |
596 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ |
597 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ |
598 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ |
599 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ |
600 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} |
601 |
|
|
602 |
|
/* Expansion from one destination to "standard" sources. */ |
603 |
|
#define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \ |
604 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \ |
605 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \ |
606 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, FROM_PREINC, NIB1, NIB2, E}}}, \ |
607 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, FROM_PREDEC, NIB1, NIB2, E}}}, \ |
608 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, FROM_DISP2, NIB1, NIB2, E}}}, \ |
609 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16, NIB1, NIB2, DISP16LIST, E}}}, \ |
610 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32, NIB1, NIB2, DISP32LIST, E}}}, \ |
611 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \ |
612 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \ |
613 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \ |
614 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \ |
615 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \ |
616 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}} |
617 |
|
|
618 |
|
/* Expansion from immediate source to "standard" destinations. */ |
619 |
|
#define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \ |
620 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \ |
621 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \ |
622 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \ |
623 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \ |
624 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \ |
625 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ |
626 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ |
627 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ |
628 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ |
629 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ |
630 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ |
631 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ |
632 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}} |
633 |
|
|
634 |
|
/* Expansion from abs/disp source to "standard" destinations. */ |
635 |
|
#define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \ |
636 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \ |
637 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \ |
638 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, DSTLIST, TO_PREINC, NIB1, NIB2, E}}}, \ |
639 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, DSTLIST, TO_PREDEC, NIB1, NIB2, E}}}, \ |
640 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, DSTLIST, TO_DISP2, NIB1, NIB2, E}}}, \ |
641 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ |
642 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ |
643 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ |
644 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ |
645 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ |
646 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ |
647 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ |
648 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} |
649 |
|
|
650 |
|
/* Expansion from ind source to "standard" destinations. */ |
651 |
|
#define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \ |
652 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \ |
653 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \ |
654 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC, OPCODE, IGNORE, E}}}, \ |
655 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC, OPCODE, IGNORE, E}}}, \ |
656 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2, OPCODE, IGNORE, E}}}, \ |
657 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ |
658 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ |
659 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ |
660 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ |
661 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ |
662 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ |
663 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ |
664 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}} |
665 |
|
|
666 |
|
/* Expansion macros for three word (plus data) instructions. */ |
667 |
|
|
668 |
|
#define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ |
669 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ |
670 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ |
671 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ |
672 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ |
673 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ |
674 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ |
675 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ |
676 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ |
677 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ |
678 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ |
679 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ |
680 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ |
681 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}} |
682 |
|
|
683 |
|
#define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ |
684 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, INFIX, 0, RDIND, OPCODE, B30 | IGNORE, E}}}, \ |
685 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ |
686 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ |
687 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ |
688 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ |
689 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ |
690 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ |
691 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ |
692 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ |
693 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ |
694 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ |
695 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ |
696 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ |
697 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ |
698 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, INFIX, 4, B30 | IGNORE, OPCODE, B30 | IGNORE, DSTABS16LIST, E}}}, \ |
699 |
|
{CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, INFIX, 4, B31 | IGNORE, OPCODE, B30 | IGNORE, DSTABS32LIST, E}}} |
700 |
|
|
701 |
|
|
702 |
|
#define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \ |
703 |
|
EXPAND3_L_SRC (CODE, 6, NAME, RSIND, PREFIX_0104, TFROM_IND, OPCODE), \ |
704 |
|
EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104, TFROM_POSTINC, OPCODE), \ |
705 |
|
EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106, TFROM_POSTDEC, OPCODE), \ |
706 |
|
EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC, PREFIX_0105, TFROM_PREINC, OPCODE), \ |
707 |
|
EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC, PREFIX_0107, TFROM_PREDEC, OPCODE), \ |
708 |
|
EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC, PREFIX_010_D2, TFROM_DISP2, OPCODE), \ |
709 |
|
EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104, TFROM_DISP16, OPCODE), \ |
710 |
|
EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4, TFROM_DISP32, OPCODE), \ |
711 |
|
EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16, PREFIX_0105, TFROM_DISP16B, OPCODE), \ |
712 |
|
EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16, PREFIX_0106, TFROM_DISP16W, OPCODE), \ |
713 |
|
EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16, PREFIX_0107, TFROM_DISP16L, OPCODE), \ |
714 |
|
EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32, PREFIX_78R5, TFROM_DISP32B, OPCODE), \ |
715 |
|
EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32, PREFIX_78R6, TFROM_DISP32W, OPCODE), \ |
716 |
|
EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32, PREFIX_78R7, TFROM_DISP32L, OPCODE), \ |
717 |
|
EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC, PREFIX_0104, TFROM_ABS16, OPCODE), \ |
718 |
|
EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC, PREFIX_0104, TFROM_ABS32, OPCODE) |
719 |
|
|
720 |
|
|
721 |
|
#define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \ |
722 |
|
EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154, TFROM_POSTINC, OPCODE), \ |
723 |
|
EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156, TFROM_POSTDEC, OPCODE), \ |
724 |
|
EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0155, TFROM_PREINC, OPCODE), \ |
725 |
|
EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0157, TFROM_PREDEC, OPCODE), \ |
726 |
|
EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_015_D2, TFROM_DISP2, OPCODE), \ |
727 |
|
EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154, TFROM_DISP16, OPCODE), \ |
728 |
|
EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32, OPCODE), \ |
729 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0155, TFROM_DISP16B, OPCODE), \ |
730 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0156, TFROM_DISP16W, OPCODE), \ |
731 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0157, TFROM_DISP16L, OPCODE), \ |
732 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B, OPCODE), \ |
733 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W, OPCODE), \ |
734 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L, OPCODE) |
735 |
|
|
736 |
|
#define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \ |
737 |
|
EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174, TFROM_POSTINC_B, OPCODE), \ |
738 |
|
EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176, TFROM_POSTDEC_B, OPCODE), \ |
739 |
|
EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0175, TFROM_PREINC_B, OPCODE), \ |
740 |
|
EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0177, TFROM_PREDEC_B, OPCODE), \ |
741 |
|
EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_017_D2S, TFROM_DISP2_B, OPCODE), \ |
742 |
|
EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174, TFROM_DISP16_B, OPCODE), \ |
743 |
|
EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32_B, OPCODE), \ |
744 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0175, TFROM_DISP16B_B, OPCODE), \ |
745 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0176, TFROM_DISP16W_B, OPCODE), \ |
746 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0177, TFROM_DISP16L_B, OPCODE), \ |
747 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B_B, OPCODE), \ |
748 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W_B, OPCODE), \ |
749 |
|
EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L_B, OPCODE) |
750 |
|
|
751 |
|
|
752 |
|
/* Use the expansion macros to fill out the opcode table. */ |
753 |
|
|
754 |
|
#define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \ |
755 |
|
{CODE, AV_H8SX, 0, NAME, {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, OP2, RS8, IGNORE, E}}}, \ |
756 |
|
EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \ |
757 |
|
{CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, OP2, RS8, IGNORE, E}}}, \ |
758 |
|
{CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \ |
759 |
|
{CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}} |
760 |
|
|
761 |
|
#define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \ |
762 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, OP1, OP2, IGNORE, RD8, E}}}, \ |
763 |
|
EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \ |
764 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS8SRC, RD8, E}}, {{0x7, 0xe, ABS8LIST, OP1, OP2, IGNORE, RD8, E}}}, \ |
765 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8, E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \ |
766 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8, E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}} |
767 |
|
|
768 |
|
#define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \ |
769 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ |
770 |
|
EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \ |
771 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ |
772 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} |
773 |
|
|
774 |
|
#define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \ |
775 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6A15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ |
776 |
|
EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \ |
777 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ |
778 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} |
779 |
|
|
780 |
|
#define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \ |
781 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6A35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ |
782 |
|
EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \ |
783 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ |
784 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} |
785 |
|
|
786 |
|
#define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \ |
787 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND, E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \ |
788 |
|
EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \ |
789 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \ |
790 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}} |
791 |
|
|
792 |
|
#define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \ |
793 |
|
{CODE, AV_H8, 2, NAME, {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, OP1, OP2, RS16, IGNORE, E}}}, \ |
794 |
|
EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \ |
795 |
|
{CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \ |
796 |
|
{CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}} |
797 |
|
|
798 |
|
#define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \ |
799 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, IGNORE, OP1, OP2, IGNORE, RD16, E}}}, \ |
800 |
|
EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \ |
801 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \ |
802 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}} |
803 |
|
|
804 |
|
#define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \ |
805 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ |
806 |
|
EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \ |
807 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ |
808 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} |
809 |
|
|
810 |
|
#define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \ |
811 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6B15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ |
812 |
|
EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \ |
813 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ |
814 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} |
815 |
|
|
816 |
|
#define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \ |
817 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6B35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ |
818 |
|
EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \ |
819 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ |
820 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} |
821 |
|
|
822 |
|
#define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \ |
823 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \ |
824 |
|
EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \ |
825 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \ |
826 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}} |
827 |
|
|
828 |
|
#define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \ |
829 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \ |
830 |
|
EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \ |
831 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \ |
832 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}} |
833 |
|
|
834 |
|
#define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \ |
835 |
|
{CODE, AV_H8SX, 0, NAME, {{RS32, RDIND, E}}, {{PREFIX_0109, TO_IND, OPCODE, B30 | RS32, E}}}, \ |
836 |
|
EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \ |
837 |
|
{CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \ |
838 |
|
{CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}} |
839 |
|
|
840 |
|
#define EXPAND_TO_REG32(CODE, NAME, OPCODE) \ |
841 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, RD32, E}}, {{PREFIX_010A, FROM_IND, OPCODE, B30 | RD32, E}}}, \ |
842 |
|
EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \ |
843 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \ |
844 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}} |
845 |
|
|
846 |
|
|
847 |
|
#define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \ |
848 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
849 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174, 0x6, 0xc, B30 | RDPOSTINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
850 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
851 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC, E}}, {{PREFIX_0175, 0x6, 0xc, B30 | RDPREINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
852 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC, E}}, {{PREFIX_0177, 0x6, 0xc, B30 | RDPREDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
853 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST, E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
854 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
855 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
856 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
857 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
858 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
859 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
860 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
861 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
862 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
863 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | B20 | IGNORE, DSTABS16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
864 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | B20 | IGNORE, DSTABS32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ |
865 |
|
{CODE, AV_H8, 2, NAME, {{RS8, RD8, E}}, {{OP2, OP3, RS8, RD8, E}}}, \ |
866 |
|
EXPAND_FROM_REG8 (CODE, NAME, OP2, OP3, OP4), \ |
867 |
|
EXPAND_TO_REG8 (CODE, NAME, OP2, OP3, OP4), \ |
868 |
|
EXPAND_FROM_IND8 (CODE, NAME, OP4), \ |
869 |
|
EXPAND_STD_MATRIX_B (CODE, NAME, OP4), \ |
870 |
|
EXPAND_FROM_ABS16_B (CODE, NAME, OP4), \ |
871 |
|
EXPAND_FROM_ABS32_B (CODE, NAME, OP4) |
872 |
|
|
873 |
|
#define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \ |
874 |
|
{CODE, AV_H8H, 6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \ |
875 |
|
EXPAND_FROM_IMM16_W (CODE, NAME, OP3), \ |
876 |
|
EXPAND_FROM_REG16 (CODE, NAME, OP1, OP2, OP3), \ |
877 |
|
EXPAND_TO_REG16 (CODE, NAME, OP1, OP2, OP3), \ |
878 |
|
EXPAND_FROM_IND16 (CODE, NAME, OP3), \ |
879 |
|
EXPAND_STD_MATRIX_W (CODE, NAME, OP3), \ |
880 |
|
EXPAND_FROM_ABS16_W (CODE, NAME, OP3), \ |
881 |
|
EXPAND_FROM_ABS32_W (CODE, NAME, OP3) |
882 |
|
|
883 |
|
#define EXPAND_TWOOP_L(CODE, NAME, OP1) \ |
884 |
|
{CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \ |
885 |
|
{CODE, AV_H8H, 6, NAME, {{IMM32, RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST, E}}}, \ |
886 |
|
EXPAND_FROM_IMM16_L (CODE, NAME, OP1), \ |
887 |
|
EXPAND_FROM_IMM32_L (CODE, NAME, OP1), \ |
888 |
|
EXPAND_FROM_REG32 (CODE, NAME, OP1), \ |
889 |
|
EXPAND_TO_REG32 (CODE, NAME, OP1), \ |
890 |
|
EXPAND_STD_MATRIX_L (CODE, NAME, OP1) |
891 |
|
|
892 |
|
|
893 |
|
/* Old expanders: */ |
894 |
|
|
895 |
|
#define BITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ |
896 |
|
{code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \ |
897 |
|
{code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \ |
898 |
|
{code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \ |
899 |
|
{code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \ |
900 |
|
{code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}} |
901 |
|
|
902 |
|
#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ |
903 |
|
{code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \ |
904 |
|
{code, AV_H8SX, 0, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, op4, E}}}, \ |
905 |
|
{code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \ |
906 |
|
{code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}} |
907 |
|
|
908 |
|
#define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ |
909 |
|
BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ |
910 |
|
BITOP(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) |
911 |
|
|
912 |
|
#define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ |
913 |
|
BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ |
914 |
|
BITOP_B(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) |
915 |
|
|
916 |
|
#define WTWOP(code, name, op1, op2) \ |
917 |
|
{code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}} |
918 |
|
|
919 |
#define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\ |
#define BRANCH(code, name, op) \ |
920 |
BITOP(code,imm, name, op00+1, op01, op10,op11, op20,op21,op30),\ |
{code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \ |
921 |
BITOP(code,RS8, name, op00, op01, op10,op11, op20,op21,op30) |
{code, AV_H8, 4, name, {{PCREL8, E}}, {{0x4, op, PCREL8, DATA | B00, E}}} |
922 |
|
|
|
#define WTWOP(code,name, op1, op2) \ |
|
|
{ code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}, 0, 0, 0, 0} |
|
923 |
|
|
924 |
#define BRANCH(code, name, op) \ |
#define UNOP(code, name, op1, op2) \ |
925 |
{ code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ |
{code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}} |
926 |
{ code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}, 0, 0, 0, 0} |
|
927 |
|
#define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \ |
928 |
|
{CODE, AV_H8, 2, NAME, {{OR8, E}}, {{ OP1, OP2, OP3, OR8, E}}}, \ |
929 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B30 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
930 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
931 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
932 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
933 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
934 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
935 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
936 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
937 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
938 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
939 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
940 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
941 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
942 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
943 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS8SRC, E}}, {{ 7, 15, ABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
944 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 10, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
945 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 10, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} |
946 |
|
|
947 |
|
#define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \ |
948 |
|
{CODE, AV_H8H, 2, NAME, {{OR16, E}}, {{ OP1, OP2, OP3, OR16, E}}}, \ |
949 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B31 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
950 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
951 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
952 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
953 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
954 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
955 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
956 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
957 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
958 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
959 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
960 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
961 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
962 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
963 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 11, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
964 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 11, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} |
965 |
|
|
966 |
|
#define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \ |
967 |
|
{CODE, AV_H8H, 2, NAME, {{OR32, E}}, {{ OP1, OP2, OP3, B30 | OR32, E}}}, \ |
968 |
|
{CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{PREFIX, 4, 6, 9, B30 | RSIND, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
969 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
970 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
971 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
972 |
|
{CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
973 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
974 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
975 |
|
{CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
976 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
977 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
978 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
979 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B31 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
980 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B31 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
981 |
|
{CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B31 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
982 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ |
983 |
|
{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}} |
984 |
|
|
985 |
|
#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ |
986 |
|
{CODE, AV_H8, 2, NAME, {{CONST, RD8, E}}, {{ OP1, OP2, OP3, RD8, E}}}, \ |
987 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B30 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
988 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
989 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
990 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
991 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
992 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
993 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
994 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
995 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
996 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
997 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
998 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
999 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1000 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1001 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST, E}}, {{ 7, 15, DSTABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1002 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 10, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1003 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 10, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} |
1004 |
|
|
1005 |
|
#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ |
1006 |
|
{CODE, AV_H8, 2, NAME, {{CONST, RD16, E}}, {{ OP1, OP2, OP3, RD16, E}}}, \ |
1007 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B31 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
1008 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
1009 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
1010 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
1011 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
1012 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ |
1013 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1014 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1015 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1016 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1017 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1018 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1019 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1020 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1021 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 11, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ |
1022 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 11, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} |
1023 |
|
|
1024 |
|
#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \ |
1025 |
|
{CODE, AV_H8, 2, NAME, {{CONST, RD32, E}}, {{ OP1, OP2, OP3, BIT | RD32, E}}}, \ |
1026 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{PREFIX, 4, 6, 9, B30 | RDIND, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1027 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1028 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1029 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1030 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1031 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1032 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1033 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1034 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1035 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1036 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1037 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1038 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1039 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1040 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ |
1041 |
|
{CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}} |
1042 |
|
|
1043 |
|
#define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST |
1044 |
|
#define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC |
1045 |
|
|
1046 |
|
#define O(op, size) (op * 4 + size) |
1047 |
|
#define OP_SIZE(HOW) (HOW % 4) |
1048 |
|
#define OP_KIND(HOW) (HOW / 4) |
1049 |
|
|
1050 |
#define SOP(code, x,name) \ |
enum h8_asm_codes |
1051 |
{code, 1, x, name |
{ |
1052 |
|
O_RECOMPILE = 0, |
1053 |
|
O_ADD, |
1054 |
|
O_ADDX, |
1055 |
|
O_AND, |
1056 |
|
O_BAND, |
1057 |
|
O_BRA, |
1058 |
|
O_BRAB, |
1059 |
|
O_BRAW, |
1060 |
|
O_BRAL, |
1061 |
|
O_BRAS, |
1062 |
|
O_BRABC, |
1063 |
|
O_BRABS, |
1064 |
|
O_BSRBC, |
1065 |
|
O_BSRBS, |
1066 |
|
O_BRN, |
1067 |
|
O_BHI, |
1068 |
|
O_BLS, |
1069 |
|
O_BCC, |
1070 |
|
O_BCS, |
1071 |
|
O_BNE, |
1072 |
|
O_BVC, |
1073 |
|
O_BVS, |
1074 |
|
O_BPL, |
1075 |
|
O_BMI, |
1076 |
|
O_BGE, |
1077 |
|
O_BLT, |
1078 |
|
O_BGT, |
1079 |
|
O_BLE, |
1080 |
|
O_ANDC, |
1081 |
|
O_BEQ, |
1082 |
|
O_BCLR, |
1083 |
|
O_BCLREQ, |
1084 |
|
O_BCLRNE, |
1085 |
|
O_BSETEQ, |
1086 |
|
O_BSETNE, |
1087 |
|
O_BFLD, |
1088 |
|
O_BFST, |
1089 |
|
O_BIAND, |
1090 |
|
O_BILD, |
1091 |
|
O_BIOR, |
1092 |
|
O_BIXOR, |
1093 |
|
O_BIST, |
1094 |
|
O_BISTZ, |
1095 |
|
O_BLD, |
1096 |
|
O_BNOT, |
1097 |
|
O_BOR, |
1098 |
|
O_BSET, |
1099 |
|
O_BSR, |
1100 |
|
O_BXOR, |
1101 |
|
O_CMP, |
1102 |
|
O_DAA, |
1103 |
|
O_DAS, |
1104 |
|
O_DEC, |
1105 |
|
O_DIVU, |
1106 |
|
O_DIVS, |
1107 |
|
O_DIVXU, |
1108 |
|
O_DIVXS, |
1109 |
|
O_INC, |
1110 |
|
O_LDC, |
1111 |
|
O_MOV, |
1112 |
|
O_MOVAB, |
1113 |
|
O_MOVAW, |
1114 |
|
O_MOVAL, |
1115 |
|
O_MOVMD, |
1116 |
|
O_MOVSD, |
1117 |
|
O_OR, |
1118 |
|
O_ROTL, |
1119 |
|
O_ROTR, |
1120 |
|
O_ROTXL, |
1121 |
|
O_ROTXR, |
1122 |
|
O_BPT, |
1123 |
|
O_SHAL, |
1124 |
|
O_SHAR, |
1125 |
|
O_SHLL, |
1126 |
|
O_SHLR, |
1127 |
|
O_SUB, |
1128 |
|
O_SUBS, |
1129 |
|
O_TRAPA, |
1130 |
|
O_XOR, |
1131 |
|
O_XORC, |
1132 |
|
O_BST, |
1133 |
|
O_BSTZ, |
1134 |
|
O_BTST, |
1135 |
|
O_EEPMOV, |
1136 |
|
O_EXTS, |
1137 |
|
O_EXTU, |
1138 |
|
O_JMP, |
1139 |
|
O_JSR, |
1140 |
|
O_MULU, |
1141 |
|
O_MULUU, |
1142 |
|
O_MULS, |
1143 |
|
O_MULSU, |
1144 |
|
O_MULXU, |
1145 |
|
O_MULXS, |
1146 |
|
O_NOP, |
1147 |
|
O_NOT, |
1148 |
|
O_ORC, |
1149 |
|
O_RTE, |
1150 |
|
O_RTEL, |
1151 |
|
O_STC, |
1152 |
|
O_SUBX, |
1153 |
|
O_NEG, |
1154 |
|
O_RTS, |
1155 |
|
O_RTSL, |
1156 |
|
O_SLEEP, |
1157 |
|
O_ILL, |
1158 |
|
O_ADDS, |
1159 |
|
O_SYSCALL, |
1160 |
|
O_TAS, |
1161 |
|
O_CLRMAC, |
1162 |
|
O_LDMAC, |
1163 |
|
O_MAC, |
1164 |
|
O_LDM, |
1165 |
|
O_STM, |
1166 |
|
O_STMAC, |
1167 |
|
O_LAST, |
1168 |
|
/* Change made for System Call processing. */ |
1169 |
|
O_SYS_CREAT, |
1170 |
|
O_SYS_OPEN, |
1171 |
|
O_SYS_READ, |
1172 |
|
O_SYS_WRITE, |
1173 |
|
O_SYS_LSEEK, |
1174 |
|
O_SYS_CLOSE, |
1175 |
|
O_SYS_STAT, |
1176 |
|
O_SYS_FSTAT, |
1177 |
|
/* Space reserved for future file I/O system calls. */ |
1178 |
|
O_SYS_CMDLINE |
1179 |
|
/* End of System Call specific Changes. */ |
1180 |
|
}; |
1181 |
|
|
1182 |
#define NEW_SOP(code, in,x,name) \ |
enum h8_size |
1183 |
{code, in, x, name |
{ |
1184 |
#define EOP ,0,0,0,0 } |
SB = 0, |
1185 |
|
SW = 1, |
1186 |
#define TWOOP(code, name, op1, op2,op3) \ |
SL = 2, |
1187 |
{ code,1, 2,name, {{IMM8, RD8, E}}, {{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\ |
SN = 3 |
1188 |
{ code, 1, 2,name, {{RS8, RD8, E}}, {{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0} |
}; |
|
|
|
|
#define UNOP(code,name, op1, op2) \ |
|
|
{ code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}, 0, 0, 0, 0} |
|
|
|
|
|
#define UNOP3(code, name, op1, op2, op3) \ |
|
|
{ O(code,SB), 1, 2, name, {{OR8, E, 0}}, {{op1, op2, op3+0, OR8, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ |
|
|
{ O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ |
|
|
{ O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}, 0, 0, 0, 0} \ |
|
|
,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST, E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ |
|
|
{ O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ |
|
|
{ O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}, 0, 0, 0, 0} |
|
|
|
|
|
|
|
|
#define IMM32LIST IMM32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE |
|
|
#define IMM24LIST IMM24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE |
|
|
#define IMM16LIST IMM16,IGNORE,IGNORE,IGNORE |
|
|
#define A16LIST L_16,IGNORE,IGNORE,IGNORE |
|
|
#define DISP24LIST DISP|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE |
|
|
#define DISP32LIST DISP|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE |
|
|
#define ABS24LIST ABS|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE |
|
|
#define ABS32LIST ABS|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE |
|
|
#define A24LIST L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE |
|
|
#define A32LIST L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE |
|
|
#define PREFIX32 0x0,0x1,0x0,0x0 |
|
|
#define PREFIXLDC 0x0,0x1,0x4,0x0 |
|
|
|
|
|
|
|
|
#define O(op, size) (op*4+size) |
|
|
|
|
|
#define O_RECOMPILE 0 |
|
|
#define O_ADD 1 |
|
|
#define O_ADDX 2 |
|
|
#define O_AND 3 |
|
|
#define O_BAND 4 |
|
|
#define O_BRA 5 |
|
|
#define O_BRN 6 |
|
|
#define O_BHI 7 |
|
|
#define O_BLS 8 |
|
|
#define O_BCC 9 |
|
|
#define O_BCS 10 |
|
|
#define O_BNE 11 |
|
|
#define O_BVC 12 |
|
|
#define O_BVS 13 |
|
|
#define O_BPL 14 |
|
|
#define O_BMI 15 |
|
|
#define O_BGE 16 |
|
|
#define O_BLT 17 |
|
|
#define O_BGT 18 |
|
|
#define O_BLE 19 |
|
|
#define O_ANDC 20 |
|
|
#define O_BEQ 21 |
|
|
#define O_BCLR 22 |
|
|
#define O_BIAND 23 |
|
|
#define O_BILD 24 |
|
|
#define O_BIOR 25 |
|
|
#define O_BIXOR 26 |
|
|
#define O_BIST 27 |
|
|
#define O_BLD 28 |
|
|
#define O_BNOT 29 |
|
|
#define O_BSET 30 |
|
|
#define O_BSR 31 |
|
|
#define O_BXOR 32 |
|
|
#define O_CMP 33 |
|
|
#define O_DAA 34 |
|
|
#define O_DAS 35 |
|
|
#define O_DEC 36 |
|
|
#define O_DIVU 37 |
|
|
#define O_DIVS 38 |
|
|
#define O_INC 39 |
|
|
#define O_LDC 40 |
|
|
#define O_MOV_TO_MEM 41 |
|
|
#define O_OR 42 |
|
|
#define O_ROTL 43 |
|
|
#define O_ROTR 44 |
|
|
#define O_ROTXL 45 |
|
|
#define O_ROTXR 46 |
|
|
#define O_BPT 47 |
|
|
#define O_SHAL 48 |
|
|
#define O_SHAR 49 |
|
|
#define O_SHLL 50 |
|
|
#define O_SHLR 51 |
|
|
#define O_SUB 52 |
|
|
#define O_SUBS 53 |
|
|
#define O_TRAPA 54 |
|
|
#define O_XOR 55 |
|
|
#define O_XORC 56 |
|
|
#define O_BOR 57 |
|
|
#define O_BST 58 |
|
|
#define O_BTST 59 |
|
|
#define O_EEPMOV 60 |
|
|
#define O_EXTS 61 |
|
|
#define O_EXTU 62 |
|
|
#define O_JMP 63 |
|
|
#define O_JSR 64 |
|
|
#define O_MULU 65 |
|
|
#define O_MULS 66 |
|
|
#define O_NOP 67 |
|
|
#define O_NOT 68 |
|
|
#define O_ORC 69 |
|
|
#define O_RTE 70 |
|
|
#define O_STC 71 |
|
|
#define O_SUBX 72 |
|
|
#define O_NEG 73 |
|
|
#define O_RTS 74 |
|
|
#define O_SLEEP 75 |
|
|
#define O_ILL 76 |
|
|
#define O_ADDS 77 |
|
|
#define O_SYSCALL 78 |
|
|
#define O_MOV_TO_REG 79 |
|
|
#define O_TAS 80 |
|
|
#define O_CLRMAC 82 |
|
|
#define O_LDMAC 83 |
|
|
#define O_MAC 84 |
|
|
#define O_LDM 85 |
|
|
#define O_STM 86 |
|
|
#define O_STMAC 87 |
|
|
#define O_LAST 88 |
|
|
#define SB 0 |
|
|
#define SW 1 |
|
|
#define SL 2 |
|
|
#define SN 3 |
|
1189 |
|
|
1190 |
|
|
1191 |
/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences. |
/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences. |
1193 |
|
|
1194 |
struct h8_opcode h8_opcodes[] = |
struct h8_opcode h8_opcodes[] = |
1195 |
{ |
{ |
1196 |
TWOOP(O(O_ADD,SB),"add.b", 0x8, 0x0,0x8), |
{O (O_ADD, SB), AV_H8, 2, "add.b", {{IMM8, RD8, E}}, {{0x8, RD8, IMM8LIST, E}}}, |
1197 |
|
EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0), |
|
NEW_SOP(O(O_ADD,SW),1,2,"add.w"),{{RS16,RD16,E}},{{0x0,0x9,RS16,RD16,E}} EOP, |
|
|
NEW_SOP(O(O_ADD,SW),0,4,"add.w"),{{IMM16,RD16,E}},{{0x7,0x9,0x1,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, |
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NEW_SOP(O(O_ADD,SL),0,2,"add.l"),{{RS32,RD32,E }}, {{0x0,0xA,B31|RS32,B30|RD32,E}} EOP, |
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NEW_SOP(O(O_ADD,SL),0,6,"add.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x1,B30|RD32,IMM32LIST,E}} EOP, |
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NEW_SOP(O(O_ADDS,SL),1,2,"adds"), {{KBIT,RDP,E}}, {{0x0,0xB,KBIT,RDP,E,0,0,0,0}} EOP, |
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TWOOP(O(O_ADDX,SB),"addx",0x9,0x0,0xE), |
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TWOOP(O(O_AND,SB), "and.b",0xE,0x1,0x6), |
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NEW_SOP(O(O_AND,SW),0,2,"and.w"),{{RS16,RD16,E }},{{0x6,0x6,RS16,RD16,E}} EOP, |
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NEW_SOP(O(O_AND,SW),0,4,"and.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x6,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, |
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NEW_SOP(O(O_AND,SL),0,6,"and.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x6,B30|RD32,IMM32LIST,E}} EOP, |
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NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E}} EOP, |
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NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR|DST,E}},{{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP, |
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NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP, |
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BITOP(O(O_BAND,SB), IMM3|B30,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0), |
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BRANCH(O(O_BRA,SB),"bra",0x0), |
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BRANCH(O(O_BRA,SB),"bt",0x0), |
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BRANCH(O(O_BRN,SB),"brn",0x1), |
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BRANCH(O(O_BRN,SB),"bf",0x1), |
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BRANCH(O(O_BHI,SB),"bhi",0x2), |
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BRANCH(O(O_BLS,SB),"bls",0x3), |
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BRANCH(O(O_BCC,SB),"bcc",0x4), |
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BRANCH(O(O_BCC,SB),"bhs",0x4), |
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BRANCH(O(O_BCS,SB),"bcs",0x5), |
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BRANCH(O(O_BCS,SB),"blo",0x5), |
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BRANCH(O(O_BNE,SB),"bne",0x6), |
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BRANCH(O(O_BEQ,SB),"beq",0x7), |
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BRANCH(O(O_BVC,SB),"bvc",0x8), |
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BRANCH(O(O_BVS,SB),"bvs",0x9), |
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BRANCH(O(O_BPL,SB),"bpl",0xA), |
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BRANCH(O(O_BMI,SB),"bmi",0xB), |
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BRANCH(O(O_BGE,SB),"bge",0xC), |
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BRANCH(O(O_BLT,SB),"blt",0xD), |
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BRANCH(O(O_BGT,SB),"bgt",0xE), |
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BRANCH(O(O_BLE,SB),"ble",0xF), |
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EBITOP(O(O_BCLR,SB),IMM3|B30,"bclr", 0x6,0x2,0x7,0xD,0x7,0xF,0x8), |
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BITOP(O(O_BIAND,SB),IMM3|B31,"biand",0x7,0x6,0x7,0xC,0x7,0xE,0x0), |
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BITOP(O(O_BILD,SB), IMM3|B31,"bild", 0x7,0x7,0x7,0xC,0x7,0xE,0x0), |
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BITOP(O(O_BIOR,SB), IMM3|B31,"bior", 0x7,0x4,0x7,0xC,0x7,0xE,0x0), |
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BITOP(O(O_BIST,SB), IMM3|B31,"bist", 0x6,0x7,0x7,0xD,0x7,0xF,0x8), |
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BITOP(O(O_BIXOR,SB),IMM3|B31,"bixor",0x7,0x5,0x7,0xC,0x7,0xE,0x0), |
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BITOP(O(O_BLD,SB), IMM3|B30,"bld", 0x7,0x7,0x7,0xC,0x7,0xE,0x0), |
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EBITOP(O(O_BNOT,SB),IMM3|B30,"bnot", 0x6,0x1,0x7,0xD,0x7,0xF,0x8), |
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BITOP(O(O_BOR,SB), IMM3|B30,"bor", 0x7,0x4,0x7,0xC,0x7,0xE,0x0), |
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EBITOP(O(O_BSET,SB),IMM3|B30,"bset", 0x6,0x0,0x7,0xD,0x7,0xF,0x8), |
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SOP(O(O_BSR,SB),6,"bsr"),{{DISP8,E,0}},{{ 0x5,0x5,DISP8,IGNORE,E,0,0,0,0}} EOP, |
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SOP(O(O_BSR,SB),6,"bsr"),{{DISP16,E,0}},{{ 0x5,0xC,0x0,0x0,DISP16,IGNORE,IGNORE,IGNORE,E,0,0,0,0}} EOP, |
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BITOP(O(O_BST,SB), IMM3|B30,"bst",0x6,0x7,0x7,0xD,0x7,0xF,0x8), |
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EBITOP(O(O_BTST,SB), IMM3|B30,"btst",0x6,0x3,0x7,0xC,0x7,0xE,0x0), |
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BITOP(O(O_BXOR,SB), IMM3|B30,"bxor",0x7,0x5,0x7,0xC,0x7,0xE,0x0), |
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TWOOP(O(O_CMP,SB), "cmp.b",0xA,0x1,0xC), |
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WTWOP(O(O_CMP,SW), "cmp.w",0x1,0xD), |
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NEW_SOP(O(O_CMP,SW),1,2,"cmp.w"),{{RS16,RD16,E }},{{0x1,0xD,RS16,RD16,E}} EOP, |
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NEW_SOP(O(O_CMP,SW),0,4,"cmp.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x2,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, |
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NEW_SOP(O(O_CMP,SL),0,6,"cmp.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x2,B30|RD32,IMM32LIST,E}} EOP, |
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NEW_SOP(O(O_CMP,SL),0,2,"cmp.l") ,{{RS32,RD32,E }},{{0x1,0xF,B31|RS32,B30|RD32,E}} EOP, |
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UNOP(O(O_DAA,SB), "daa",0x0,0xF), |
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UNOP(O(O_DAS,SB), "das",0x1,0xF), |
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UNOP(O(O_DEC,SB), "dec.b",0x1,0xA), |
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NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{{DBIT,RD16,E }},{{0x1,0xB,0x5|DBIT,RD16,E}} EOP, |
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NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{{DBIT,RD32,E }},{{0x1,0xB,0x7|DBIT,RD32|B30,E}} EOP, |
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NEW_SOP(O(O_DIVU,SB),1,13,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP, |
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NEW_SOP(O(O_DIVU,SW),0,21,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP, |
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NEW_SOP(O(O_DIVS,SB),0,13,"divxs.b") ,{{RS8,RD16,E }},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP, |
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NEW_SOP(O(O_DIVS,SW),0,21,"divxs.w") ,{{RS16,RD32,E }},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP, |
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NEW_SOP(O(O_EEPMOV,SB),1,4,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}}EOP, |
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NEW_SOP(O(O_EEPMOV,SW),0,4,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E}} EOP, |
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NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{{OR16,E,0}},{{0x1,0x7,0xD,OR16,E }}EOP, |
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NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{{OR32,E,0}},{{0x1,0x7,0xF,OR32|B30,E }}EOP, |
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NEW_SOP(O(O_EXTU,SW),0,2,"extu.w"),{{OR16,E,0}},{{0x1,0x7,0x5,OR16,E }}EOP, |
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NEW_SOP(O(O_EXTU,SL),0,2,"extu.l"),{{OR32,E,0}},{{0x1,0x7,0x7,OR32|B30,E }}EOP, |
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UNOP(O(O_INC,SB), "inc",0x0,0xA), |
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NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{{DBIT,RD16,E }},{{0x0,0xB,0x5|DBIT,RD16,E}} EOP, |
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NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{{DBIT,RD32,E }},{{0x0,0xB,0x7|DBIT,RD32|B30,E}} EOP, |
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SOP(O(O_JMP,SB),4,"jmp"),{{RSIND,E,0}},{{0x5,0x9,B30|RSIND,0x0,E,0,0,0,0}}EOP, |
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|
SOP(O(O_JMP,SB),6,"jmp"),{{SRC|ABSJMP,E,0}},{{0x5,0xA,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP, |
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SOP(O(O_JMP,SB),8,"jmp"),{{SRC|MEMIND,E,0}},{{0x5,0xB,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP, |
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SOP(O(O_JSR,SB),6,"jsr"),{{SRC|RSIND,E,0}}, {{0x5,0xD,B30|RSIND,0x0,E,0,0,0,0}}EOP, |
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SOP(O(O_JSR,SB),8,"jsr"),{{SRC|ABSJMP,E,0}},{{0x5,0xE,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP, |
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SOP(O(O_JSR,SB),8,"jsr"),{{SRC|MEMIND,E,0}},{{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP, |
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NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR|DST,E}}, {{ 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR|DST,E}}, {{ 0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR|DST,E}}, {{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR|DST,E}}, {{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP, |
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NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR|DST,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR|DST,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP, |
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NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR|DST,E}}, {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR|DST,E}}, {{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP, |
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|
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NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR|DST,E}}, {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP, |
|
|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP, |
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|
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP, |
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|
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|
SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS|SRC|L_16|MEMRELAX,RD8,E}}, {{ 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{ABS|SRC|L_32|MEMRELAX,RD8,E }}, {{ 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS|L_16|MEMRELAX|DST,E}}, {{ 0x6,0xA,0x8,RS8,DST|ABS|MEMRELAX|A16LIST,E}}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,ABS|DST|L_32|MEMRELAX,E }}, {{ 0x6,0xA,0xA,RS8,DST|ABS|MEMRELAX|A32LIST,E }}EOP, |
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|
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|
SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP|L_32|SRC,RD8,E}}, {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0x2,RD8,SRC|DISP32LIST,E}}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP|L_32|DST,E}}, {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0xA,RS8,DST|DISP32LIST,E}}EOP, |
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SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{RS8,RD8,E}}, {{ 0x0,0xC,RS8,RD8,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{IMM8,RD8,E}}, {{ 0xF,RD8,IMM8,IGNORE,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{RSIND,RD8,E}}, {{ 0x6,0x8,B30|RSIND,RD8,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP16SRC,RD8,E}}, {{ 0x6,0xE,B30|DISPREG,RD8,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{RSINC,RD8,E}}, {{ 0x6,0xC,B30|RSINC,RD8,E,0,0,0,0}}EOP, |
|
|
|
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|
SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS8SRC,RD8,E}}, {{ 0x2,RD8,ABS8SRC,IGNORE,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,RDIND,E}}, {{ 0x6,0x8,RDIND|B31,RS8,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP16DST,E}}, {{ 0x6,0xE,DISPREG|B31,RS8,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,RDDEC|B31,E}}, {{ 0x6,0xC,RDDEC|B31,RS8,E,0,0,0,0}}EOP, |
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|
|
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|
SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS8DST,E}}, {{ 0x3,RS8,ABS8DST,IGNORE,E,0,0,0,0}}EOP, |
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|
|
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|
SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDIND,E}}, {{ 0x6,0x9,RDIND|B31,RS16,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP|L_32|SRC,RD16,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,RD16,SRC|DISP32LIST,E}}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP|L_32|DST,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0xA,RS16,DST|DISP32LIST,E}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS|L_32|MEMRELAX|SRC,RD16,E }},{{ 0x6,0xB,0x2,RD16,SRC|MEMRELAX|ABS32LIST,E }}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS|L_32|MEMRELAX|DST,E }},{{ 0x6,0xB,0xA,RS16,DST|MEMRELAX|ABS32LIST,E }}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SW),2,"mov.w"),{{RS16,RD16,E}}, {{ 0x0,0xD,RS16, RD16,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{IMM16,RD16,E}}, {{ 0x7,0x9,0x0,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{RSIND,RD16,E}}, {{ 0x6,0x9,B30|RSIND,RD16,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP16SRC,RD16,E}}, {{ 0x6,0xF,B30|DISPREG,RD16,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{RSINC,RD16,E}}, {{ 0x6,0xD,B30|RSINC,RD16,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS16SRC,RD16,E}}, {{ 0x6,0xB,0x0,RD16,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
|
|
|
SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP16DST,E}}, {{ 0x6,0xF,DISPREG|B31,RS16,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDDEC,E}}, {{ 0x6,0xD,RDDEC|B31,RS16,E,0,0,0,0}}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS16DST,E}}, {{ 0x6,0xB,0x8,RS16,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
|
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|
SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{IMM32,RD32,E}}, {{ 0x7,0xA,0x0,B30|RD32,IMM32LIST,E}}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SL),2,"mov.l"),{{RS32,RD32,E}}, {{ 0x0,0xF,B31|RS32,B30|RD32,E,0,0,0,0}}EOP, |
|
|
|
|
|
SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{RSIND,RD32,E}}, {{ PREFIX32,0x6,0x9,RSIND|B30,B30|RD32,E,0,0,0,0 }}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP16SRC,RD32,E}}, {{ PREFIX32,0x6,0xF,DISPREG|B30,B30|RD32,DISP16SRC,IGNORE,IGNORE,IGNORE,E }}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP|L_32|SRC,RD32,E}},{{ PREFIX32,0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,B30|RD32,SRC|DISP32LIST,E }}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{RSINC,RD32,E}}, {{ PREFIX32,0x6,0xD,B30|RSINC,B30|RD32,E,0,0,0,0 }}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS16SRC,RD32,E}}, {{ PREFIX32,0x6,0xB,0x0,B30|RD32,ABS16SRC,IGNORE,IGNORE,IGNORE,E }}EOP, |
|
|
SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS32SRC|MEMRELAX,RD32,E }}, {{ PREFIX32,0x6,0xB,0x2,B30|RD32,SRC|MEMRELAX|ABS32LIST,E }}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDIND,E}}, {{ PREFIX32,0x6,0x9,RDIND|B31,B30|RS32,E,0,0,0,0 }}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP16DST,E}}, {{ PREFIX32,0x6,0xF,DISPREG|B31,B30|RS32,DISP16DST,IGNORE,IGNORE,IGNORE,E }}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP|L_32|DST,E}},{{ PREFIX32,0x7,0x8,B31|DISPREG,0x0,0x6,0xB,0xA,B30|RS32,DST|DISP32LIST,E }}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDDEC,E}}, {{ PREFIX32,0x6,0xD,RDDEC|B31,B30|RS32,E,0,0,0,0 }}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS16DST,E}}, {{ PREFIX32,0x6,0xB,0x8,B30|RS32,ABS16DST,IGNORE,IGNORE,IGNORE,E }}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS32DST|MEMRELAX,E }}, {{ PREFIX32,0x6,0xB,0xA,B30|RS32,DST|MEMRELAX|ABS32LIST,E }}EOP, |
|
|
|
|
|
SOP(O(O_MOV_TO_REG,SB),10,"movfpe"),{{ABS16SRC,RD8,E}},{{ 0x6,0xA,0x4,RD8,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
SOP(O(O_MOV_TO_MEM,SB),10,"movtpe"),{{RS8,ABS16DST,E}},{{ 0x6,0xA,0xC,RS8,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
|
|
|
|
NEW_SOP(O(O_MULU,SB),1,14,"mulxu.b"),{{RS8,RD16,E}}, {{ 0x5,0x0,RS8,RD16,E,0,0,0,0}}EOP, |
|
|
NEW_SOP(O(O_MULU,SW),0,14,"mulxu.w"),{{RS16,RD32,E}},{{ 0x5,0x2,RS16,B30|RD32,E,0,0,0,0}}EOP, |
|
1198 |
|
|
1199 |
NEW_SOP(O(O_MULS,SB),0,20,"mulxs.b"),{{RS8,RD16,E}}, {{ 0x0,0x1,0xc,0x0,0x5,0x0,RS8,RD16,E}}EOP, |
{O (O_ADD, SW), AV_H8, 6, "add.w", {{RS16, RD16, E}}, {{0x0, 0x9, RS16, RD16, E}}}, |
1200 |
NEW_SOP(O(O_MULS,SW),0,20,"mulxs.w"),{{RS16,RD32,E}},{{ 0x0,0x1,0xc,0x0,0x5,0x2,RS16,B30|RD32,E}}EOP, |
{O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16, E}}}, |
1201 |
|
{O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, |
1202 |
|
{O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, |
1203 |
|
{O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, |
1204 |
|
EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1), |
1205 |
|
|
1206 |
|
{O (O_ADD, SL), AV_H8H, 6, "add.l", {{RS32, RD32, E}}, {{0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, |
1207 |
|
{O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, |
1208 |
|
EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1), |
1209 |
|
|
1210 |
|
{O (O_ADDS, SL), AV_H8, 2, "adds", {{KBIT, RDP, E}}, {{0x0, 0xB,KBIT, RDP, E}}}, |
1211 |
|
|
1212 |
|
{O (O_ADDX, SB), AV_H8, 2, "addx", {{IMM8, RD8, E}}, {{0x9, RD8, IMM8LIST, E}}}, |
1213 |
|
{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, |
1214 |
|
{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, |
1215 |
|
{O (O_ADDX, SB), AV_H8, 2, "addx", {{RS8, RD8, E}}, {{0x0, 0xe, RS8, RD8, E}}}, |
1216 |
|
{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, |
1217 |
|
{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, |
1218 |
|
{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, |
1219 |
|
{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, |
1220 |
|
{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, |
1221 |
|
{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, |
1222 |
|
|
1223 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x1, RD16, IMM16LIST, E}}}, |
1224 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, |
1225 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, |
1226 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x0, 0x9, RS16, RD16, E}}}, |
1227 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, |
1228 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, |
1229 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, |
1230 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, |
1231 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, |
1232 |
|
{O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, |
1233 |
|
|
1234 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x1, RD32, IMM32LIST, E}}}, |
1235 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, |
1236 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, |
1237 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, |
1238 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, |
1239 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, |
1240 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, |
1241 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, |
1242 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, |
1243 |
|
{O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, |
1244 |
|
|
1245 |
|
{O (O_AND, SB), AV_H8, 2, "and.b", {{IMM8, RD8, E}}, {{0xe, RD8, IMM8LIST, E}}}, |
1246 |
|
EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0), |
1247 |
|
|
1248 |
|
{O (O_AND, SW), AV_H8, 2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16, E}}}, |
1249 |
|
EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6), |
1250 |
|
|
1251 |
|
{O (O_AND, SL), AV_H8H, 2, "and.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}}, |
1252 |
|
EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6), |
1253 |
|
|
1254 |
|
{O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}}, |
1255 |
|
{O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}}, |
1256 |
|
|
1257 |
|
BRANCH (O (O_BRA, SB), "bra", 0x0), |
1258 |
|
|
1259 |
|
{O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8, E}}, {{0x5, 0x9, LOWREG | L_8 | B30, 0x5, E}}}, |
1260 |
|
{O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}}, |
1261 |
|
{O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}}, |
1262 |
|
|
1263 |
|
{O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, |
1264 |
|
{O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, |
1265 |
|
{O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, |
1266 |
|
{O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, |
1267 |
|
{O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, |
1268 |
|
{O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, |
1269 |
|
{O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, |
1270 |
|
{O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, |
1271 |
|
{O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1272 |
|
{O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1273 |
|
{O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1274 |
|
{O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1275 |
|
{O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1276 |
|
{O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1277 |
|
{O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1278 |
|
{O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1279 |
|
|
1280 |
/* ??? This can use UNOP3. */ |
{O (O_BRAS, SB), AV_H8SX, 0, "bra/s", {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}}, |
|
NEW_SOP(O(O_NEG,SB),1,2,"neg.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x8,OR8,E,0,0,0,0}}EOP, |
|
|
NEW_SOP(O(O_NEG,SW),0,2,"neg.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x9,OR16,E}}EOP, |
|
|
NEW_SOP(O(O_NEG,SL),0,2,"neg.l"),{{ OR32,E,0}},{{ 0x1,0x7,0xB,B30|OR32,E}}EOP, |
|
|
|
|
|
NEW_SOP(O(O_NOP,SN),1,2,"nop"),{{E,0,0}},{{ 0x0,0x0,0x0,0x0,E,0,0,0,0}}EOP, |
|
1281 |
|
|
1282 |
/* ??? This can use UNOP3. */ |
{O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1283 |
NEW_SOP(O(O_NOT,SB),1,2,"not.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x0,OR8,E,0,0,0,0}}EOP, |
{O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1284 |
NEW_SOP(O(O_NOT,SW),0,2,"not.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x1,OR16,E}}EOP, |
{O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1285 |
NEW_SOP(O(O_NOT,SL),0,2,"not.l"),{{ OR32,E,0}},{{ 0x1,0x7,0x3,B30|OR32,E}}EOP, |
{O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1286 |
|
{O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1287 |
TWOOP(O(O_OR, SB),"or.b",0xC,0x1,0x4), |
{O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1288 |
NEW_SOP(O(O_OR,SW),0,4,"or.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x4,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, |
{O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1289 |
NEW_SOP(O(O_OR,SW),0,2,"or.w"),{{RS16,RD16,E }},{{0x6,0x4,RS16,RD16,E}} EOP, |
{O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, |
1290 |
|
|
1291 |
NEW_SOP(O(O_OR,SL),0,6,"or.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x4,B30|RD32,IMM32LIST,E}} EOP, |
BRANCH (O (O_BRA, SB), "bt", 0x0), |
1292 |
NEW_SOP(O(O_OR,SL),0,2,"or.l"),{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E}} EOP, |
BRANCH (O (O_BRN, SB), "brn", 0x1), |
1293 |
|
BRANCH (O (O_BRN, SB), "bf", 0x1), |
1294 |
NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP, |
BRANCH (O (O_BHI, SB), "bhi", 0x2), |
1295 |
NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP, |
BRANCH (O (O_BLS, SB), "bls", 0x3), |
1296 |
|
BRANCH (O (O_BCC, SB), "bcc", 0x4), |
1297 |
NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{{OR16,E,0}},{{ 0x6,0xD,0x7,OR16,E,0,0,0,0}}EOP, |
BRANCH (O (O_BCC, SB), "bhs", 0x4), |
1298 |
NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}}EOP, |
BRANCH (O (O_BCS, SB), "bcs", 0x5), |
1299 |
NEW_SOP(O(O_MOV_TO_MEM,SW),1,6,"push.w"),{{OR16,E,0}},{{ 0x6,0xD,0xF,OR16,E,0,0,0,0}}EOP, |
BRANCH (O (O_BCS, SB), "blo", 0x5), |
1300 |
NEW_SOP(O(O_MOV_TO_MEM,SL),0,6,"push.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0xF,OR32|B30,E,0,0,0,0}}EOP, |
BRANCH (O (O_BNE, SB), "bne", 0x6), |
1301 |
|
BRANCH (O (O_BEQ, SB), "beq", 0x7), |
1302 |
UNOP3(O_ROTL, "rotl", 0x1,0x2,0x8), |
BRANCH (O (O_BVC, SB), "bvc", 0x8), |
1303 |
UNOP3(O_ROTR, "rotr", 0x1,0x3,0x8), |
BRANCH (O (O_BVS, SB), "bvs", 0x9), |
1304 |
UNOP3(O_ROTXL, "rotxl",0x1,0x2,0x0), |
BRANCH (O (O_BPL, SB), "bpl", 0xA), |
1305 |
UNOP3(O_ROTXR, "rotxr",0x1,0x3,0x0), |
BRANCH (O (O_BMI, SB), "bmi", 0xB), |
1306 |
|
BRANCH (O (O_BGE, SB), "bge", 0xC), |
1307 |
SOP(O(O_BPT,SN), 10,"bpt"),{{E,0,0}},{{ 0x7,0xA,0xF,0xF,E,0,0,0,0}}EOP, |
BRANCH (O (O_BLT, SB), "blt", 0xD), |
1308 |
SOP(O(O_RTE,SN), 10,"rte"),{{E,0,0}},{{ 0x5,0x6,0x7,0x0,E,0,0,0,0}}EOP, |
BRANCH (O (O_BGT, SB), "bgt", 0xE), |
1309 |
SOP(O(O_RTS,SN), 8,"rts"),{{E,0,0}},{{ 0x5,0x4,0x7,0x0,E,0,0,0,0}}EOP, |
BRANCH (O (O_BLE, SB), "ble", 0xF), |
1310 |
|
|
1311 |
UNOP3(O_SHAL, "shal",0x1,0x0,0x8), |
EBITOP (O (O_BCLR, SB), IMM3 | B30, "bclr", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0), |
1312 |
UNOP3(O_SHAR, "shar",0x1,0x1,0x8), |
BITOP (O (O_BAND, SB), IMM3 | B30, "band", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), |
1313 |
UNOP3(O_SHLL, "shll",0x1,0x0,0x0), |
BITOP (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), |
1314 |
UNOP3(O_SHLR, "shlr",0x1,0x1,0x0), |
BITOP (O (O_BILD, SB), IMM3 | B31, "bild", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), |
1315 |
|
BITOP (O (O_BIOR, SB), IMM3 | B31, "bior", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), |
1316 |
SOP(O(O_SLEEP,SN),2,"sleep"),{{E,0,0}},{{ 0x0,0x1,0x8,0x0,E,0,0,0,0}} EOP, |
BITOP (O (O_BIST, SB), IMM3 | B31, "bist", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), |
1317 |
|
BITOP (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), |
1318 |
NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR|SRC,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP, |
BITOP (O (O_BLD, SB), IMM3 | B30, "bld", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), |
1319 |
|
EBITOP (O (O_BNOT, SB), IMM3 | B30, "bnot", 0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0), |
1320 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RSIND,E}}, {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP, |
BITOP (O (O_BOR, SB), IMM3 | B30, "bor", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), |
1321 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP, |
EBITOP (O (O_BSET, SB), IMM3 | B30, "bset", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0), |
1322 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP, |
BITOP (O (O_BST, SB), IMM3 | B30, "bst", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), |
1323 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDDEC,E}}, {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP, |
EBITOP (O (O_BTST, SB), IMM3 | B30, "btst", 0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0), |
1324 |
|
BITOP (O (O_BXOR, SB), IMM3 | B30, "bxor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), |
1325 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS16DST,E}}, {{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP, |
|
1326 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS32DST,E}}, {{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP, |
EBITOP_B (O (O_BCLREQ, SB), IMM3 | B30, "bclr/eq", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), |
1327 |
|
EBITOP_B (O (O_BCLRNE, SB), IMM3 | B30, "bclr/ne", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), |
1328 |
NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR|SRC,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP, |
EBITOP_B (O (O_BSETEQ, SB), IMM3 | B30, "bset/eq", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), |
1329 |
|
EBITOP_B (O (O_BSETNE, SB), IMM3 | B30, "bset/ne", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), |
1330 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RSIND,E}}, {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP, |
BITOP_B (O (O_BISTZ, SB), IMM3 | B31, "bistz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), |
1331 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP, |
BITOP_B (O (O_BSTZ, SB), IMM3 | B30, "bstz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), |
1332 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP, |
|
1333 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDDEC,E}}, {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP, |
{O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND, R3_8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}}, |
1334 |
|
{O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST, R3_8}}, {{0x7, 0xE, DSTABS8LIST, 0xF, R3_8, IMM8LIST, E}}}, |
1335 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS16DST,E}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP, |
{O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0xF, R3_8, IMM8LIST, E}}}, |
1336 |
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS32DST,E}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP, |
{O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0xF, R3_8, IMM8LIST, E}}}, |
1337 |
|
|
1338 |
SOP(O(O_SUB,SB),2,"sub.b"),{{RS8,RD8,E}},{{ 0x1,0x8,RS8,RD8,E,0,0,0,0}}EOP, |
/* Because the assembler treats SRC, DST and OP3 as ordinals, |
1339 |
|
I must designate the second argument, an immediate value, as DST. |
1340 |
NEW_SOP(O(O_SUB,SW),1,2,"sub.w"),{{RS16,RD16,E }}, {{0x1,0x9,RS16,RD16,E}} EOP, |
May God have mercy on my soul. */ |
1341 |
NEW_SOP(O(O_SUB,SW),0,4,"sub.w"),{{IMM16,RD16,E }}, {{0x7,0x9,0x3,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, |
{O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}}, {{0x7, 0xD, B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}}, |
1342 |
NEW_SOP(O(O_SUB,SL),0,2,"sub.l") ,{{RS32,RD32,E }}, {{0x1,0xA,B31|RS32,B30|RD32,E}} EOP, |
{O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}}, {{0x7, 0xF, OP3ABS8LIST, 0xF, RS8, DST | IMM8LIST, E}}}, |
1343 |
NEW_SOP(O(O_SUB,SL),0,6,"sub.l"), {{IMM32,RD32,E }},{{0x7,0xA,0x3,B30|RD32,IMM32LIST,E}} EOP, |
{O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST, 0xF, RS8, DST | IMM8LIST, E}}}, |
1344 |
|
{O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST, 0xF, RS8, DST | IMM8LIST, E}}}, |
1345 |
SOP(O(O_SUBS,SL),2,"subs"),{{KBIT,RDP,E}},{{ 0x1,0xB,KBIT,RDP,E,0,0,0,0}}EOP, |
|
1346 |
TWOOP(O(O_SUBX,SB),"subx",0xB,0x1,0xE), |
{O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL8, E}}, {{0x5, 0x5, PCREL8, DATA, E}}}, |
1347 |
|
{O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}}, |
1348 |
NEW_SOP(O(O_TRAPA,SB),0,2,"trapa"),{{ IMM2,E}}, {{0x5,0x7,IMM2,IGNORE,E }}EOP, |
{O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8, E}}, {{0x5, 0xd, B30 | LOWREG | L_8, 0x5, E}}}, |
1349 |
NEW_SOP(O(O_TAS,SB),0,2,"tas"),{{RSIND,E}}, {{0x0,0x1,0xe,0x0,0x7,0xb,B30|RSIND,0xc,E }}EOP, |
{O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16, E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}}, |
1350 |
|
{O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32, E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}}, |
1351 |
TWOOP(O(O_XOR, SB),"xor",0xD,0x1,0x5), |
|
1352 |
|
{O (O_CMP, SB), AV_H8, 2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}}, |
1353 |
NEW_SOP(O(O_XOR,SW),0,4,"xor.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x5,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, |
EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00), |
1354 |
NEW_SOP(O(O_XOR,SW),0,2,"xor.w"),{{RS16,RD16,E }},{{0x6,0x5,RS16,RD16,E}} EOP, |
|
1355 |
|
{O (O_CMP, SW), AV_H8, 2, "cmp.w", {{RS16, RD16, E}}, {{0x1, 0xd, RS16, RD16, E}}}, |
1356 |
NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x5,B30|RD32,IMM32LIST,E}} EOP, |
{O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16, E}}}, |
1357 |
NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E}} EOP, |
{O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, |
1358 |
|
{O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, |
1359 |
SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP, |
{O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, |
1360 |
SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP, |
EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2), |
1361 |
|
|
1362 |
NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}} EOP, |
{O (O_CMP, SL), AV_H8H, 6, "cmp.l", {{RS32, RD32, E}}, {{0x1, 0xf, B31 | RS32, B30 | RD32, E}}}, |
1363 |
NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E}} EOP, |
{O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, |
1364 |
NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{{RS32,MACREG,E}},{{0x0,0x3,MACREG,RS32,E}} EOP, |
EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2), |
1365 |
NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MACREG,RD32,E}},{{0x0,0x2,MACREG,RD32,E}} EOP, |
|
1366 |
NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP, |
UNOP (O (O_DAA, SB), "daa", 0x0, 0xF), |
1367 |
NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP, |
UNOP (O (O_DAS, SB), "das", 0x1, 0xF), |
1368 |
{0, 0, 0, NULL, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}, 0, 0, 0, 0} |
UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA), |
1369 |
|
|
1370 |
|
{O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16, E}}}, |
1371 |
|
{O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, |
1372 |
|
|
1373 |
|
{O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}}, |
1374 |
|
{O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}}, |
1375 |
|
{O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4, B30 | RD32, E}}}, |
1376 |
|
{O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, |
1377 |
|
|
1378 |
|
{O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}}, |
1379 |
|
{O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}}, |
1380 |
|
{O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4, B30 | RD32, E}}}, |
1381 |
|
{O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, |
1382 |
|
|
1383 |
|
{O (O_DIVXS, SB), AV_H8SX, 0, "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}}, |
1384 |
|
{O (O_DIVXS, SB), AV_H8H, 13, "divxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8, RD16, E}}}, |
1385 |
|
{O (O_DIVXS, SW), AV_H8SX, 0, "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}}, |
1386 |
|
{O (O_DIVXS, SW), AV_H8H, 21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}}, |
1387 |
|
|
1388 |
|
{O (O_DIVXU, SB), AV_H8SX, 0, "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}}, |
1389 |
|
{O (O_DIVXU, SB), AV_H8, 13, "divxu.b", {{RS8, RD16, E}}, {{0x5, 0x1, RS8, RD16, E}}}, |
1390 |
|
{O (O_DIVXU, SW), AV_H8SX, 0, "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}}, |
1391 |
|
{O (O_DIVXU, SW), AV_H8H, 21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3, RS16, B30 | RD32, E}}}, |
1392 |
|
|
1393 |
|
{O (O_EEPMOV, SB), AV_H8, 4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}}, |
1394 |
|
{O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}}, |
1395 |
|
|
1396 |
|
EXPAND_UNOP_STD_W (O (O_EXTS, SW), "exts.w", PREFIX_015, 0x1, 0x7, 0xd), |
1397 |
|
EXPAND_UNOP_STD_L (O (O_EXTS, SL), "exts.l", PREFIX_010, 0x1, 0x7, 0xf), |
1398 |
|
EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0), |
1399 |
|
EXPAND_UNOP_STD_W (O (O_EXTU, SW), "extu.w", PREFIX_015, 0x1, 0x7, 0x5), |
1400 |
|
EXPAND_UNOP_STD_L (O (O_EXTU, SL), "extu.l", PREFIX_010, 0x1, 0x7, 0x7), |
1401 |
|
EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0), |
1402 |
|
|
1403 |
|
UNOP (O (O_INC, SB), "inc", 0x0, 0xA), |
1404 |
|
|
1405 |
|
{O (O_INC, SW), AV_H8H, 2, "inc.w", {{DBIT, RD16, E}}, {{0x0, 0xB, 0x5 | DBIT, RD16, E}}}, |
1406 |
|
{O (O_INC, SL), AV_H8H, 2, "inc.l", {{DBIT, RD32, E}}, {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, |
1407 |
|
|
1408 |
|
{O (O_JMP, SN), AV_H8, 4, "jmp", {{RSIND, E}}, {{0x5, 0x9, B30 | RSIND, 0x0, E}}}, |
1409 |
|
{O (O_JMP, SN), AV_H8, 6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}}, |
1410 |
|
|
1411 |
|
{O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, |
1412 |
|
|
1413 |
|
{O (O_JMP, SN), AV_H8, 8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}}, |
1414 |
|
{O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}}, |
1415 |
|
|
1416 |
|
{O (O_JSR, SN), AV_H8, 6, "jsr", {{RSIND, E}}, {{0x5, 0xD, B30 | RSIND, 0x0, E}}}, |
1417 |
|
{O (O_JSR, SN), AV_H8, 8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}}, |
1418 |
|
|
1419 |
|
{O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, |
1420 |
|
|
1421 |
|
{O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}}, |
1422 |
|
{O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}}, |
1423 |
|
|
1424 |
|
{O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}}, |
1425 |
|
{O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}}, |
1426 |
|
{O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}}, |
1427 |
|
{O (O_LDC, SB), AV_H8S, 2, "ldc", {{RS8, EXR | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}}, |
1428 |
|
{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, |
1429 |
|
{O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSIND, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, |
1430 |
|
{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, |
1431 |
|
{O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSPOSTINC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, |
1432 |
|
{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, |
1433 |
|
{O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, |
1434 |
|
{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, |
1435 |
|
{O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, |
1436 |
|
{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, |
1437 |
|
{O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, |
1438 |
|
{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, |
1439 |
|
{O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, |
1440 |
|
|
1441 |
|
{O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}}, |
1442 |
|
|
1443 |
|
|
1444 |
|
{O (O_MOV, SB), AV_H8, 2, "mov.b", {{IMM8, RD8, E}}, {{0xF, RD8, IMM8LIST, E}}}, |
1445 |
|
{O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}}, |
1446 |
|
{O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}}, |
1447 |
|
MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8), |
1448 |
|
|
1449 |
|
{O (O_MOV, SB), AV_H8, 2, "mov.b", {{RS8, RD8, E}}, {{0x0, 0xC, RS8, RD8, E}}}, |
1450 |
|
MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), |
1451 |
|
{O (O_MOV, SB), AV_H8, 4, "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}}, |
1452 |
|
MOVTO_REG_BW (O (O_MOV, SB), "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), |
1453 |
|
{O (O_MOV, SB), AV_H8, 4, "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST, E}}}, |
1454 |
|
|
1455 |
|
MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND, FROM_IND), |
1456 |
|
MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC), |
1457 |
|
MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC), |
1458 |
|
MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC, FROM_PREINC), |
1459 |
|
MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC, FROM_PREDEC), |
1460 |
|
MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC, FROM_DISP2), |
1461 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16, DISP16LIST), |
1462 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32, DISP32LIST), |
1463 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16, FROM_DISP16B, DISP16LIST), |
1464 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16, FROM_DISP16W, DISP16LIST), |
1465 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16, FROM_DISP16L, DISP16LIST), |
1466 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32, FROM_DISP32B, DISP32LIST), |
1467 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32, FROM_DISP32W, DISP32LIST), |
1468 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32, FROM_DISP32L, DISP32LIST), |
1469 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC, FROM_ABS16, ABS16LIST), |
1470 |
|
MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC, FROM_ABS32, ABS32LIST), |
1471 |
|
|
1472 |
|
{O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16, E}}}, |
1473 |
|
{O (O_MOV, SW), AV_H8, 4, "mov.w", {{IMM16, RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}}, |
1474 |
|
{O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}}, |
1475 |
|
{O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}}, |
1476 |
|
|
1477 |
|
MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS), |
1478 |
|
MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST), |
1479 |
|
|
1480 |
|
{O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}}, |
1481 |
|
MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0), |
1482 |
|
MOVTO_REG_BW (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0), |
1483 |
|
|
1484 |
|
MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND, FROM_IND), |
1485 |
|
MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC), |
1486 |
|
MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC), |
1487 |
|
MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC, FROM_PREINC), |
1488 |
|
MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC, FROM_PREDEC), |
1489 |
|
MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC, FROM_DISP2), |
1490 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16, DISP16LIST), |
1491 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32, DISP32LIST), |
1492 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16, FROM_DISP16B, DISP16LIST), |
1493 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16, FROM_DISP16W, DISP16LIST), |
1494 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16, FROM_DISP16L, DISP16LIST), |
1495 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32, FROM_DISP32B, DISP32LIST), |
1496 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32, FROM_DISP32W, DISP32LIST), |
1497 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32, FROM_DISP32L, DISP32LIST), |
1498 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC, FROM_ABS16, ABS16LIST), |
1499 |
|
MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC, FROM_ABS32, ABS32LIST), |
1500 |
|
|
1501 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, |
1502 |
|
|
1503 |
|
MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS), |
1504 |
|
MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST), |
1505 |
|
|
1506 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}}, |
1507 |
|
{O (O_MOV, SL), AV_H8H, 4, "mov.l", {{IMM32, RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST, E}}}, |
1508 |
|
|
1509 |
|
MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST), |
1510 |
|
|
1511 |
|
{O (O_MOV, SL), AV_H8H, 2, "mov.l", {{RS32, RD32, E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}}, |
1512 |
|
|
1513 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDIND, E}}, {{PREFIX_0100, 0x6, 0x9, B31 | RDIND, B30 | RS32, E}}}, |
1514 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103, 0x6, 0xd, B31 | RDPOSTINC, RS32, E}}}, |
1515 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101, 0x6, 0xd, B31 | RDPOSTDEC, RS32, E}}}, |
1516 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC, E}}, {{PREFIX_0102, 0x6, 0xd, B31 | RDPREINC, RS32, E}}}, |
1517 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDPREDEC, E}}, {{PREFIX_0100, 0x6, 0xd, B31 | RDPREDEC, RS32, E}}}, |
1518 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}}, |
1519 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, |
1520 |
|
{O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, |
1521 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, |
1522 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, |
1523 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, |
1524 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, |
1525 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, |
1526 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, |
1527 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, |
1528 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS16DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0x8, RS32, DSTABS16LIST, E}}}, |
1529 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS32DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTABS32LIST, E}}}, |
1530 |
|
|
1531 |
|
{O (O_MOV, SL), AV_H8H, 4, "mov.l", {{RSIND, RD32, E}}, {{PREFIX_0100, 0x6, 0x9, B30 | RSIND, RD32, E}}}, |
1532 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100, 0x6, 0xd, B30 | RSPOSTINC, RD32, E}}}, |
1533 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102, 0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}}, |
1534 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC, RD32, E}}, {{PREFIX_0101, 0x6, 0xd, B30 | RSPREINC, RD32, E}}}, |
1535 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC, RD32, E}}, {{PREFIX_0103, 0x6, 0xd, B30 | RSPREDEC, RD32, E}}}, |
1536 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}}, |
1537 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, |
1538 |
|
{O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, |
1539 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, |
1540 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, |
1541 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, |
1542 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, |
1543 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, |
1544 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, |
1545 |
|
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, |
1546 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x0, RD32, SRC | ABS16LIST, E}}}, |
1547 |
|
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS32SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x2, RD32, SRC | MEMRELAX | ABS32LIST, E}}}, |
1548 |
|
|
1549 |
|
MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND, FROM_IND), |
1550 |
|
MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC), |
1551 |
|
MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC), |
1552 |
|
MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC, FROM_PREINC), |
1553 |
|
MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC, FROM_PREDEC), |
1554 |
|
MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC, FROM_DISP2), |
1555 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16, DISP16LIST), |
1556 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32, DISP32LIST), |
1557 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16, FROM_DISP16B, DISP16LIST), |
1558 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16, FROM_DISP16W, DISP16LIST), |
1559 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16, FROM_DISP16L, DISP16LIST), |
1560 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32, FROM_DISP32B, DISP32LIST), |
1561 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32, FROM_DISP32W, DISP32LIST), |
1562 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32, FROM_DISP32L, DISP32LIST), |
1563 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC, FROM_ABS16, ABS16LIST), |
1564 |
|
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST), |
1565 |
|
|
1566 |
|
#define DO_MOVA1(TYPE, OP0, OP1) \ |
1567 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, DISP16LIST, E}}}, \ |
1568 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, DISP16LIST, E}}}, \ |
1569 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, DISP16LIST, E}}}, \ |
1570 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, DISP16LIST, E}}}, \ |
1571 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, DISP16LIST, E}}}, \ |
1572 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, DISP16LIST, E}}}, \ |
1573 |
|
\ |
1574 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, DISP32LIST, E}}}, \ |
1575 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, DISP32LIST, E}}}, \ |
1576 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, DISP32LIST, E}}}, \ |
1577 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, DISP32LIST, E}}}, \ |
1578 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, DISP32LIST, E}}}, \ |
1579 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, DISP32LIST, E}}} |
1580 |
|
|
1581 |
|
#define DO_MOVA2(TYPE, OP0, OP1, OP2) \ |
1582 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, DISP16LIST, E}}}, \ |
1583 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, DISP16LIST, E}}}, \ |
1584 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, DISP16LIST, E}}}, \ |
1585 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, DISP16LIST, E}}}, \ |
1586 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, DISP16LIST, E}}}, \ |
1587 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, DISP16LIST, E}}}, \ |
1588 |
|
\ |
1589 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, DISP32LIST, E}}}, \ |
1590 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, DISP32LIST, E}}}, \ |
1591 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, DISP32LIST, E}}}, \ |
1592 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, DISP32LIST, E}}}, \ |
1593 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, DISP32LIST, E}}}, \ |
1594 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, DISP32LIST, E}}} |
1595 |
|
|
1596 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, DISP16LIST, E}}}, |
1597 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, DISP16LIST, E}}}, |
1598 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, DISP16LIST, E}}}, |
1599 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, DISP16LIST, E}}}, |
1600 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, DISP16LIST, E}}}, |
1601 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, DISP16LIST, E}}}, |
1602 |
|
|
1603 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, DISP32LIST, E}}}, |
1604 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, DISP32LIST, E}}}, |
1605 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, DISP32LIST, E}}}, |
1606 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, DISP32LIST, E}}}, |
1607 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, DISP32LIST, E}}}, |
1608 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, DISP32LIST, E}}}, |
1609 |
|
|
1610 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, DISP16LIST, E}}}, |
1611 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, DISP16LIST, E}}}, |
1612 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, DISP16LIST, E}}}, |
1613 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, DISP16LIST, E}}}, |
1614 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, DISP16LIST, E}}}, |
1615 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, DISP16LIST, E}}}, |
1616 |
|
|
1617 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, DISP32LIST, E}}}, |
1618 |
|
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, DISP32LIST, E}}}, |
1619 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, DISP32LIST, E}}}, |
1620 |
|
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, DISP32LIST, E}}}, |
1621 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, DISP32LIST, E}}}, |
1622 |
|
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, DISP32LIST, E}}}, |
1623 |
|
|
1624 |
|
DO_MOVA1 (RDIND, 0x0, B30 | RDIND), |
1625 |
|
DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC), |
1626 |
|
DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC), |
1627 |
|
DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC), |
1628 |
|
DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC), |
1629 |
|
DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG), |
1630 |
|
DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, DSTDISP16LIST), |
1631 |
|
DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, DSTDISP32LIST), |
1632 |
|
DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, DSTDISP16LIST), |
1633 |
|
DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, DSTDISP16LIST), |
1634 |
|
DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, DSTDISP16LIST), |
1635 |
|
DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, DSTDISP32LIST), |
1636 |
|
DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, DSTDISP32LIST), |
1637 |
|
DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, DSTDISP32LIST), |
1638 |
|
DO_MOVA2 (ABS16DST, 0x4, 0x0, DSTABS16LIST), |
1639 |
|
DO_MOVA2 (ABS32DST, 0x4, 0x8, DSTABS32LIST), |
1640 |
|
|
1641 |
|
{O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}}, |
1642 |
|
{O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}}, |
1643 |
|
|
1644 |
|
{O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}}, {{0x7, 0xb, 0x9, 0x4, E}}}, |
1645 |
|
{O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}}, {{0x7, 0xb, 0xa, 0x4, E}}}, |
1646 |
|
{O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}}, {{0x7, 0xb, 0xb, 0x4, E}}}, |
1647 |
|
{O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}}, |
1648 |
|
|
1649 |
|
{O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}}, |
1650 |
|
{O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}}, |
1651 |
|
{O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4, B30 | RD32, E}}}, |
1652 |
|
{O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, |
1653 |
|
|
1654 |
|
{O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}}, |
1655 |
|
{O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}}, |
1656 |
|
{O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4, B30 | RD32, E}}}, |
1657 |
|
{O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, |
1658 |
|
|
1659 |
|
{O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4, B30 | RD32, E}}}, |
1660 |
|
{O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, |
1661 |
|
{O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4, B30 | RD32, E}}}, |
1662 |
|
{O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, |
1663 |
|
|
1664 |
|
{O (O_MULXS, SB), AV_H8SX, 0, "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16, E}}}, |
1665 |
|
{O (O_MULXS, SB), AV_H8H, 20, "mulxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8, RD16, E}}}, |
1666 |
|
{O (O_MULXS, SW), AV_H8SX, 0, "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}}, |
1667 |
|
{O (O_MULXS, SW), AV_H8H, 20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}}, |
1668 |
|
|
1669 |
|
{O (O_MULXU, SB), AV_H8SX, 0, "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}}, |
1670 |
|
{O (O_MULXU, SB), AV_H8, 14, "mulxu.b", {{RS8, RD16, E}}, {{0x5, 0x0, RS8, RD16, E}}}, |
1671 |
|
{O (O_MULXU, SW), AV_H8SX, 0, "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}}, |
1672 |
|
{O (O_MULXU, SW), AV_H8H, 14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2, RS16, B30 | RD32, E}}}, |
1673 |
|
|
1674 |
|
EXPAND_UNOP_STD_B (O (O_NEG, SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8), |
1675 |
|
EXPAND_UNOP_STD_W (O (O_NEG, SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9), |
1676 |
|
EXPAND_UNOP_STD_L (O (O_NEG, SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb), |
1677 |
|
|
1678 |
|
{O (O_NOP, SN), AV_H8, 2, "nop", {{E}}, {{0x0, 0x0, 0x0, 0x0, E}}}, |
1679 |
|
|
1680 |
|
EXPAND_UNOP_STD_B (O (O_NOT, SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0), |
1681 |
|
EXPAND_UNOP_STD_W (O (O_NOT, SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1), |
1682 |
|
EXPAND_UNOP_STD_L (O (O_NOT, SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3), |
1683 |
|
|
1684 |
|
{O (O_OR, SB), AV_H8, 2, "or.b", {{IMM8, RD8, E}}, {{0xc, RD8, IMM8LIST, E}}}, |
1685 |
|
EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0), |
1686 |
|
|
1687 |
|
{O (O_OR, SW), AV_H8, 2, "or.w", {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}}, |
1688 |
|
EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4), |
1689 |
|
|
1690 |
|
{O (O_OR, SL), AV_H8H, 2, "or.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}}, |
1691 |
|
EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4), |
1692 |
|
|
1693 |
|
{O (O_ORC, SB), AV_H8, 2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}}, |
1694 |
|
{O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}}, |
1695 |
|
|
1696 |
|
{O (O_MOV, SW), AV_H8, 6, "pop.w", {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}}, |
1697 |
|
{O (O_MOV, SL), AV_H8H, 6, "pop.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}}, |
1698 |
|
{O (O_MOV, SW), AV_H8, 6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}}, |
1699 |
|
{O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}}, |
1700 |
|
|
1701 |
|
EXPAND_UNOP_STD_B (O (O_ROTL, SB), "rotl.b", PREFIX_017, 0x1, 0x2, 0x8), |
1702 |
|
EXPAND_UNOP_EXTENDED_B (O (O_ROTL, SB), "rotl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0xc), |
1703 |
|
EXPAND_UNOP_STD_W (O (O_ROTL, SW), "rotl.w", PREFIX_015, 0x1, 0x2, 0x9), |
1704 |
|
EXPAND_UNOP_EXTENDED_W (O (O_ROTL, SW), "rotl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0xd), |
1705 |
|
EXPAND_UNOP_STD_L (O (O_ROTL, SL), "rotl.l", PREFIX_010, 0x1, 0x2, 0xb), |
1706 |
|
EXPAND_UNOP_EXTENDED_L (O (O_ROTL, SL), "rotl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30), |
1707 |
|
EXPAND_UNOP_STD_B (O (O_ROTR, SB), "rotr.b", PREFIX_017, 0x1, 0x3, 0x8), |
1708 |
|
EXPAND_UNOP_EXTENDED_B (O (O_ROTR, SB), "rotr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0xc), |
1709 |
|
EXPAND_UNOP_STD_W (O (O_ROTR, SW), "rotr.w", PREFIX_015, 0x1, 0x3, 0x9), |
1710 |
|
EXPAND_UNOP_EXTENDED_W (O (O_ROTR, SW), "rotr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0xd), |
1711 |
|
EXPAND_UNOP_STD_L (O (O_ROTR, SL), "rotr.l", PREFIX_010, 0x1, 0x3, 0xb), |
1712 |
|
EXPAND_UNOP_EXTENDED_L (O (O_ROTR, SL), "rotr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30), |
1713 |
|
EXPAND_UNOP_STD_B (O (O_ROTXL, SB), "rotxl.b", PREFIX_017, 0x1, 0x2, 0x0), |
1714 |
|
EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4), |
1715 |
|
EXPAND_UNOP_STD_W (O (O_ROTXL, SW), "rotxl.w", PREFIX_015, 0x1, 0x2, 0x1), |
1716 |
|
EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5), |
1717 |
|
EXPAND_UNOP_STD_L (O (O_ROTXL, SL), "rotxl.l", PREFIX_010, 0x1, 0x2, 0x3), |
1718 |
|
EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30), |
1719 |
|
EXPAND_UNOP_STD_B (O (O_ROTXR, SB), "rotxr.b", PREFIX_017, 0x1, 0x3, 0x0), |
1720 |
|
EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4), |
1721 |
|
EXPAND_UNOP_STD_W (O (O_ROTXR, SW), "rotxr.w", PREFIX_015, 0x1, 0x3, 0x1), |
1722 |
|
EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5), |
1723 |
|
EXPAND_UNOP_STD_L (O (O_ROTXR, SL), "rotxr.l", PREFIX_010, 0x1, 0x3, 0x3), |
1724 |
|
EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30), |
1725 |
|
|
1726 |
|
|
1727 |
|
{O (O_BPT, SN), AV_H8, 10, "bpt", {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}}, |
1728 |
|
{O (O_RTE, SN), AV_H8, 10, "rte", {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}}, |
1729 |
|
{O (O_RTS, SN), AV_H8, 8, "rts", {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}}, |
1730 |
|
{O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}}, |
1731 |
|
{O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}}, |
1732 |
|
|
1733 |
|
EXPAND_UNOP_STD_B (O (O_SHAL, SB), "shal.b", PREFIX_017, 0x1, 0x0, 0x8), |
1734 |
|
EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc), |
1735 |
|
EXPAND_UNOP_STD_W (O (O_SHAL, SW), "shal.w", PREFIX_015, 0x1, 0x0, 0x9), |
1736 |
|
EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd), |
1737 |
|
EXPAND_UNOP_STD_L (O (O_SHAL, SL), "shal.l", PREFIX_010, 0x1, 0x0, 0xb), |
1738 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30), |
1739 |
|
EXPAND_UNOP_STD_B (O (O_SHAR, SB), "shar.b", PREFIX_017, 0x1, 0x1, 0x8), |
1740 |
|
EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc), |
1741 |
|
EXPAND_UNOP_STD_W (O (O_SHAR, SW), "shar.w", PREFIX_015, 0x1, 0x1, 0x9), |
1742 |
|
EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd), |
1743 |
|
EXPAND_UNOP_STD_L (O (O_SHAR, SL), "shar.l", PREFIX_010, 0x1, 0x1, 0xb), |
1744 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30), |
1745 |
|
|
1746 |
|
EXPAND_UNOP_STD_B (O (O_SHLL, SB), "shll.b", PREFIX_017, 0x1, 0x0, 0x0), |
1747 |
|
|
1748 |
|
{O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x0, RD8, E}}}, |
1749 |
|
|
1750 |
|
EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4), |
1751 |
|
EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa), |
1752 |
|
{O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}}, |
1753 |
|
|
1754 |
|
EXPAND_UNOP_STD_W (O (O_SHLL, SW), "shll.w", PREFIX_015, 0x1, 0x0, 0x1), |
1755 |
|
|
1756 |
|
{O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x1, RD16, E}}}, |
1757 |
|
|
1758 |
|
EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5), |
1759 |
|
EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2), |
1760 |
|
EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6), |
1761 |
|
{O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}}, |
1762 |
|
|
1763 |
|
EXPAND_UNOP_STD_L (O (O_SHLL, SL), "shll.l", PREFIX_010, 0x1, 0x0, 0x3), |
1764 |
|
|
1765 |
|
{O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x3, B30 | RD32, E}}}, |
1766 |
|
|
1767 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2, PREFIX_010, 0x1, 0x0, 0x7, B30), |
1768 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4, PREFIX_010, 0x1, 0x0, 0x3, B31), |
1769 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8, PREFIX_010, 0x1, 0x0, 0x7, B31), |
1770 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31), |
1771 |
|
{O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}}, |
1772 |
|
|
1773 |
|
EXPAND_UNOP_STD_B (O (O_SHLR, SB), "shlr.b", PREFIX_017, 0x1, 0x1, 0x0), |
1774 |
|
|
1775 |
|
{O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x0, RD8, E}}}, |
1776 |
|
|
1777 |
|
EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4), |
1778 |
|
EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa), |
1779 |
|
{O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}}, |
1780 |
|
|
1781 |
|
EXPAND_UNOP_STD_W (O (O_SHLR, SW), "shlr.w", PREFIX_015, 0x1, 0x1, 0x1), |
1782 |
|
|
1783 |
|
{O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x1, RD16, E}}}, |
1784 |
|
|
1785 |
|
EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5), |
1786 |
|
EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2), |
1787 |
|
EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6), |
1788 |
|
{O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}, |
1789 |
|
|
1790 |
|
EXPAND_UNOP_STD_L (O (O_SHLR, SL), "shlr.l", PREFIX_010, 0x1, 0x1, 0x3), |
1791 |
|
|
1792 |
|
{O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x3, B30 | RD32, E}}}, |
1793 |
|
|
1794 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2, PREFIX_010, 0x1, 0x1, 0x7, B30), |
1795 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4, PREFIX_010, 0x1, 0x1, 0x3, B31), |
1796 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8, PREFIX_010, 0x1, 0x1, 0x7, B31), |
1797 |
|
EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31), |
1798 |
|
{O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}}, |
1799 |
|
|
1800 |
|
{O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}}, |
1801 |
|
|
1802 |
|
{O (O_STC, SB), AV_H8, 2, "stc", {{CCR | SRC, RD8, E}}, {{0x0, 0x2, B30 | CCR | SRC, RD8, E}}}, |
1803 |
|
{O (O_STC, SB), AV_H8S, 2, "stc", {{EXR | SRC, RD8, E}}, {{0x0, 0x2, B30 | EXR | SRC, RD8, E}}}, |
1804 |
|
{O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, |
1805 |
|
{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, |
1806 |
|
{O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, |
1807 |
|
{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, |
1808 |
|
{O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, |
1809 |
|
{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, |
1810 |
|
{O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, |
1811 |
|
{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, |
1812 |
|
{O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, |
1813 |
|
{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, |
1814 |
|
{O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, |
1815 |
|
{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, |
1816 |
|
{O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}}, |
1817 |
|
|
1818 |
|
|
1819 |
|
EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01), |
1820 |
|
|
1821 |
|
{O (O_SUB, SW), AV_H8, 2, "sub.w", {{RS16, RD16, E}}, {{0x1, 0x9, RS16, RD16, E}}}, |
1822 |
|
{O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16, E}}}, |
1823 |
|
{O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, |
1824 |
|
{O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, |
1825 |
|
{O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, |
1826 |
|
EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3), |
1827 |
|
|
1828 |
|
{O (O_SUB, SL), AV_H8H, 6, "sub.l", {{RS32, RD32, E}}, {{0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, |
1829 |
|
{O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, |
1830 |
|
EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3), |
1831 |
|
|
1832 |
|
{O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}}, |
1833 |
|
|
1834 |
|
{O (O_SUBX, SB), AV_H8, 2, "subx", {{IMM8, RD8, E}}, {{0xb, RD8, IMM8LIST, E}}}, |
1835 |
|
{O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, |
1836 |
|
{O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, |
1837 |
|
{O (O_SUBX, SB), AV_H8, 2, "subx", {{RS8, RD8, E}}, {{0x1, 0xe, RS8, RD8, E}}}, |
1838 |
|
{O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, |
1839 |
|
{O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, |
1840 |
|
{O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, |
1841 |
|
{O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, |
1842 |
|
{O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, |
1843 |
|
{O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, |
1844 |
|
|
1845 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x3, RD16, IMM16LIST, E}}}, |
1846 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, |
1847 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, |
1848 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x1, 0x9, RS16, RD16, E}}}, |
1849 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, |
1850 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, |
1851 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, |
1852 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, |
1853 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, |
1854 |
|
{O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, |
1855 |
|
|
1856 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x3, RD32, IMM32LIST, E}}}, |
1857 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, |
1858 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, |
1859 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, |
1860 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, |
1861 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, |
1862 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, |
1863 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, |
1864 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, |
1865 |
|
{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, |
1866 |
|
|
1867 |
|
{O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2, E}}, {{0x5, 0x7, IMM2, IGNORE, E}}}, |
1868 |
|
{O (O_TAS, SB), AV_H8H, 2, "tas", {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}}, |
1869 |
|
|
1870 |
|
{O (O_XOR, SB), AV_H8, 2, "xor.b", {{IMM8, RD8, E}}, {{0xd, RD8, IMM8LIST, E}}}, |
1871 |
|
EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0), |
1872 |
|
|
1873 |
|
{O (O_XOR, SW), AV_H8, 2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}}, |
1874 |
|
EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5), |
1875 |
|
|
1876 |
|
{O (O_XOR, SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}}, |
1877 |
|
EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5), |
1878 |
|
|
1879 |
|
{O (O_XORC, SB), AV_H8, 2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}}, |
1880 |
|
{O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}}, |
1881 |
|
|
1882 |
|
{O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}}, |
1883 |
|
{O (O_MAC, SW), AV_H8S, 2, "mac", {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}}, |
1884 |
|
{O (O_LDMAC, SL), AV_H8S, 2, "ldmac", {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}}, |
1885 |
|
{O (O_STMAC, SL), AV_H8S, 2, "stmac", {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}}, |
1886 |
|
{O (O_LDM, SL), AV_H8H, 6, "ldm.l", {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}}, |
1887 |
|
{O (O_STM, SL), AV_H8H, 6, "stm.l", {{RS32, RDPREDEC, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}}, |
1888 |
|
{0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}} |
1889 |
}; |
}; |
1890 |
#else |
#else |
1891 |
extern struct h8_opcode h8_opcodes[]; |
extern const struct h8_opcode h8_opcodes[]; |
1892 |
#endif |
#endif |
1893 |
|
|