/[gcl]/gcl/binutils/include/opcode/cris.h
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revision 1.1.1.1 by camm, Fri Aug 9 05:36:49 2002 UTC revision 1.1.1.1.20.1 by camm, Fri Sep 30 02:10:25 2005 UTC
# Line 1  Line 1 
1  /* cris.h -- Header file for CRIS opcode and register tables.  /* cris.h -- Header file for CRIS opcode and register tables.
2     Copyright (C) 2000, 2001 Free Software Foundation, Inc.     Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc.
3     Contributed by Axis Communications AB, Lund, Sweden.     Contributed by Axis Communications AB, Lund, Sweden.
4     Originally written for GAS 1.38.1 by Mikael Asker.     Originally written for GAS 1.38.1 by Mikael Asker.
5     Updated, BFDized and GNUified by Hans-Peter Nilsson.     Updated, BFDized and GNUified by Hans-Peter Nilsson.
# Line 38  Foundation, Inc., 59 Temple Place - Suit Line 38  Foundation, Inc., 59 Temple Place - Suit
38     immediate operands.  */     immediate operands.  */
39  enum cris_insn_version_usage  enum cris_insn_version_usage
40  {  {
41    /* Any version. */    /* Any version.  */
42    cris_ver_version_all=0,    cris_ver_version_all=0,
43    
44    /* Indeterminate (intended for disassembly only, or obsolete).  */    /* Indeterminate (intended for disassembly only, or obsolete).  */
45    cris_ver_warning,    cris_ver_warning,
46    
   /* Simulator only (reserved).  */  
   cris_ver_sim,  
   
47    /* Only for v0..3 (Etrax 1..4).  */    /* Only for v0..3 (Etrax 1..4).  */
48    cris_ver_v0_3,    cris_ver_v0_3,
49    
# Line 59  enum cris_insn_version_usage Line 56  enum cris_insn_version_usage
56    /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX).  */    /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX).  */
57    cris_ver_v8p,    cris_ver_v8p,
58    
59    /* Only for v10 or higher (ETRAX 100 LX).    /* Only for v0..10.  FIXME: Not sure what to do with this.  */
60       Of course some or all these of may change to cris_ver_v10p if/when    cris_ver_sim_v0_10,
61    
62      /* Only for v0..10.  */
63      cris_ver_v0_10,
64    
65      /* Only for v3..10.  (ETRAX 4, ETRAX 100 and ETRAX 100 LX).  */
66      cris_ver_v3_10,
67    
68      /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX).  */
69      cris_ver_v8_10,
70    
71      /* Only for v10 (ETRAX 100 LX) and same series.  */
72      cris_ver_v10,
73    
74      /* Only for v10 (ETRAX 100 LX) and same series.  */
75      cris_ver_v10p,
76    
77      /* Only for v32 or higher (codename GUINNESS).
78         Of course some or all these of may change to cris_ver_v32p if/when
79       there's a new revision. */       there's a new revision. */
80    cris_ver_v10p    cris_ver_v32p
81  };  };
82    
83    
# Line 85  struct cris_spec_reg Line 100  struct cris_spec_reg
100  };  };
101  extern const struct cris_spec_reg cris_spec_regs[];  extern const struct cris_spec_reg cris_spec_regs[];
102    
103    
104    /* Support registers (kind of special too, but not named as such).  */
105    struct cris_support_reg
106    {
107      const char *const name;
108      unsigned int number;
109    };
110    extern const struct cris_support_reg cris_support_regs[];
111    
112    struct cris_cond15
113    {
114      /* The name of the condition.  */
115      const char *const name;
116    
117      /* What CPU version this condition name applies to.  */
118      enum cris_insn_version_usage applicable_version;
119    };
120    extern const struct cris_cond15 cris_conds15[];
121    
122  /* Opcode-dependent constants.  */  /* Opcode-dependent constants.  */
123  #define AUTOINCR_BIT (0x04)  #define AUTOINCR_BIT (0x04)
124    
# Line 163  extern const char *const cris_cc_strings Line 197  extern const char *const cris_cc_strings
197  #define ADD_PC_INCR_OPCODE \  #define ADD_PC_INCR_OPCODE \
198   (0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC)   (0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC)
199    
200    #define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
201    
202    /* BA DWORD (V32).  */
203    #define BA_DWORD_OPCODE (0x0EBF)
204    
205  /* Nop.  */  /* Nop.  */
206  #define NOP_OPCODE (0x050F)  #define NOP_OPCODE (0x050F)
207  #define NOP_Z_BITS (0xFAF0)  #define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
208    
209    #define NOP_OPCODE_V32 (0x05B0)
210    #define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
211    
212    /* For the compatibility mode, let's use "MOVE R0,P0".  Doesn't affect
213       registers or flags.  Unfortunately shuts off interrupts for one cycle
214       for < v32, but there doesn't seem to be any alternative without that
215       effect.  */
216    #define NOP_OPCODE_COMMON (0x630)
217    #define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
218    
219    /* LAPC.D  */
220    #define LAPC_DWORD_OPCODE (0x0D7F)
221    #define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
222    
223  /* Structure of an opcode table entry.  */  /* Structure of an opcode table entry.  */
224  enum cris_imm_oprnd_size_type  enum cris_imm_oprnd_size_type
# Line 179  enum cris_imm_oprnd_size_type Line 232  enum cris_imm_oprnd_size_type
232    /* Indicated by size of special register.  */    /* Indicated by size of special register.  */
233    SIZE_SPEC_REG,    SIZE_SPEC_REG,
234    
235    /* Indicated by size field.  */    /* Indicated by size field, signed.  */
236      SIZE_FIELD_SIGNED,
237    
238      /* Indicated by size field, unsigned.  */
239      SIZE_FIELD_UNSIGNED,
240    
241      /* Indicated by size field, no sign implied.  */
242    SIZE_FIELD    SIZE_FIELD
243  };  };
244    

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