/[gcl]/gcl/binutils/include/opcode/arm.h
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revision 1.1.1.1 by camm, Fri Aug 9 05:36:49 2002 UTC revision 1.2 by camm, Fri Sep 9 23:32:34 2005 UTC
# Line 1  Line 1 
1  /* ARM opcode list.  /* ARM assembler/disassembler support.
2     Copyright 1989, 1991 Free Software Foundation, Inc.     Copyright 2004 Free Software Foundation, Inc.
3    
4  This file is part of GDB and GAS.     This file is part of GDB and GAS.
5    
6  GDB and GAS are free software; you can redistribute it and/or modify     GDB and GAS are free software; you can redistribute it and/or
7  it under the terms of the GNU General Public License as published by     modify it under the terms of the GNU General Public License as
8  the Free Software Foundation; either version 1, or (at your option)     published by the Free Software Foundation; either version 1, or (at
9  any later version.     your option) any later version.
10    
11  GDB and GAS are distributed in the hope that it will be useful,     GDB and GAS are distributed in the hope that it will be useful, but
12  but WITHOUT ANY WARRANTY; without even the implied warranty of     WITHOUT ANY WARRANTY; without even the implied warranty of
13  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  GNU General Public License for more details.     General Public License for more details.
15    
16  You should have received a copy of the GNU General Public License     You should have received a copy of the GNU General Public License
17  along with GDB or GAS; see the file COPYING.  If not, write to     along with GDB or GAS; see the file COPYING.  If not, write to the
18  the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */     Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19       02111-1307, USA.  */
20  /* types of instruction (encoded in bits 26 and 27 of the instruction) */  
21    /* The following bitmasks control CPU extensions:  */
22  #define TYPE_ARITHMETIC         0  #define ARM_EXT_V1       0x00000001     /* All processors (core set).  */
23  #define TYPE_LDR_STR            1  #define ARM_EXT_V2       0x00000002     /* Multiply instructions.  */
24  #define TYPE_BLOCK_BRANCH       2  #define ARM_EXT_V2S      0x00000004     /* SWP instructions.       */
25  #define TYPE_SWI                3  #define ARM_EXT_V3       0x00000008     /* MSR MRS.                */
26    #define ARM_EXT_V3M      0x00000010     /* Allow long multiplies.  */
27  /* bit 25 decides whether an instruction is a block move or a branch */  #define ARM_EXT_V4       0x00000020     /* Allow half word loads.  */
28  #define SUBTYPE_BLOCK           0  #define ARM_EXT_V4T      0x00000040     /* Thumb v1.               */
29  #define SUBTYPE_BRANCH          1  #define ARM_EXT_V5       0x00000080     /* Allow CLZ, etc.         */
30    #define ARM_EXT_V5T      0x00000100     /* Thumb v2.               */
31  /* codes to distinguish the arithmetic instructions */  #define ARM_EXT_V5ExP    0x00000200     /* DSP core set.           */
32    #define ARM_EXT_V5E      0x00000400     /* DSP Double transfers.   */
33  #define OPCODE_AND      0  #define ARM_EXT_V5J      0x00000800     /* Jazelle extension.      */
34  #define OPCODE_EOR      1  #define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
35  #define OPCODE_SUB      2  #define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
36  #define OPCODE_RSB      3  #define ARM_EXT_V6Z      0x00004000     /* ARM V6Z.                */
37  #define OPCODE_ADD      4  
38  #define OPCODE_ADC      5  /* Co-processor space extensions.  */
39  #define OPCODE_SBC      6  #define ARM_CEXT_XSCALE   0x00800000    /* Allow MIA etc.          */
40  #define OPCODE_RSC      7  #define ARM_CEXT_MAVERICK 0x00400000    /* Use Cirrus/DSP coprocessor.  */
41  #define OPCODE_TST      8  #define ARM_CEXT_IWMMXT   0x00200000    /* Intel Wireless MMX technology coprocessor.   */
42  #define OPCODE_TEQ      9  
43  #define OPCODE_CMP      10  /* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
44  #define OPCODE_CMN      11     defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
45  #define OPCODE_ORR      12     ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE.  To these we add
46  #define OPCODE_MOV      13     three more to cover cores prior to ARM6.  Finally, there are cores which
47  #define OPCODE_BIC      14     implement further extensions in the co-processor space.  */
48  #define OPCODE_MVN      15  #define ARM_ARCH_V1                       ARM_EXT_V1
49    #define ARM_ARCH_V2     (ARM_ARCH_V1    | ARM_EXT_V2)
50  /* condition codes */  #define ARM_ARCH_V2S    (ARM_ARCH_V2    | ARM_EXT_V2S)
51    #define ARM_ARCH_V3     (ARM_ARCH_V2S   | ARM_EXT_V3)
52  #define COND_EQ         0  #define ARM_ARCH_V3M    (ARM_ARCH_V3    | ARM_EXT_V3M)
53  #define COND_NE         1  #define ARM_ARCH_V4xM   (ARM_ARCH_V3    | ARM_EXT_V4)
54  #define COND_CS         2  #define ARM_ARCH_V4     (ARM_ARCH_V3M   | ARM_EXT_V4)
55  #define COND_CC         3  #define ARM_ARCH_V4TxM  (ARM_ARCH_V4xM  | ARM_EXT_V4T)
56  #define COND_MI         4  #define ARM_ARCH_V4T    (ARM_ARCH_V4    | ARM_EXT_V4T)
57  #define COND_PL         5  #define ARM_ARCH_V5xM   (ARM_ARCH_V4xM  | ARM_EXT_V5)
58  #define COND_VS         6  #define ARM_ARCH_V5     (ARM_ARCH_V4    | ARM_EXT_V5)
59  #define COND_VC         7  #define ARM_ARCH_V5TxM  (ARM_ARCH_V5xM  | ARM_EXT_V4T | ARM_EXT_V5T)
60  #define COND_HI         8  #define ARM_ARCH_V5T    (ARM_ARCH_V5    | ARM_EXT_V4T | ARM_EXT_V5T)
61  #define COND_LS         9  #define ARM_ARCH_V5TExP (ARM_ARCH_V5T   | ARM_EXT_V5ExP)
62  #define COND_GE         10  #define ARM_ARCH_V5TE   (ARM_ARCH_V5TExP | ARM_EXT_V5E)
63  #define COND_LT         11  #define ARM_ARCH_V5TEJ  (ARM_ARCH_V5TE  | ARM_EXT_V5J)
64  #define COND_GT         12  #define ARM_ARCH_V6     (ARM_ARCH_V5TEJ | ARM_EXT_V6)
65  #define COND_LE         13  #define ARM_ARCH_V6K    (ARM_ARCH_V6    | ARM_EXT_V6K)
66  #define COND_AL         14  #define ARM_ARCH_V6Z    (ARM_ARCH_V6    | ARM_EXT_V6Z)
67  #define COND_NV         15  #define ARM_ARCH_V6ZK   (ARM_ARCH_V6    | ARM_EXT_V6K | ARM_EXT_V6Z)
68    
69  /* Describes the format of an ARM machine instruction */  /* Processors with specific extensions in the co-processor space.  */
70    #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE  | ARM_CEXT_XSCALE)
71  struct generic_fmt {  #define ARM_ARCH_IWMMXT (ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT)
72      unsigned rest       :25;    /* the rest of the instruction */  
73      unsigned subtype    :1;     /* used to decide between block and branch */  #define FPU_FPA_EXT_V1   0x80000000     /* Base FPA instruction set.  */
74      unsigned type       :2;     /* one of TYPE_* */  #define FPU_FPA_EXT_V2   0x40000000     /* LFM/SFM.                   */
75      unsigned cond       :4;     /* one of COND_* defined above */  #define FPU_VFP_EXT_NONE 0x20000000     /* Use VFP word-ordering.     */
76  };  #define FPU_VFP_EXT_V1xD 0x10000000     /* Base VFP instruction set.  */
77    #define FPU_VFP_EXT_V1   0x08000000     /* Double-precision insns.    */
78  struct arith_fmt {  #define FPU_VFP_EXT_V2   0x04000000     /* ARM10E VFPr1.              */
79      unsigned operand2   :12;    /* #nn or rn or rn shift #m or rn shift rm */  #define FPU_MAVERICK     0x02000000     /* Cirrus Maverick.           */
80      unsigned dest       :4;     /* place where the answer goes */  #define FPU_NONE         0
81      unsigned operand1   :4;     /* first operand to instruction */  
82      unsigned set        :1;     /* == 1 means set processor flags */  #define FPU_ARCH_FPE     FPU_FPA_EXT_V1
83      unsigned opcode     :4;     /* one of OPCODE_* defined above */  #define FPU_ARCH_FPA    (FPU_ARCH_FPE | FPU_FPA_EXT_V2)
84      unsigned immed      :1;     /* operand2 is an immediate value */  
85      unsigned type       :2;     /* == TYPE_ARITHMETIC */  #define FPU_ARCH_VFP       FPU_VFP_EXT_NONE
86      unsigned cond       :4;     /* one of COND_* defined above */  #define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE)
87  };  #define FPU_ARCH_VFP_V1   (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1)
88    #define FPU_ARCH_VFP_V2   (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2)
89  struct ldr_str_fmt {  
90      unsigned offset     :12;    /* #nn or rn or rn shift #m */  #define FPU_ARCH_MAVERICK  FPU_MAVERICK
91      unsigned reg        :4;     /* destination for LDR, source for STR */  
92      unsigned base       :4;     /* base register */  /* Some useful combinations:  */
93      unsigned is_load    :1;     /* == 1 for LDR */  #define ARM_ANY         0x0000ffff      /* Any basic core.  */
94      unsigned writeback  :1;     /* == 1 means write back (base+offset) into base */  #define ARM_ALL         0x00ffffff      /* Any core + co-processor */
95      unsigned byte       :1;     /* == 1 means byte access else word */  #define CPROC_ANY       0x00ff0000      /* Any co-processor */
96      unsigned up         :1;     /* == 1 means add offset else subtract it */  #define FPU_ANY         0xff000000      /* Note this is ~ARM_ALL.  */
     unsigned pre_index  :1;     /* == 1 means [a,b] form else [a],b form */  
     unsigned immed      :1;     /* == 0 means immediate offset */  
     unsigned type       :2;     /* == TYPE_LDR_STR */  
     unsigned cond       :4;     /* one of COND_* defined above */  
 };  
   
 struct block_fmt {  
     unsigned mask       :16;    /* register mask */  
     unsigned base       :4;     /* register used as base of move */  
     unsigned is_load    :1;     /* == 1 for LDM */  
     unsigned writeback  :1;     /* == 1 means update base after move */  
     unsigned set        :1;     /* == 1 means set flags in pc if included in mask */  
     unsigned increment  :1;     /* == 1 means increment base register */  
     unsigned before     :1;     /* == 1 means inc/dec before each move */  
     unsigned is_block   :1;     /* == SUBTYPE_BLOCK */  
     unsigned type       :2;     /* == TYPE_BLOCK_BRANCH */  
     unsigned cond       :4;     /* one of COND_* defined above */  
 };  
   
 struct branch_fmt {  
     unsigned dest       :24;    /* destination of the branch */  
     unsigned link       :1;     /* branch with link (function call) */  
     unsigned is_branch  :1;     /* == SUBTYPE_BRANCH */  
     unsigned type       :2;     /* == TYPE_BLOCK_BRANCH */  
     unsigned cond       :4;     /* one of COND_* defined above */  
 };  
   
 #define ROUND_N         0  
 #define ROUND_P         1  
 #define ROUND_M         2  
 #define ROUND_Z         3  
   
 #define FLOAT2_MVF      0  
 #define FLOAT2_MNF      1  
 #define FLOAT2_ABS      2  
 #define FLOAT2_RND      3  
 #define FLOAT2_SQT      4  
 #define FLOAT2_LOG      5  
 #define FLOAT2_LGN      6  
 #define FLOAT2_EXP      7  
 #define FLOAT2_SIN      8  
 #define FLOAT2_COS      9  
 #define FLOAT2_TAN      10  
 #define FLOAT2_ASN      11  
 #define FLOAT2_ACS      12  
 #define FLOAT2_ATN      13  
   
 #define FLOAT3_ADF      0  
 #define FLOAT3_MUF      1  
 #define FLOAT3_SUF      2  
 #define FLOAT3_RSF      3  
 #define FLOAT3_DVF      4  
 #define FLOAT3_RDF      5  
 #define FLOAT3_POW      6  
 #define FLOAT3_RPW      7  
 #define FLOAT3_RMF      8  
 #define FLOAT3_FML      9  
 #define FLOAT3_FDV      10  
 #define FLOAT3_FRD      11  
 #define FLOAT3_POL      12  
   
 struct float2_fmt {  
     unsigned operand2   :3;     /* second operand */  
     unsigned immed      :1;     /* == 1 if second operand is a constant */  
     unsigned pad1       :1;     /* == 0 */  
     unsigned rounding   :2;     /* ROUND_* */  
     unsigned is_double  :1;     /* == 1 if precision is double (only if not extended) */  
     unsigned pad2       :4;     /* == 1 */  
     unsigned dest       :3;     /* destination */  
     unsigned is_2_op    :1;     /* == 1 if 2 operand ins */  
     unsigned operand1   :3;     /* first operand (only of is_2_op == 0) */  
     unsigned is_extended :1;    /* == 1 if precision is extended */  
     unsigned opcode     :4;     /* FLOAT2_* or FLOAT3_* depending on is_2_op */  
     unsigned must_be_2  :2;     /* == 2 */  
     unsigned type       :2;     /* == TYPE_SWI */  
     unsigned cond       :4;     /* COND_* */  
 };  
   
 struct swi_fmt {  
     unsigned argument   :24;    /* argument to SWI (syscall number) */  
     unsigned must_be_3  :2;     /* == 3 */  
     unsigned type       :2;     /* == TYPE_SWI */  
     unsigned cond       :4;     /* one of COND_* defined above */  
 };  
   
 union insn_fmt {  
     struct generic_fmt  generic;  
     struct arith_fmt    arith;  
     struct ldr_str_fmt  ldr_str;  
     struct block_fmt    block;  
     struct branch_fmt   branch;  
     struct swi_fmt      swi;  
     unsigned long       ins;  
 };  
   
 struct opcode {  
     unsigned long value, mask;  /* recognise instruction if (op&mask)==value */  
     char *assembler;            /* how to disassemble this instruction */  
 };  
   
 /* format of the assembler string :  
     
    %%                   %  
    %<bitfield>d         print the bitfield in decimal  
    %<bitfield>x         print the bitfield in hex  
    %<bitfield>r         print as an ARM register  
    %<bitfield>f         print a floating point constant if >7 else an fp register  
    %c                   print condition code (always bits 28-31)  
    %P                   print floating point precision in arithmetic insn  
    %Q                   print floating point precision in ldf/stf insn  
    %R                   print floating point rounding mode  
    %<bitnum>'c          print specified char iff bit is one  
    %<bitnum>`c          print specified char iff bit is zero  
    %<bitnum>?ab         print a if bit is one else print b  
    %p                   print 'p' iff bits 12-15 are 15  
    %o                   print operand2 (immediate or register + shift)  
    %a                   print address for ldr/str instruction  
    %b                   print branch destination  
    %A                   print address for ldc/stc/ldf/stf instruction  
    %m                   print register mask for ldm/stm instruction  
 */  
   
 static struct opcode opcodes[] = {  
     /* ARM instructions */  
     0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r",  
     0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r",  
     0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o",  
     0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o",  
     0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o",  
     0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o",  
     0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o",  
     0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o",  
     0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o",  
     0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o",  
     0x01000000, 0x0de00000, "tst%c%p %16-19r, %o",  
     0x01200000, 0x0de00000, "teq%c%p %16-19r, %o",  
     0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o",  
     0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o",  
     0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o",  
     0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o",  
     0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o",  
     0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o",  
     0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a",  
     0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a",  
     0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m",  
     0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^",  
     0x0a000000, 0x0e000000, "b%c%24'l %b",  
     0x0f000000, 0x0f000000, "swi%c %0-23x",  
     /* Floating point coprocessor instructions */  
     0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f",  
     0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f",  
     0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f",  
     0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f",  
     0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f",  
     0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f",  
     0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f",  
     0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f",  
     0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f",  
     0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f",  
     0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f",  
     0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f",  
     0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f",  
     0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f",  
     0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f",  
     0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r",  
     0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f",  
     0x0e200110, 0x0fff0fff, "wfs%c %12-15r",  
     0x0e300110, 0x0fff0fff, "rfs%c %12-15r",  
     0x0e400110, 0x0fff0fff, "wfc%c %12-15r",  
     0x0e500110, 0x0fff0fff, "rfc%c %12-15r",  
     0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f",  
     0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f",  
     0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f",  
     0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f",  
     0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A",  
     0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A",  
     /* Generic coprocessor instructions */  
     0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}",  
     0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",  
     0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",  
     0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A",  
     0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A",  
     /* the rest */  
     0x00000000, 0x00000000, "undefined instruction %0-31x",  
 };  
 #define N_OPCODES       (sizeof opcodes / sizeof opcodes[0])  

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