/[gcl]/gcl/binutils/include/gdb/sim-sh.h
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revision 1.1.1.1 by camm, Fri Aug 9 05:36:55 2002 UTC revision 1.1.1.1.20.1 by camm, Fri Sep 30 02:10:24 2005 UTC
# Line 1  Line 1 
1  /* This file defines the interface between the sh simulator and gdb.  /* This file defines the interface between the sh simulator and gdb.
2     Copyright (C) 2002 Free Software Foundation, Inc.     Copyright (C) 2000, 2002, 2004 Free Software Foundation, Inc.
3    
4  This file is part of GDB.  This file is part of GDB.
5    
# Line 27  extern "C" { // } Line 27  extern "C" { // }
27  /* The simulator makes use of the following register information. */  /* The simulator makes use of the following register information. */
28    
29  enum  enum
30    {  {
31      SIM_SH64_R0_REGNUM = 0,    SIM_SH_R0_REGNUM = 0,
32      SIM_SH64_SP_REGNUM = 15,    SIM_SH_R1_REGNUM,
33      SIM_SH64_PC_REGNUM = 64,    SIM_SH_R2_REGNUM,
34      SIM_SH64_SR_REGNUM = 65,    SIM_SH_R3_REGNUM,
35      SIM_SH64_SSR_REGNUM = 66,    SIM_SH_R4_REGNUM,
36      SIM_SH64_SPC_REGNUM = 67,    SIM_SH_R5_REGNUM,
37      SIM_SH64_TR0_REGNUM = 68,    SIM_SH_R6_REGNUM,
38      SIM_SH64_FPCSR_REGNUM = 76,    SIM_SH_R7_REGNUM,
39      SIM_SH64_FR0_REGNUM = 77    SIM_SH_R8_REGNUM,
40    };    SIM_SH_R9_REGNUM,
41      SIM_SH_R10_REGNUM,
42      SIM_SH_R11_REGNUM,
43      SIM_SH_R12_REGNUM,
44      SIM_SH_R13_REGNUM,
45      SIM_SH_R14_REGNUM,
46      SIM_SH_R15_REGNUM,
47      SIM_SH_PC_REGNUM,
48      SIM_SH_PR_REGNUM,
49      SIM_SH_GBR_REGNUM,
50      SIM_SH_VBR_REGNUM,
51      SIM_SH_MACH_REGNUM,
52      SIM_SH_MACL_REGNUM,
53      SIM_SH_SR_REGNUM,
54      SIM_SH_FPUL_REGNUM,
55      SIM_SH_FPSCR_REGNUM,
56      SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */
57      SIM_SH_FR1_REGNUM,
58      SIM_SH_FR2_REGNUM,
59      SIM_SH_FR3_REGNUM,
60      SIM_SH_FR4_REGNUM,
61      SIM_SH_FR5_REGNUM,
62      SIM_SH_FR6_REGNUM,
63      SIM_SH_FR7_REGNUM,
64      SIM_SH_FR8_REGNUM,
65      SIM_SH_FR9_REGNUM,
66      SIM_SH_FR10_REGNUM,
67      SIM_SH_FR11_REGNUM,
68      SIM_SH_FR12_REGNUM,
69      SIM_SH_FR13_REGNUM,
70      SIM_SH_FR14_REGNUM,
71      SIM_SH_FR15_REGNUM,
72      SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */
73      SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
74      SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */
75      SIM_SH_R1_BANK0_REGNUM,
76      SIM_SH_R2_BANK0_REGNUM,
77      SIM_SH_R3_BANK0_REGNUM,
78      SIM_SH_R4_BANK0_REGNUM,
79      SIM_SH_R5_BANK0_REGNUM,
80      SIM_SH_R6_BANK0_REGNUM,
81      SIM_SH_R7_BANK0_REGNUM,
82      SIM_SH_R0_BANK1_REGNUM,
83      SIM_SH_R1_BANK1_REGNUM,
84      SIM_SH_R2_BANK1_REGNUM,
85      SIM_SH_R3_BANK1_REGNUM,
86      SIM_SH_R4_BANK1_REGNUM,
87      SIM_SH_R5_BANK1_REGNUM,
88      SIM_SH_R6_BANK1_REGNUM,
89      SIM_SH_R7_BANK1_REGNUM,
90      SIM_SH_XF0_REGNUM,
91      SIM_SH_XF1_REGNUM,
92      SIM_SH_XF2_REGNUM,
93      SIM_SH_XF3_REGNUM,
94      SIM_SH_XF4_REGNUM,
95      SIM_SH_XF5_REGNUM,
96      SIM_SH_XF6_REGNUM,
97      SIM_SH_XF7_REGNUM,
98      SIM_SH_XF8_REGNUM,
99      SIM_SH_XF9_REGNUM,
100      SIM_SH_XF10_REGNUM,
101      SIM_SH_XF11_REGNUM,
102      SIM_SH_XF12_REGNUM,
103      SIM_SH_XF13_REGNUM,
104      SIM_SH_XF14_REGNUM,
105      SIM_SH_XF15_REGNUM,
106      SIM_SH_SGR_REGNUM,
107      SIM_SH_DBR_REGNUM,
108      SIM_SH4_NUM_REGS, /* 77 */
109    
110      /* sh[3]-dsp */
111      SIM_SH_DSR_REGNUM,
112      SIM_SH_A0G_REGNUM,
113      SIM_SH_A0_REGNUM,
114      SIM_SH_A1G_REGNUM,
115      SIM_SH_A1_REGNUM,
116      SIM_SH_M0_REGNUM,
117      SIM_SH_M1_REGNUM,
118      SIM_SH_X0_REGNUM,
119      SIM_SH_X1_REGNUM,
120      SIM_SH_Y0_REGNUM,
121      SIM_SH_Y1_REGNUM,
122      SIM_SH_MOD_REGNUM,
123      SIM_SH_RS_REGNUM,
124      SIM_SH_RE_REGNUM,
125      SIM_SH_R0_BANK_REGNUM,
126      SIM_SH_R1_BANK_REGNUM,
127      SIM_SH_R2_BANK_REGNUM,
128      SIM_SH_R3_BANK_REGNUM,
129      SIM_SH_R4_BANK_REGNUM,
130      SIM_SH_R5_BANK_REGNUM,
131      SIM_SH_R6_BANK_REGNUM,
132      SIM_SH_R7_BANK_REGNUM,
133      /* 109..127: room for expansion.  */
134      SIM_SH_TBR_REGNUM,
135      SIM_SH_IBNR_REGNUM,
136      SIM_SH_IBCR_REGNUM,
137      SIM_SH_BANK_REGNUM,
138      SIM_SH_BANK_MACL_REGNUM,
139      SIM_SH_BANK_GBR_REGNUM,
140      SIM_SH_BANK_PR_REGNUM,
141      SIM_SH_BANK_IVN_REGNUM,
142      SIM_SH_BANK_MACH_REGNUM
143    };
144    
145  enum  enum
146    {  {
147      SIM_SH64_NR_REGS = 141,  /* total number of architectural registers */    SIM_SH64_R0_REGNUM = 0,
148      SIM_SH64_NR_R_REGS = 64, /* number of general registers */    SIM_SH64_SP_REGNUM = 15,
149      SIM_SH64_NR_TR_REGS = 8, /* number of target registers */    SIM_SH64_PC_REGNUM = 64,
150      SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */    SIM_SH64_SR_REGNUM = 65,
151    };    SIM_SH64_SSR_REGNUM = 66,
152      SIM_SH64_SPC_REGNUM = 67,
153      SIM_SH64_TR0_REGNUM = 68,
154      SIM_SH64_FPCSR_REGNUM = 76,
155      SIM_SH64_FR0_REGNUM = 77
156    };
157    
158    enum
159    {
160      SIM_SH64_NR_REGS = 141,  /* total number of architectural registers */
161      SIM_SH64_NR_R_REGS = 64, /* number of general registers */
162      SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
163      SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */
164    };
165    
166  #ifdef __cplusplus  #ifdef __cplusplus
167  }  }

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