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/* This file defines the interface between the sh simulator and gdb. |
/* This file defines the interface between the sh simulator and gdb. |
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Copyright (C) 2002 Free Software Foundation, Inc. |
Copyright (C) 2000, 2002, 2004 Free Software Foundation, Inc. |
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This file is part of GDB. |
This file is part of GDB. |
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27 |
/* The simulator makes use of the following register information. */ |
/* The simulator makes use of the following register information. */ |
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enum |
enum |
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{ |
{ |
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SIM_SH64_R0_REGNUM = 0, |
SIM_SH_R0_REGNUM = 0, |
32 |
SIM_SH64_SP_REGNUM = 15, |
SIM_SH_R1_REGNUM, |
33 |
SIM_SH64_PC_REGNUM = 64, |
SIM_SH_R2_REGNUM, |
34 |
SIM_SH64_SR_REGNUM = 65, |
SIM_SH_R3_REGNUM, |
35 |
SIM_SH64_SSR_REGNUM = 66, |
SIM_SH_R4_REGNUM, |
36 |
SIM_SH64_SPC_REGNUM = 67, |
SIM_SH_R5_REGNUM, |
37 |
SIM_SH64_TR0_REGNUM = 68, |
SIM_SH_R6_REGNUM, |
38 |
SIM_SH64_FPCSR_REGNUM = 76, |
SIM_SH_R7_REGNUM, |
39 |
SIM_SH64_FR0_REGNUM = 77 |
SIM_SH_R8_REGNUM, |
40 |
}; |
SIM_SH_R9_REGNUM, |
41 |
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SIM_SH_R10_REGNUM, |
42 |
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SIM_SH_R11_REGNUM, |
43 |
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SIM_SH_R12_REGNUM, |
44 |
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SIM_SH_R13_REGNUM, |
45 |
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SIM_SH_R14_REGNUM, |
46 |
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SIM_SH_R15_REGNUM, |
47 |
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SIM_SH_PC_REGNUM, |
48 |
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SIM_SH_PR_REGNUM, |
49 |
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SIM_SH_GBR_REGNUM, |
50 |
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SIM_SH_VBR_REGNUM, |
51 |
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SIM_SH_MACH_REGNUM, |
52 |
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SIM_SH_MACL_REGNUM, |
53 |
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SIM_SH_SR_REGNUM, |
54 |
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SIM_SH_FPUL_REGNUM, |
55 |
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SIM_SH_FPSCR_REGNUM, |
56 |
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SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */ |
57 |
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SIM_SH_FR1_REGNUM, |
58 |
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SIM_SH_FR2_REGNUM, |
59 |
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SIM_SH_FR3_REGNUM, |
60 |
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SIM_SH_FR4_REGNUM, |
61 |
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SIM_SH_FR5_REGNUM, |
62 |
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SIM_SH_FR6_REGNUM, |
63 |
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SIM_SH_FR7_REGNUM, |
64 |
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SIM_SH_FR8_REGNUM, |
65 |
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SIM_SH_FR9_REGNUM, |
66 |
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SIM_SH_FR10_REGNUM, |
67 |
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SIM_SH_FR11_REGNUM, |
68 |
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SIM_SH_FR12_REGNUM, |
69 |
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SIM_SH_FR13_REGNUM, |
70 |
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SIM_SH_FR14_REGNUM, |
71 |
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SIM_SH_FR15_REGNUM, |
72 |
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SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */ |
73 |
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SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */ |
74 |
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SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */ |
75 |
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SIM_SH_R1_BANK0_REGNUM, |
76 |
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SIM_SH_R2_BANK0_REGNUM, |
77 |
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SIM_SH_R3_BANK0_REGNUM, |
78 |
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SIM_SH_R4_BANK0_REGNUM, |
79 |
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SIM_SH_R5_BANK0_REGNUM, |
80 |
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SIM_SH_R6_BANK0_REGNUM, |
81 |
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SIM_SH_R7_BANK0_REGNUM, |
82 |
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SIM_SH_R0_BANK1_REGNUM, |
83 |
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SIM_SH_R1_BANK1_REGNUM, |
84 |
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SIM_SH_R2_BANK1_REGNUM, |
85 |
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SIM_SH_R3_BANK1_REGNUM, |
86 |
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SIM_SH_R4_BANK1_REGNUM, |
87 |
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SIM_SH_R5_BANK1_REGNUM, |
88 |
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SIM_SH_R6_BANK1_REGNUM, |
89 |
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SIM_SH_R7_BANK1_REGNUM, |
90 |
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SIM_SH_XF0_REGNUM, |
91 |
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SIM_SH_XF1_REGNUM, |
92 |
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SIM_SH_XF2_REGNUM, |
93 |
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SIM_SH_XF3_REGNUM, |
94 |
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SIM_SH_XF4_REGNUM, |
95 |
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SIM_SH_XF5_REGNUM, |
96 |
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SIM_SH_XF6_REGNUM, |
97 |
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SIM_SH_XF7_REGNUM, |
98 |
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SIM_SH_XF8_REGNUM, |
99 |
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SIM_SH_XF9_REGNUM, |
100 |
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SIM_SH_XF10_REGNUM, |
101 |
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SIM_SH_XF11_REGNUM, |
102 |
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SIM_SH_XF12_REGNUM, |
103 |
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SIM_SH_XF13_REGNUM, |
104 |
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SIM_SH_XF14_REGNUM, |
105 |
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SIM_SH_XF15_REGNUM, |
106 |
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SIM_SH_SGR_REGNUM, |
107 |
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SIM_SH_DBR_REGNUM, |
108 |
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SIM_SH4_NUM_REGS, /* 77 */ |
109 |
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110 |
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/* sh[3]-dsp */ |
111 |
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SIM_SH_DSR_REGNUM, |
112 |
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SIM_SH_A0G_REGNUM, |
113 |
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SIM_SH_A0_REGNUM, |
114 |
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SIM_SH_A1G_REGNUM, |
115 |
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SIM_SH_A1_REGNUM, |
116 |
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SIM_SH_M0_REGNUM, |
117 |
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SIM_SH_M1_REGNUM, |
118 |
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SIM_SH_X0_REGNUM, |
119 |
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SIM_SH_X1_REGNUM, |
120 |
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SIM_SH_Y0_REGNUM, |
121 |
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SIM_SH_Y1_REGNUM, |
122 |
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SIM_SH_MOD_REGNUM, |
123 |
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SIM_SH_RS_REGNUM, |
124 |
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SIM_SH_RE_REGNUM, |
125 |
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SIM_SH_R0_BANK_REGNUM, |
126 |
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SIM_SH_R1_BANK_REGNUM, |
127 |
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SIM_SH_R2_BANK_REGNUM, |
128 |
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SIM_SH_R3_BANK_REGNUM, |
129 |
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SIM_SH_R4_BANK_REGNUM, |
130 |
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SIM_SH_R5_BANK_REGNUM, |
131 |
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SIM_SH_R6_BANK_REGNUM, |
132 |
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SIM_SH_R7_BANK_REGNUM, |
133 |
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/* 109..127: room for expansion. */ |
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SIM_SH_TBR_REGNUM, |
135 |
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SIM_SH_IBNR_REGNUM, |
136 |
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SIM_SH_IBCR_REGNUM, |
137 |
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SIM_SH_BANK_REGNUM, |
138 |
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SIM_SH_BANK_MACL_REGNUM, |
139 |
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SIM_SH_BANK_GBR_REGNUM, |
140 |
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SIM_SH_BANK_PR_REGNUM, |
141 |
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SIM_SH_BANK_IVN_REGNUM, |
142 |
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SIM_SH_BANK_MACH_REGNUM |
143 |
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}; |
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enum |
enum |
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{ |
{ |
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SIM_SH64_NR_REGS = 141, /* total number of architectural registers */ |
SIM_SH64_R0_REGNUM = 0, |
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SIM_SH64_NR_R_REGS = 64, /* number of general registers */ |
SIM_SH64_SP_REGNUM = 15, |
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SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ |
SIM_SH64_PC_REGNUM = 64, |
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SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ |
SIM_SH64_SR_REGNUM = 65, |
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}; |
SIM_SH64_SSR_REGNUM = 66, |
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SIM_SH64_SPC_REGNUM = 67, |
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SIM_SH64_TR0_REGNUM = 68, |
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SIM_SH64_FPCSR_REGNUM = 76, |
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SIM_SH64_FR0_REGNUM = 77 |
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}; |
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enum |
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{ |
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SIM_SH64_NR_REGS = 141, /* total number of architectural registers */ |
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SIM_SH64_NR_R_REGS = 64, /* number of general registers */ |
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SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ |
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SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ |
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}; |
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#ifdef __cplusplus |
#ifdef __cplusplus |
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} |
} |