132 |
* Set it to zero if integer division is too hard to be performed |
* Set it to zero if integer division is too hard to be performed |
133 |
* inline using a simple opcode. |
* inline using a simple opcode. |
134 |
*/ |
*/ |
135 |
#define MD_HAS_INT_DIVISION 0 /* TODO */ |
#define MD_HAS_INT_DIVISION 1 |
136 |
|
|
137 |
/* |
/* |
138 |
* Set to 1 if 64-bit register pairs are stored in little-endian order. |
* Set to 1 if 64-bit register pairs are stored in little-endian order. |
340 |
#define md_mul_reg_reg_word_32(inst,reg1,reg2) \ |
#define md_mul_reg_reg_word_32(inst,reg1,reg2) \ |
341 |
ppc_alu_reg_dss((inst), PPC_MUL, (reg1), (reg1), (reg2)) |
ppc_alu_reg_dss((inst), PPC_MUL, (reg1), (reg1), (reg2)) |
342 |
#define md_div_reg_reg_word_32(inst,reg1,reg2) \ |
#define md_div_reg_reg_word_32(inst,reg1,reg2) \ |
343 |
do { ; } while (0) |
ppc_alu_reg_dss((inst), PPC_DIV, (reg1), (reg1), (reg2)) |
344 |
#define md_udiv_reg_reg_word_32(inst,reg1,reg2) \ |
#define md_udiv_reg_reg_word_32(inst,reg1,reg2) \ |
345 |
do { ; } while (0) |
ppc_alu_reg_dss((inst), PPC_DIV_UN , (reg1), (reg1), (reg2)) |
346 |
#define md_rem_reg_reg_word_32(inst,reg1,reg2) \ |
#define md_rem_reg_reg_word_32(inst,reg1,reg2) \ |
347 |
do { ; } while (0) |
do {\ |
348 |
|
ppc_alu_reg_dss((inst), PPC_DIV, PPC_WORK, (reg1), (reg2));\ |
349 |
|
ppc_alu_reg_dss((inst), PPC_MUL, PPC_WORK, PPC_WORK, (reg2));\ |
350 |
|
ppc_alu_reg_dss((inst), PPC_SUBF, (reg1), PPC_WORK, (reg1));\ |
351 |
|
} while (0) |
352 |
#define md_urem_reg_reg_word_32(inst,reg1,reg2) \ |
#define md_urem_reg_reg_word_32(inst,reg1,reg2) \ |
353 |
do { ; } while (0) |
do {\ |
354 |
|
ppc_alu_reg_dss((inst), PPC_DIV_UN, PPC_WORK, (reg1), (reg2));\ |
355 |
|
ppc_alu_reg_dss((inst), PPC_MUL, PPC_WORK, PPC_WORK, (reg2));\ |
356 |
|
ppc_alu_reg_dss((inst), PPC_SUBF, (reg1), PPC_WORK, (reg1));\ |
357 |
|
} while (0) |
358 |
#define md_neg_reg_word_32(inst,reg) \ |
#define md_neg_reg_word_32(inst,reg) \ |
359 |
ppc_alu_reg_ds((inst), PPC_NEG, (reg), (reg)) |
ppc_alu_reg_ds((inst), PPC_NEG, (reg), (reg)) |
360 |
#define md_and_reg_reg_word_32(inst,reg1,reg2) \ |
#define md_and_reg_reg_word_32(inst,reg1,reg2) \ |
451 |
{ \ |
{ \ |
452 |
/* Jump to the contents of the specified PC */ \ |
/* Jump to the contents of the specified PC */ \ |
453 |
ppc_load_membase(inst, PPC_WORK, MD_REG_PC, 0); \ |
ppc_load_membase(inst, PPC_WORK, MD_REG_PC, 0); \ |
|
ppc_jump_reg(inst, PPC_WORK); \ |
|
454 |
} \ |
} \ |
455 |
else \ |
else \ |
456 |
{ \ |
{ \ |
457 |
ppc_jump(inst, label);\ |
ppc_mov_reg_imm(inst, PPC_WORK, (label));\ |
458 |
} \ |
} \ |
459 |
|
ppc_jump_reg(inst, PPC_WORK); \ |
460 |
} while (0) |
} while (0) |
461 |
|
|
462 |
/* |
/* |