42 |
count zeros and check for bit no 5 |
count zeros and check for bit no 5 |
43 |
*/ |
*/ |
44 |
ppc_alu_reg_ds(inst, PPC_CNTLZ, reg, reg); |
ppc_alu_reg_ds(inst, PPC_CNTLZ, reg, reg); |
45 |
/* srwi reg, PPC_WORK, 5 */ |
/* srwi reg, reg, 5 */ |
46 |
ppc_alu_rlwinm(inst, reg, reg, 32-5, 5, 31); |
ppc_alu_rlwinm(inst, reg, reg, 32-5, 5, 31); |
47 |
} |
} |
48 |
break; |
break; |
92 |
return inst; |
return inst; |
93 |
} |
} |
94 |
|
|
95 |
|
/* |
96 |
|
* li dreg, 1 |
97 |
|
* bgt L3 |
98 |
|
* blt L2 |
99 |
|
* li dreg, 0 |
100 |
|
* b L3 |
101 |
|
* L2: |
102 |
|
* li dreg, -1 |
103 |
|
* L3: |
104 |
|
*/ |
105 |
|
|
106 |
md_inst_ptr _md_ppc_setcmp(md_inst_ptr inst, int dreg) |
md_inst_ptr _md_ppc_setcmp(md_inst_ptr inst, int dreg) |
107 |
{ |
{ |
108 |
TODO_trap(inst); |
md_inst_ptr patch1, patch2, patch3; |
109 |
|
|
110 |
|
ppc_mov_reg_imm(inst, dreg, 1); |
111 |
|
|
112 |
|
patch1 = inst; |
113 |
|
ppc_branch(inst, PPC_CC_GT, 0); |
114 |
|
|
115 |
|
patch2 = inst; |
116 |
|
ppc_branch(inst, PPC_CC_LT, 0); |
117 |
|
|
118 |
|
ppc_mov_reg_imm(inst, dreg, 0); |
119 |
|
|
120 |
|
patch3 = inst; |
121 |
|
ppc_jump(inst, 0); |
122 |
|
|
123 |
|
ppc_patch(patch2, inst); |
124 |
|
ppc_mov_reg_imm(inst, dreg, -1); |
125 |
|
|
126 |
|
ppc_patch(patch1, inst); |
127 |
|
ppc_patch(patch3, inst); |
128 |
|
|
129 |
return inst; |
return inst; |
130 |
} |
} |
131 |
#endif /* CVM_PPC */ |
#endif /* CVM_PPC */ |