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/* Interrupt vectors (byte addresses) */ |
/* Interrupt vectors (byte addresses) */ |
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#define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 0 */ |
/* External Interrupt Request 0 */ |
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#define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 1 */ |
#define INT0_vect _VECTOR(1) |
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#define SIG_INTERRUPT2 _VECTOR(3) /* External Interrupt Request 2 */ |
#define SIG_INTERRUPT0 _VECTOR(1) |
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#define SIG_PIN_CHANGE0 _VECTOR(4) /* Pin Change Interrupt Request 0 */ |
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#define SIG_PIN_CHANGE1 _VECTOR(5) /* Pin Change Interrupt Request 1 */ |
/* External Interrupt Request 1 */ |
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#define SIG_INPUT_CAPTURE3 _VECTOR(6) /* Timer/Counter3 Capture Event */ |
#define INT1_vect _VECTOR(2) |
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#define SIG_OUTPUT_COMPARE3A _VECTOR(7) /* Timer/Counter3 Compare Match A */ |
#define SIG_INTERRUPT1 _VECTOR(2) |
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#define SIG_OUTPUT_COMPARE3B _VECTOR(8) /* Timer/Counter3 Compare Match B */ |
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#define SIG_OVERFLOW3 _VECTOR(9) /* Timer/Counter3 Overflow */ |
/* External Interrupt Request 2 */ |
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#define SIG_OUTPUT_COMPARE2 _VECTOR(10) /* Timer/Counter2 Compare Match */ |
#define INT2_vect _VECTOR(3) |
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#define SIG_OVERFLOW2 _VECTOR(11) /* Timer/Counter2 Overflow */ |
#define SIG_INTERRUPT2 _VECTOR(3) |
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#define SIG_INPUT_CAPTURE1 _VECTOR(12) /* Timer/Counter1 Capture Event */ |
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#define SIG_OUTPUT_COMPARE1A _VECTOR(13) /* Timer/Counter1 Compare Match A */ |
/* Pin Change Interrupt Request 0 */ |
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#define SIG_OUTPUT_COMPARE1B _VECTOR(14) /* Timer/Counter1 Compare Match B */ |
#define PCINT0_vect _VECTOR(4) |
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#define SIG_OVERFLOW1 _VECTOR(15) /* Timer/Counter1 Overflow */ |
#define SIG_PIN_CHANGE0 _VECTOR(4) |
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#define SIG_OUTPUT_COMPARE0 _VECTOR(16) /* Timer/Counter0 Compare Match */ |
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#define SIG_OVERFLOW0 _VECTOR(17) /* Timer/Counter0 Overflow */ |
/* Pin Change Interrupt Request 1 */ |
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#define SIG_SPI _VECTOR(18) /* Serial Transfer Complete */ |
#define PCINT1_vect _VECTOR(5) |
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#define SIG_USART0_RECV _VECTOR(19) /* USART0,Rx Complete */ |
#define SIG_PIN_CHANGE1 _VECTOR(5) |
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#define SIG_USART1_RECV _VECTOR(20) /* USART1,Rx Complete */ |
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#define SIG_USART0_DATA _VECTOR(21) /* USART0 Data Register Empty */ |
/* Timer/Counter3 Capture Event */ |
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#define SIG_USART1_DATA _VECTOR(22) /* USART1 Data Register Empty */ |
#define TIMER3_CAPT_vect _VECTOR(6) |
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#define SIG_USART0_TRANS _VECTOR(23) /* USART0,Tx Complete */ |
#define SIG_INPUT_CAPTURE3 _VECTOR(6) |
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#define SIG_USART1_TRANS _VECTOR(24) /* USART1,Tx Complete */ |
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#define SIG_EEPROM_READY _VECTOR(25) /* EEPROM Ready */ |
/* Timer/Counter3 Compare Match A */ |
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#define SIG_COMPARATOR _VECTOR(26) /* Analog Comparator */ |
#define TIMER3_COMPA_vect _VECTOR(7) |
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#define SIG_SPM_READY _VECTOR(27) /* Store Program Memory Ready */ |
#define SIG_OUTPUT_COMPARE3A _VECTOR(7) |
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/* Timer/Counter3 Compare Match B */ |
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#define TIMER3_COMPB_vect _VECTOR(8) |
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#define SIG_OUTPUT_COMPARE3B _VECTOR(8) |
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/* Timer/Counter3 Overflow */ |
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#define TIMER3_OVF_vect _VECTOR(9) |
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#define SIG_OVERFLOW3 _VECTOR(9) |
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/* Timer/Counter2 Compare Match */ |
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#define TIMER2_COMP_vect _VECTOR(10) |
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#define SIG_OUTPUT_COMPARE2 _VECTOR(10) |
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/* Timer/Counter2 Overflow */ |
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#define TIMER2_OVF_vect _VECTOR(11) |
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#define SIG_OVERFLOW2 _VECTOR(11) |
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/* Timer/Counter1 Capture Event */ |
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#define TIMER1_CAPT_vect _VECTOR(12) |
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#define SIG_INPUT_CAPTURE1 _VECTOR(12) |
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/* Timer/Counter1 Compare Match A */ |
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#define TIMER1_COMPA_vect _VECTOR(13) |
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#define SIG_OUTPUT_COMPARE1A _VECTOR(13) |
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/* Timer/Counter Compare Match B */ |
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#define TIMER1_COMPB_vect _VECTOR(14) |
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#define SIG_OUTPUT_COMPARE1B _VECTOR(14) |
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/* Timer/Counter1 Overflow */ |
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#define TIMER1_OVF_vect _VECTOR(15) |
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#define SIG_OVERFLOW1 _VECTOR(15) |
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/* Timer/Counter0 Compare Match */ |
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#define TIMER0_COMP_vect _VECTOR(16) |
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#define SIG_OUTPUT_COMPARE0 _VECTOR(16) |
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/* Timer/Counter0 Overflow */ |
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#define TIMER0_OVF_vect _VECTOR(17) |
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#define SIG_OVERFLOW0 _VECTOR(17) |
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/* SPI Serial Transfer Complete */ |
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#define SPI_STC_vect _VECTOR(18) |
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#define SIG_SPI _VECTOR(18) |
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/* USART0, Rx Complete */ |
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#define USART0_RXC_vect _VECTOR(19) |
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#define SIG_USART0_RECV _VECTOR(19) |
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/* USART1, Rx Complete */ |
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#define USART1_RXC_vect _VECTOR(20) |
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#define SIG_USART1_RECV _VECTOR(20) |
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/* USART0 Data register Empty */ |
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#define USART0_UDRE_vect _VECTOR(21) |
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#define SIG_USART0_DATA _VECTOR(21) |
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/* USART1, Data register Empty */ |
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#define USART1_UDRE_vect _VECTOR(22) |
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#define SIG_USART1_DATA _VECTOR(22) |
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/* USART0, Tx Complete */ |
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#define USART0_TXC_vect _VECTOR(23) |
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#define SIG_USART0_TRANS _VECTOR(23) |
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/* USART1, Tx Complete */ |
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#define USART1_TXC_vect _VECTOR(24) |
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#define SIG_USART1_TRANS _VECTOR(24) |
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/* EEPROM Ready */ |
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#define EE_RDY_vect _VECTOR(25) |
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#define SIG_EEPROM_READY _VECTOR(25) |
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/* Analog Comparator */ |
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#define ANA_COMP_vect _VECTOR(26) |
273 |
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#define SIG_COMPARATOR _VECTOR(26) |
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/* Store Program Memory Read */ |
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#define SPM_RDY_vect _VECTOR(27) |
277 |
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#define SIG_SPM_READY _VECTOR(27) |
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280 |
#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */ |
#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */ |
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