30 |
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31 |
/* $Id$ */ |
/* $Id$ */ |
32 |
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33 |
/* avr/io90pwmx.h - definitions for AT90PWM2 and AT90PWM3 */ |
/* avr/io90pwmx.h - definitions for AT90PWM2(B) and AT90PWM3(B) */ |
34 |
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35 |
#ifndef _AVR_IO90PWMX_H_ |
#ifndef _AVR_IO90PWMX_H_ |
36 |
#define _AVR_IO90PWMX_H_ 1 |
#define _AVR_IO90PWMX_H_ 1 |
982 |
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983 |
/* PSC 0 Input Capture Registers */ |
/* PSC 0 Input Capture Registers */ |
984 |
#define PICR0 _SFR_MEM16(0xDE) |
#define PICR0 _SFR_MEM16(0xDE) |
985 |
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986 |
#define PICR0L _SFR_MEM8(0xDE) |
#define PICR0L _SFR_MEM8(0xDE) |
987 |
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988 |
#define PICR0H _SFR_MEM8(0xDF) |
#define PICR0H _SFR_MEM8(0xDF) |
989 |
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#define PCST0 7 /* PSC Capture Software Trig bit */ |
990 |
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/* not implemented on AT90PWM2/AT90PWM3 */ |
991 |
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992 |
/* PSC 1 Synchro and Output Configuration */ |
/* PSC 1 Synchro and Output Configuration */ |
993 |
#define PSOC1 _SFR_MEM8(0xE0) |
#define PSOC1 _SFR_MEM8(0xE0) |
1066 |
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1067 |
/* PSC 1 Input Capture Registers */ |
/* PSC 1 Input Capture Registers */ |
1068 |
#define PICR1 _SFR_MEM16(0xEE) |
#define PICR1 _SFR_MEM16(0xEE) |
1069 |
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1070 |
#define PICR1L _SFR_MEM8(0xEE) |
#define PICR1L _SFR_MEM8(0xEE) |
1071 |
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1072 |
#define PICR1H _SFR_MEM8(0xEF) |
#define PICR1H _SFR_MEM8(0xEF) |
1073 |
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#define PCST1 7 /* PSC Capture Software Trig bit */ |
1074 |
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/* not implemented on AT90PWM2/AT90PWM3 */ |
1075 |
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1076 |
/* PSC 2 Synchro and Output Configuration */ |
/* PSC 2 Synchro and Output Configuration */ |
1077 |
#define PSOC2 _SFR_MEM8(0xF0) |
#define PSOC2 _SFR_MEM8(0xF0) |
1167 |
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1168 |
/* PSC 2 Input Capture Registers */ |
/* PSC 2 Input Capture Registers */ |
1169 |
#define PICR2 _SFR_MEM16(0xFE) |
#define PICR2 _SFR_MEM16(0xFE) |
1170 |
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1171 |
#define PICR2L _SFR_MEM8(0xFE) |
#define PICR2L _SFR_MEM8(0xFE) |
1172 |
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1173 |
#define PICR2H _SFR_MEM8(0xFF) |
#define PICR2H _SFR_MEM8(0xFF) |
1174 |
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#define PCST2 7 /* PSC Capture Software Trig bit */ |
1175 |
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/* not implemented on AT90PWM2/AT90PWM3 */ |
1176 |
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1177 |
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1178 |
/* Interrupt vectors */ |
/* Interrupt vectors */ |