### GNU MAKE BUG REPORT: undefined variables and leading whitespace rule ### # # Running the test cases: # Setup: # touch larry.cc curly.cc moe.cc; sleep 1; touch larry.o curly.o moe.o # # Display the discrepancy: # rm -f libsuccess.a; make -f stooges.mk success # rm -f libfail.a; make -f stooges.mk fail # ########################################################################### # Enumerate source files: CCSRC.c = CCCSRC.cc = larry.cc curly.cc moe.cc # Compute the object files: ###### # ISSUE: The order of catenation affects conformance to GNU Make Manual, Section # 6.5, Setting Variables: "Whitespace ... immediately after the ‘=’ is ignored." # OBJECTS_FAIL gets a leading space (the space following the undefined CCSRCs). # This space disrupts the libfail.a pre-requisite. Re-scanning the definition # after variable substitution would solve this? # NOTE: make v3.81 behaves correctly. ###### OBJECTS_FAIL = $(CCSRC.c:.c=.o) $(CCCSRC.cc:.cc=.o) OBJECTS_SUCCESS = $(CCCSRC.cc:.cc=.o) $(CCSRC.c:.c=.o) success: printS libsuccess.a($(OBJECTS_SUCCESS)) fail: printF libfail.a($(OBJECTS_FAIL)) .PHONY: printF printS printS: @echo ""; echo "== SUCCESS =========="; @echo "CCSRC.c=<$(CCSRC.c)>"; @echo "CCCSRC.cc=<$(CCCSRC.cc)>"; @echo "OBJECTS=<$(OBJECTS_SUCCESS)>"; @echo "target=lib.a($(OBJECT_SUCCESS))"; printF: @echo ""; echo "== FAIL =========="; @echo "CCSRC.c=<$(CCSRC.c)>"; @echo "CCCSRC.cc=<$(CCCSRC.cc)>"; @echo "OBJECTS=<$(OBJECTS_FAIL)> - ** NOTE the LEADING SPACE **"; @echo "target=lib.a($(OBJECT_FAIL))";